Figure 26.3. Flashcon: Jtag Flash Control Register - Silicon Laboratories C8051F120 Manual

Figure 26.3. FLASHCON: JTAG Flash Control Register

SFLE WRMD2 WRMD1
Bit7 Bit6
This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT
Register.
Bit7: SFLE: Scratchpad FLASH Memory Access Enable
When this bit is set, FLASH reads and writes are directed to the two 128-byte Scratchpad FLASH
sectors. When SFLE is set to logic 1, FLASH accesses out of the address range 0x00-0xFF should not
be attempted (with the exception of address 0x400, which can be used to simultaneously erase both
Scratchpad areas). Reads/Writes out of this range will yield undefined results.
0: FLASH access directed to the 128k byte Program/Data FLASH sector.
1: FLASH access directed to the two 128 byte Scratchpad sectors.
Bits6-4: WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASHDAT
Register per the following values:
000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise ignored.
001: A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing
the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x1FBFE - 0x1FBFF, the entire user space
will be erased (i.e. entire Flash memory except for Reserved area 0x1FC00 - 0x1FFFF).
(All other values for WRMD2-0 are reserved.)
Bits3-0: RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads from the FLASHDAT
Register per the following values:
0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise ignored.
0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no
operation is currently active. This mode is used for block reads.
WRMD0 RDMD3
Bit5 Bit4 Bit3
Rev. 1.2
C8051F120/1/2/3/4/5/6/7
RDMD2 RDMD1 RDMD0
Bit2 Bit1
Reset Value
00000000
Bit0
319