Silicon Laboratories C8051F120 Manual page 142

C8051F120/1/2/3/4/5/6/7
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address
SPI0CKR 0x9D
SPI0CN 0xF8
SPI0DAT 0x9B
SSTA0 0x91
TCON 0x88
TH0 0x8C
TH1 0x8D
TL0 0x8A
TL1 0x8B
TMOD 0x89
TMR2CF 0xC9
TMR2CN 0xC8
TMR2H 0xCD
TMR2L 0xCC
TMR3CF 0xC9
TMR3CN 0xC8
TMR3H 0xCD
TMR3L 0xCC
TMR4CF 0xC9
TMR4CN 0xC8
TMR4H 0xCD
TMR4L 0xCC
WDTCN 0xFF
XBR0 0xE1
XBR1 0xE2
XBR2 0xE3
* Refers to a register in the C8051F120/1/4/5 only.
** Refers to a register in the C8051F122/3/6/7 only.
† Refers to a register in the C8051F120/2/4/6 only.
†† Refers to a register in the C8051F121/3/5/7 only.
142
Table 12.3. Special Function Registers
SFR
Description
Page
0 SPI Clock Rate Control
0 SPI Control
0 SPI Data
0 UART 0 Status
0 Timer/Counter Control
0 Timer/Counter 0 High Byte
0 Timer/Counter 1 High Byte
0 Timer/Counter 0 Low Byte
0 Timer/Counter 1 Low Byte
0 Timer/Counter Mode
0 Timer/Counter 2 Configuration
0 Timer/Counter 2 Control
0 Timer/Counter 2 High Byte
0 Timer/Counter 2 Low Byte
1 Timer 3 Configuration
1 Timer 3 Control
1 Timer 3 High Byte
1 Timer 3 Low Byte
2 Timer/Counter 4 Configuration
2 Timer/Counter 4 Control
2 Timer/Counter 4 High Byte
2 Timer/Counter 4 Low Byte
All Pages Watchdog Timer Control
F Port I/O Crossbar Control 0
F Port I/O Crossbar Control 1
F Port I/O Crossbar Control 2
Rev. 1.2
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