Figure 24.6. Ckcon: Clock Control Register - Silicon Laboratories C8051F120 Manual

Figure 24.6. CKCON: Clock Control Register

R/W R/W
- -
Bit7 Bit6
Bits7-5: UNUSED. Read = 000b, Write = don't care.
Bit4: T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.
Bit3: T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2: UNUSED. Read = 0b, Write = don't care.
Bits1-0: SCA1-SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use
prescaled clock inputs.
SCA1 SCA0
0 0
0 1
1 0
1 1
† Note: External clock divided by 8 is synchronized with the system clock.
R/W R/W R/W
- T1M T0M
Bit5 Bit4 Bit3
Prescaled Clock
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8†
Rev. 1.2
C8051F120/1/2/3/4/5/6/7
R/W R/W
- SCA1 SCA0
Bit2 Bit1
SFR Address:
R/W Reset Value
00000000
Bit0
0x8E
SFR Page: 0
291