Stat2 Register; Data Register - PEP Modular Computers Modular Computers RS485 User Manual

Chapter 6 Communications Modules
Interrupt pending flags (IP0 - IP4) are set by the interrupt source if the
corresponding line is not masked in the CTRL1 register. All flags are
cleared when the STAT1 register is read.

6.2.7.9 STAT2 Register

S T 2 - 7
unused
PE
TC
ER1 current status of end-of-range switch 1
ER2 current status of end-of-range switch 2
MH
The MH flag is set internally as soon as the encoder reaches the preset
register value with the flag being cleared immediately the status is read.
This feature is intended for use with the board in automatic mode to allow
slow polling of the status registers while ensuring that a match is not lost.

6.2.7.10 Data Register

The data register, cleared after a power-on reset is a 24-bit register containing
the result of the last encoder reading. When using encoders with less than 24-
bit data, the result is always aligned from the lowest significant bit and the
used upper bits are always cleared.
October 01, 1996
S T 2 - 6 S T 2 - 5
unused unused
parity error on last transmission (True/False)
transmission complete (True/False)
comparison match (True/False)
©1996 PEP Modular Computers GmbH
SMART I/O User's Manual
Note
S T 2 - 4 S T 2 - 3
MH ER2
Note
S T 2 - 2 S T 2 - 1
ER1 TC
Page 6 - 25
6