Compare Register; Identification Register; Status Register; Stat1 Register - PEP Modular Computers Modular Computers RS485 User Manual

SMART I/O User's Manual

6.2.7.5 Compare Register

This 24-bit register indicates the comparison value and is cleared after a
power-on reset.

6.2.7.6 Identification Register

The identification register is read only and fixed at a value of $81.

6.2.7.7 Status Register

The 16-bit status register is divided into two sub-registers which are partly
cleared after a power-on reset and show:
• IP : Interrupt Pending flags
• PE : Parity Error
• TC : Transmission Complete
• OL : Open Line
IP, PE, TC, OL, DF and MH flags are cleared after a reset. ER1 and ER2
represent the current hardware condition

6.2.7.8 STAT1 Register

S T 1 - 7 S T 1 - 6
OL unused
IP0-PE
IP1-TC
IP2-ER1
IP3-ER2
IP4-MH
DF
OL
Page 6- 24
S T 1 - 5 S T 1 - 4
DF IP4-MH
interrupt pending on parity error
interrupt pending on transmission complete
interrupt pending on end-of-range switch 1
interrupt pending on end-of-range switch 2
interrupt pending on comparison match
SSI data flow (True/False)
open line (True/False)
©1996 PEP Modular Computers GmbH
Chapter 6 Communications Modules
• DF : Data Flow
• ER1 : End-of-Range 1
• ER2 : End-of-Range 2
• MH : Match
S T 1 - 3 S T 1 - 2
IP3-ER2 IP2-ER1
S T 1 - 1
IP1-TC
October 01, 1996