Graphics And Memory Controller Hub (815-B0) - Kontron CP6500-V User Manual

CP6500-V
2.1.4

Graphics and Memory Controller Hub (815-B0)

The 815-B0 Graphics Memory Controller Hub (GMCH) is a highly integrated hub that provides
the CPU interface, the SDRAM system memory interface, a hub link interface to the ICH4 and
an internal graphics.
Graphics and Memory Controller Hub Feature Set
Host Interface
The 815-B0 is optimized for the Intel Celeron microprocessor. The chipset supports a Proces-
sor Side Bus (PSB) frequency of up to 133 MHz using 1.25 V AGTL signalling. Single-ended
AGTL termination is supported for single-processor configurations. The AGTL bus supports
32-bit host addressing for decoding up to 4 GB memory address space.
System Memory Interface
The 815-B0 integrates a system memory SDRAM controller with a 64-bit wide interface without
ECC. The chipset supports Single Data Rate (SDR) SDRAM for system memory with 64 Mbit,
128 Mbit, 256 Mbit and 512 Mbit SDRAM devices.
815-B0 Graphics Controller
The 815-B0 includes a highly integrated graphics accelerator decoding delivering high perfor-
mance 3D and 2D video capabilities. The internal graphics controller provides interfaces for a
standard progressive scan monitor, TV-Out device, and TMDS transmitter. These interfaces
are only active when running in internal graphics mode.
The advantage of the internal graphics solution is the price, the integration reduces the number
of the components and design complexity.
The disadvantage of the internal graphics controller is the shared memory architecture, which
results in a lower memory performance for the processor. To avoid memory conflicts with the
processor, the maximum VGA resolution is limited to 1600 x 1200 pixel with 256 colors and
60 Hz.
2.1.5 I/O Controller Hub ICH4
The ICH4 is a highly integrated multifunctional I/O Controller Hub that provides the interface to
the PCI Bus, and integrates many of the functions needed in today's PC platforms, such as Ul-
tra DMA 100/33 controller, USB host controller supporting USB 2.0, LPC interface and FWH
Flash BIOS interface controller. The ICH4 communicates with the host controller over a dedi-
cated hub interface.
The I/O Controller Hub Feature set comprises:
• PCI 2.2 interface with 32-bit/33 MHz and eight IRQ inputs
• Bus Master EIDE controller UltraDMA 100/33
• Up to four USB 2.0
• Hub interface for a 815-B0 chipset
• FWH interface
• LPC interface
• RTC controller
ID 28945, Rev. 01 © 2005 Kontron Modular Computers GmbH
Functional Description
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