Clock Interrupt Register (Rcc_Cir) - ST STM32F101xx Reference Manual

Connectivity line devices: reset and clock control (RCC)
Bits 1:0 SW[1:0]: System clock Switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Not allowed
8.3.3

Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
PLL3 PLL2 PLL
RDYIE RDYIE RDYIE
Res.
rw rw
Bits 31:24 Reserved, always read as 0.
Bit 23 CSSC: Clock security system interrupt clear
Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear
Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear
Bit 20 PLLRDYC: PLL ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
134/1096
28 27 26 25
Reserved
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
This bit is set by software to clear the PLL3RDYF flag.
0: No effect
1: Clear PLL3RDYF flag
This bit is set by software to clear the PLL2RDYF flag.
0: No effect
1: Clear PLL2RDYF flag
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Doc ID 13902 Rev 12
24 23 22 21
PLL3 PLL2
CSSC
RDYC RDYC
w w w
8 7 6 5
LSI PLL3 PLL2
CSSF
RDYIE RDYF RDYF
rw r r
20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w
4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r r
RM0008
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r