Figure 2. System Architecture In Connectivity Line Devices - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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Table of Contents

Memory and bus architecture

In connectivity line devices the main system consists of:

Five masters:

Three slaves:

These are interconnected using a multilayer AHB bus architecture as shown in

This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory

instruction interface. Prefetching is performed on this bus.

Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)

GP-DMA1 & 2 (general-purpose DMA)

Ethernet DMA

Internal SRAM

Internal Flash memory

AHB to APB bridges (AHB to APBx), which connect all the APB peripherals

System architecture in connectivity line devices

Ethernet MAC

Doc ID 13902 Rev 12

Reset & clock

control (RCC)

AHB system bus