Gpio Registers; Port Configuration Register Low (Gpiox_Crl) (X=A..g - ST STM32F101xx Reference Manual

RM0008
9.2

GPIO registers

Refer to
The peripheral registers have to be accessed by words (32-bit).
9.2.1

Port configuration register low (GPIOx_CRL) (x=A..G)

Address offset: 0x00
Reset value: 0x4444 4444
31 30 29 28
CNF7[1:0] MODE7[1:0]
rw rw rw rw
15 14 13 12
CNF3[1:0] MODE3[1:0]
rw rw rw rw
Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 0 .. 7)
23:22, 19:18, 15:14,
These bits are written by software to configure the corresponding I/O port.
11:10, 7:6, 3:2
Refer to
In input mode (MODE[1:0]=00):
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0]
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 0 .. 7)
21:20, 17:16, 13:12,
These bits are written by software to configure the corresponding I/O port.
9:8, 5:4, 1:0
Refer to
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Section 2.1 on page 46
27 26 25
CNF6[1:0] MODE6[1:0]
rw rw rw
11 10 9
CNF2[1:0] MODE2[1:0]
rw rw rw
Table 20: Port bit configuration table on page
Table 20: Port bit configuration table on page
Doc ID 13902 Rev 12
for a list of abbreviations used in register descriptions.
24 23 22
CNF5[1:0]
rw rw rw
8 7 6
CNF1[1:0]
rw rw rw
>
00):
21 20 19 18
MODE5[1:0] CNF4[1:0]
rw rw rw rw
5 4 3 2
MODE1[1:0] CNF0[1:0]
rw rw rw rw
156.
156.
17 16
MODE4[1:0]
rw rw
1 0
MODE0[1:0]
rw rw
165/1096