Partition Hot Reset; Partition Upstream Secondary Bus Reset - IDT 89HPES64H16G2 User Manual

IDT Reset and Initialization
Notes
PES64H16G2 User Manual

Partition Hot Reset

A partition hot reset is initiated by any of the following events:
– Reception of TS1 ordered-sets on the partition's upstream port indicating a hot reset.
– Data link layer of the partition's upstream port transitions to the DL_Down state.
– As directed by the Switch Partition State (STATE) field in the Switch Partition (SWPARTxCTL)
register.
When a partition hot reset is initiated the following sequence of actions take place.
1. The upstream port associated with the partition transitions its PHY LTSSM
state (i.e., the hot reset state on reception of TS1 ordered-sets indicating hot reset or else the Detect
state).
2. Each downstream switch port associated with the partition whose link is 'up' propagates a hot reset
by transmitting TS1 ordered sets with the hot reset bit set. All logic associated with the switch parti-
tion (i.e., switch ports, switch core, etc.) is logically reset to its initial state.
If the link associated with a downstream port is in the Disabled LTSSM state, then a hot reset
will not be propagated out on that port. The port will instead transition to the Detect LTSSM
state. Although not a hot reset, this has the same functional effect on downstream components.
3. All register fields and registers associated with the switch partition except those designated Sticky
and SWSticky, are reset to their initial value. The value of Sticky and SWSticky registers and fields
is preserved across a hot reset.
4. As long as the condition that initiated the partition hot reset persists, logic associated with the parti-
tion remains at this step.
5. Ports associated with the partition begin to link train and normal partition operation begins.
The initiation of a hot reset due to the data link layer of the upstream port transitioning to the DL_Down
state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the corresponding
Switch Partition Control (SWPARTxCTL) register. When the DLDHRST is set and the upstream port's data
link is down, the PHY LTSSM transitions to the appropriate states but the hot reset steps described above
are not executed. As a result, the behavior of the partition is the following:
– Peer-to-peer TLP transfers between downstream ports are allowed to progress.
– TLPs not destined to a downstream port are treated as unsupported requests.
– TLPs generated by the switch and that are normally routed to the root (e.g., INTx messages) are
silently discarded.
– Downstream ports are allowed to enter and exit L0s and L1 ASPM state without regard to the
ASPM state of the upstream port (i.e., since there is no upstream port, then upstream port plays
no role in determining when a downstream port enters or exists a low power ASPM state).
Note that other hot reset trigger conditions (i.e., hot reset triggered by reception of training sets with the
hot reset bit set on the upstream port) are unaffected by the DLDHRST bit.

Partition Upstream Secondary Bus Reset

A partition upstream secondary bus reset is initiated by any of the following events.
– A one is written to the Secondary Bus Reset (SRESET) bit in the partition's upstream port Bridge
Control (BCTL) register
When an Upstream Secondary Bus Reset occurs, the following sequence of actions take place on logic
associated with the affected partition.
1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.
1.
The term 'LTSSM' refers to a port's Link Training and Status State Machine in the Physical Layer.
2.
Note that the Bridge Control Register is only present in Type 1 Configuration Headers (i.e., PCI-to-PCI Bridge
functions).
2
.
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1
state to the appropriate
April 5, 2013