IDT Tsi578 User Manual

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IDT

Tsi578





Serial RapidIO Switch

User Manual

June 6, 2016

Table of Contents

Summary of Contents for IDT Tsi578

Page 1: User Manual
Titl Tsi578   Serial RapidIO Switch User Manual June 6, 2016...
Page 2 IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree.
Page 3: Table Of Contents
Reset Control Symbol Processing ............. 57 Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 4 Transfer Modes ..............87 Tsi578 User Manual...
Page 5 5.2.3 Configuring Multicast Masks Using the IDT Specific Registers......116 Arbitration for Multicast Engine Ingress Port ........... 117 Error Management of Multicast Packets .
Page 6 Block Diagram................144 Tsi578 as I C Master .
Page 7 Tsi578 RapidIO Buffer Watermark Selection Settings ........
Page 8 RapidIO Switch Port Link Timeout Control CSR ........271 Tsi578 User Manual...
Page 9 IDT-Specific Performance Registers ........
Page 10 12.14.4 SerDes Lane 3 Pattern Generator Control Register ........406 Tsi578 User Manual...
Page 11 C Boot and Diagnostic Timer ............480 Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 12 IDT Specific Timers ........
Page 13 IDT-specific Multicast Mask Configuration ........
Page 14 Tsi578 Clocking Architecture ........
Page 15 Lookup Table States............... . . 51 Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi578 Responses....53 Table 4: Tsi578 Port Numbering .
Page 16 IDT-Specific Per-Port Performance Registers........
Page 17: About This Document
“Revision History” on page 18 Scope The Tsi578 User Manual discusses the features, capabilities, and configuration requirements for the Tsi578. It is intended for hardware and software engineers who are designing system interconnect applications with the device. Document Conventions This document uses the following conventions.
Page 18: Revision History
“SRIO MAC x SerDes Configuration Channel 2”, and “SRIO MAC x SerDes Configuration Channel 3” • Removed Ordering Information from the manual. This information now resides solely in the Tsi578 Hardware Manual. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 19 “SRIO MAC x Digital Loopback and Clock Selection Register”.DLT_THRESH July 2009, Formal This is the production version of the manual. The document has been updated with IDT formatting. There have been no technical changes. Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 20 About this Document Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 21: Functional Overview
Overview The IDT Tsi578 is a third-generation RapidIO switch supporting 80 Gbits/s aggregate bandwidth. The Tsi578 is part of a family of switches that enable customers to develop systems with robust features and high performance at low cost. The Tsi578 provides designers and architects with maximum scalability to design the device into a wide range of applications.
Page 22: Figure 1: Block Diagram
In addition, the Tsi578 supports both in-band serial RapidIO access and out-of-band access to the full fabric register set through the I2C interface.
Page 23: Figure 2: Processor Farm Mezzanine Diagram
Serial RapidIO 80B803A_TA001_01 The Tsi578 provides traffic aggregation through packet prioritization when it is used with RapidIO-enabled I/O devices. When it is in a system with multiple RapidIO-enabled processors it provides high performance peer-to-peer communication through its non-blocking switch fabric.
Page 24: Features
1. Functional Overview > Overview 1.1.1 Features The Tsi578 contains the following features: Electrical Layer Serial RapidIO Features • Up to 8 ports in 4x Serial mode • Up to 16 ports in 1x Serial mode (each 4x port can be configured independently as two 1x ports) •...
Page 25 Optionally loads default configuration from ROMs during boot-up, through I • Supports one outstanding maintenance transaction per interface • Supports 32-bit wide (4 byte) register access 1. All bandwidths assume the internal switching fabric is clocked at 156.25 MHz. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 26: Serial Rapidio Interface
All RapidIO interfaces are compliant with the RapidIO Interconnect Specification (Revision 1.3). This section describes the transport layer features common to all Tsi578 RapidIO interfaces. The RapidIO interface has the following capabilities: •...
Page 27: Maintenance Requests
70 Gbits/s for seven egress ports operating at maximum width of 4x and a lane speed of of 3.125 Gbit/s, based on the the number of ports on the Tsi578.
Page 28: Features
RapidIO Interconnect Specification (Revision 1.3) - Part 11 Multicast Specification. Serial RapidIO Electrical Interface The Tsi578 has eight Media Access Controllers (MAC) comprising the 16 Serial RapidIO ports. The 16 ports are grouped into pairs consisting of one even numbered port and one odd numbered port. Each port has flexible testing features including multiple loopback modes and bit error rate testing.
Page 29: Figure 4: Tsi578 Mac Block Diagram
1. Functional Overview > Serial RapidIO Electrical Interface Figure 4: Tsi578 MAC Block Diagram Serial Rapid IO Registers and Buffers Numbered Even-numbered Ports (4x mode or 1x mode) Ports (1x mode only) 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B...
Page 30: Internal Switching Fabric (Isf)
1. Functional Overview > Internal Switching Fabric (ISF) Internal Switching Fabric (ISF) The Internal Switching Fabric (ISF) is the crossbar switching matrix at the core of the Tsi578. It transfers packets from ingress ports to egress ports and prioritizes traffic based on the RapidIO priority associated with a packet and port congestion.
Page 31 – Slave address can be loaded from three sources: power-up signals, boot load from EEPROM, or by software configuration – Provides read and write accesses that are 32 bits in size to all Tsi578 registers – Ignores General-Call accesses –...
Page 32: Jtag Interface
Fast Mode or High-Speed Mode (HS-MODE) • Reserved 7-bit addresses should not be used as the Tsi578’s 7-bit address. If a reserved address is programmed, the Tsi578 will respond to that address as though it were any other 7-bit address with no consideration of any other meaning.
Page 33 1. Functional Overview > JTAG Interface — Bypass — Hi-Z — IDCODE — Clamp — User data select Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 34 1. Functional Overview > JTAG Interface Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 35: Serial Rapidio Interface
Serial RapidIO Interface This chapter describes the serial RapidIO interface of the Tsi578. It includes the following information: • “Overview” on page 35 • “Transaction Flow” on page 37 • “Lookup Tables” on page 37 • “Maintenance Packets” on page 53 •...
Page 36: Transaction Flow Overview
2.1.4 Control Symbols Control symbols received by the Tsi578 have their CRC validated, and their field values checked. If either the CRC is incorrect or the control symbol field values are incorrect, a packet-not-accepted control symbol is sent back and the control symbol is discarded. Otherwise, the control symbol is used by the port for purposes of packet management in the transmit port or link maintenance.
Page 37: Transaction Flow
The Tsi578 receives a RapidIO packet on one of its RapidIO ports. After performing integrity checks, such as validating a CRC, the interface logic locates the destination ID in the packet. The Tsi578 uses this information to determine to which egress port the packet must be sent and whether it is a multicast packet.
Page 38: Filling The Lookup Tables
64-KB destination IDs, with some limitations. To ensure high system reliability, the lookup tables are parity protected. System software must intervene when a parity error is detected. The Tsi578 guarantees that packets are not incorrectly delivered when the lookup table incurs single bit errors.
Page 39: Figure 5: Lut Mode Of Operation
DestID[7:0] using DestID[15:8] using DestID[8:0] LUT entry mapped egress port < Port_Total Default egress port mapped? Route to egress port defined in LUT Route to default egress port Discard packet Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 40: Lut Modes
“RapidIO Route LUT Attributes (Default Port) CSR”). Flat mode is the default mode of operation of the LUT. Figure 6 shows the configuration of the Local and Global Lookup tables (LUT) in Flat mode. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 41: Figure 6: Flat Mode Routing
“RapidIO Route LUT Attributes (Default Port) CSR” on page 262. If the default port is unmapped, the packet is discarded and the Tsi578 raises the IMP_SPEC_ERR bit in the “RapidIO Port x Error Detect CSR” on page 294.
Page 42: Figure 7: Flat Mode Routing Example
Egress Port is loaded Default Port into Global LUT through the PORT field in the RIO_ROUTE_CFG_PORT register DestID MSB is loaded into Global LUT through the CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 43: Figure 8: Flat Mode Lut Configuration Example
2.3.3.1 Flat LUT Programming Each of the ports on the Tsi578 has its own lookup table. Each lookup table can be programmed with different values which allows each port to route packets differently. The lookup table maps the packet to the correct output port based on the destination ID. The capability of each port having their own LUT is functionality that is not required in the RapidIO Interconnect Specification (Revision 1.3).
Page 44 Lookup Table Configuration Examples The Tsi578 lookup tables can be configured through an external EEPROM or through software maintenance writes to the Tsi578 registers. IDT strongly recommends that the entire lookup table be configured on each port to avoid undefined lookup table entries which can cause non-deterministic behavior.
Page 45: Hierarchical Mode
ID to index the “global LUT” and retrieve an egress port number. Thus, the majority of the 16-bit destination ID number space is covered by the global LUT, with groups of 256 destination IDs targeting the same egress switch port. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 46: Figure 9: Hierarchical Mode
252), the incoming packet is routed to the Default Port defined by “RapidIO Route LUT Attributes (Default Port) CSR”. If the default port is unmapped, the packet is discarded and the Tsi578 raises the IMP_SPEC_ERR bit in the “RapidIO Port x Error Detect CSR” on page 294.
Page 47: Figure 10: Hierarchical Mode Routing Example
DestID MSB is loaded into Global LUT through the BASE field in the SPx_ROUTE_BASE of DestID register DestID LSB is loaded into Local LUT through the CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register Default Port Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 48 The following example shows how to program the LUT in Port 8, but because all ports in the Tsi578 are capable of operating in hierarchical mode, this procedure can be easily modified to accommodate a different ingress port.
Page 49: Mixed Mode Of Operation
323 is unpredictable when there is a parity error in the LUT. All LUT entries must be initialized before use to ensure that the parity bits are set appropriately. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 50: Lookup Table Error Summary
It's the same as a powered-on port except that the Link Partner was behaving as disconnected to the port. The port is healthy and when the link partner is resurrected, the link between the port and partner is be re-established. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 51: Lookup Table Entry States
A lookup table entry can be in one of the following states: mapped, unmapped, parity error, or unprogrammed. A lookup table entry that routes packets to a port that exists within the Tsi578 is mapped. A lookup table entry that routes packets to a port that does not exist with the Tsi578 unmapped.
Page 52 IDT-specific interface. A LUT parity error can also be left over from initializing the LUTs. The Tsi578’s design always checks the routing table entry for routing maintenance packets it receives, even though when the hop count is zero the receiving port is automatically used to return the response.
Page 53: Maintenance Packets
If there is a match, system behavior is undefined. If a maintenance packet has a hop count greater than zero, the Tsi578 decrements the hop count, recalculates the CRC, and routes the packet out the port selected by the LUT. For this reason, all maintenance packets must contain routeable source and destination addresses and the routing LUT must be programmed to route both the maintenance transaction and its response.
Page 54 2. Serial RapidIO Interface > Maintenance Packets Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi578 Responses Transaction Type Size Field Action taken by Tsi578 Error Logging Notes Write Request Do not care Send Maintenance...
Page 55: Multicast Event Control Symbols
312. Additionally, the MCES pin in the Tsi578 can output an edge when an MCS is received. The MCES pin toggles to signal an MCS is received; that is, the first MCS causes the pin to go low and the second MCS causes it to go back high.
Page 56: Generating An Mcs
2. Serial RapidIO Interface > Multicast Event Control Symbols 2.5.2 Generating an MCS The Tsi578 supports the generation of an MCS in two ways. The first method is called the software usage model which use of a maintenance write transaction in a port (see “RapidIO Port x Send Multicast-Event Control Symbol Register”...
Page 57: Reset Control Symbol Processing
The exception to the rule for CRC codes is the handling of maintenance packets. Maintenance packets have a hop count field, covered by CRC, which must be changed by the Tsi578 if the packet is to be forwarded. So, CRC is recomputed for maintenance packets for each link they traverse.
Page 58: Software Assisted Error Recovery
, which can be local or remote to the Tsi578 switch, has access to the device through another port. The system host can be any processor in a system that is tasked with error management responsibility. In a large system, multiple processors may have this responsibility.
Page 59: Hot Insertion And Hot Extraction
Hot insertion and hot extraction functionality enables reliable systems to safely add, remove, and replace components while the system continues to operate. The system host can use the Tsi578’s capability to restrict the access of a newly inserted component to prevent a faulty component from negatively affecting the system.
Page 60: Hot Insertion
“RapidIO Serial Port x Local ackID Status CSR”). Tsi578 ports on which a component insertion event can occur can be configured to notify the system host when this event occurs. The PORT_LOCKOUT bit must be set to allow the LINK_INIT_NOTIFICATION bit in the “RapidIO Port x Interrupt Status Register”...
Page 61: Hot Extraction
At this point, the component can be safely extracted. The LUT entries for all ports in the Tsi578 can be configured to not route any packets to the port on which the hot extraction occurs.
Page 62: Hot Extraction System Notification
“Hot Insertion and Hot Extraction” on page When the Tsi578 detects a LOLS, it attempts to regain synchronization and recover so that no packets are lost, duplicated, or unnecessarily retransmitted. This is in compliance with the RapidIO Interconnect Specification (Revision 1.3). To guarantee that no packets are lost, ensure that the duration of the packet time-to-live timer is programmed to be greater than the duration of the port’s silence...
Page 63: Figure 11: Lols Silent Period
2. Serial RapidIO Interface > Loss of Lane Synchronization Figure 11 shows the Tsi578 entering the silence period when it experiences the loss of signal from its link partner. Figure 11: LOLS Silent Period Once synchronization is re-acquired, the Tsi578 transmitter resumes all timers and resumes sending packets from the next un-sent packet in its transmit queue, using the next available ackID.
Page 64: Dead Link Timer
As a result, this may eventually block every traffic path in the system. To enable systems to robustly deal with dead links, the Tsi578 has a “dead link timer” feature. This is a proprietary function that is outside of the RapidIO specification. The DLT_EN and DLT_THRESH fields in the “SRIO MAC x Digital Loopback and Clock Selection Register”...
Page 65: Serial Rapidio Electrical Interface
“Bit Error Rate Testing (BERT)” on page 80 Overview The Tsi578 has eight Media Access Controllers (MAC) comprising the 16 Serial RapidIO ports. The 16 ports are grouped into pairs consisting of one even numbered port and one odd numbered port. Each port has flexible testing features including multiple loopback modes and bit error rate testing.
Page 66: Figure 12: Tsi578 Mac Block Diagram
3. Serial RapidIO Electrical Interface > Overview Figure 12: Tsi578 MAC Block Diagram Serial Rapid IO Registers and Buffers Numbered Even-numbered Ports (4x mode or 1x mode) Ports (1x mode only) 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B PRBS...
Page 67: Port Numbering
3. Serial RapidIO Electrical Interface > Port Numbering Port Numbering The RapidIO ports on the Tsi578 are numbered sequentially from 0 to 15. The following table shows the mapping between port numbers and the physical ports. These port numbers are used within the destination lookup tables for ingress RapidIO ports and in numerous register configuration fields.
Page 68: Port Aggregation: 1X And 4X Modes
Rx(Lane B) Port Aggregation: 1x and 4x Modes The RapidIO ports on the Tsi578 are grouped into pairs that share the same MAC. The MAC provides the PMA/PCS encoding/decoding layers, as well as the RapidIO physical, transport and logical layer functionality required of a RapidIO switch device.
Page 69: 1X + 1X Configuration
4x Configuration When the even-numbered port in a Tsi578 MAC is configured to operate in 4x mode (for example port 0), the odd-numbered port in a MAC (for example port 1) cannot be used and the register values for the odd-numbered port should be ignored.
Page 70: Clocking
Serial RapidIO ports use source clocked transmission; the clock is embedded in the data stream using 8B/10B encoding. The Tsi578 recovers the embedded clock in the received data stream and generates a separate clock (based on S_CLK) to transmit its own data.
Page 71: Changing The Clock Speed
When ports in the same MAC are both operating in 1x mode, both ports operate at the same rate. The data rate of all the ports in Tsi578 at power-up is determined by the setting of the SP_IO_SPEED[1:0] pins (see “Signal...
Page 72: Port Power Down
SMAC0_DLOOP_CLK_SEL register to the correct value and power the port back up again. Port Power Down All of the Tsi578 RapidIO ports can be powered down to minimize power consumption when the port is not required. However, port 0 has special power-down requirements that must be followed (see “Special Conditions for Port 0 Power Down”...
Page 73: Special Conditions For Port 0 Power Down
• To save power, assert the SPn+1_PWRDN pin and/or set the PWDN_X1 bit to 1 in the “SRIO MAC x Digital Loopback and Clock Selection Register” on page 377. If this bit is not set, Port n+1 consumes unnecessary power. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 74: Port Lanes
3.5.4.1 Signals Sampled After Reset After a hardware reset is de-asserted, the Tsi578 samples the state of the SP{n}_PWRDN pins and only powers up the ports that are enabled. Each RapidIO port has a unique pin, SPn_PWRDN. Port 0 is the default port and can only be powered down through a direct register write.
Page 75: Lane Synchronization And Alignment
Lane swap is only supported when the MAC is operating in 4x mode. Lane swapping for 1x mode is not supported. If the Tsi578 port to a connector is lane swapped as 4x mode and a 1x mode device in inserted into the connector, the 4x mode port will fail-down (that is, become a 1x mode connection) and lane A is initialized.
Page 76 When lanes are swapped, the following mapping between channels and lanes is used: • Channel 0 maps to Lane D • Channel 1 maps to Lane C • Channel 2 maps to Lane B • Channel 3 maps to Lane A Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 77: Programmable Transmit And Receive Equalization
Tx lanes are swapped and Rx lanes are not, or vice versa. Programmable Transmit and Receive Equalization The Tsi578 has programmable drive strengths and de-emphasis of a transmit lane. The Tsi578 also has the ability to internally boost the received signal. This functionality is described in the following sections.
Page 78: Receive Equalization
For example, setting RX_EQ_VAL[2:0] = 3’b100 results in a 2.5dB boost of the received signal. This boost is internal to the device and is useful in improving the signal at the slicer when the signal arriving at the pins are degraded. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 79: Port Loopback Testing
3. Serial RapidIO Electrical Interface > Port Loopback Testing Port Loopback Testing The Tsi578’s serial RapidIO ports support the following kinds of loopback: • Digital equipment loopback • Logical line loopback Figure 15 shows where each loopback is implemented in the Tsi578.
Page 80: Digital Equipment Loopback
Bit Error Rate Testing (BERT) The RapidIO ports on the Tsi578 have a built-in bit error rate test (BERT). This test is based either on fixed symbols or on a pseudo-random bit sequence (PRBS). Each lane within a port has a pair of Pattern Generators and Pattern Matchers.
Page 81 Tsi578 and a device that supports the same polynomial equation. When testing a link on the Tsi578 with the BERT feature, the link partner device must support PRBS testing with at least one of the two polynomials shown in Table 8, or it must support fixed-pattern tests.
Page 82: Bert Pattern Matcher And Error Counter
The Pattern Generator and Matcher are independently controllable within the same lane. They do not need to be enabled, or programmed, the same way. For example, the Tsi578 can transmit a different PRBS pattern than the pattern it is receiving.
Page 83: Using Prbs Scripts For The Transmitters And Receivers
3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) — 3.9.3.1 Fixed Pattern-based BERT Transmitter Configuration To configure a Tsi578 transmitter for fixed-pattern BERT operation: • Write the bit stream to be transmitted into the PAT0 field in the “SerDes Lane 0 Pattern Generator Control Register” on page 403.
Page 84 3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT) Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 85: Internal Switching Fabric
“Arbitration for Egress Port” on page 88 Overview The Internal Switching Fabric (ISF) is the crossbar switching matrix at the core of the Tsi578. It transfers packets from ingress ports to egress ports and prioritizes traffic based on the RapidIO priority associated with a packet and port congestion.
Page 86: Functional Behavior
The ISF is responsible for transporting packets from an ingress port to an egress port and to and from the multicast engine. When RapidIO packets arrive at the ingress ports, the Tsi578 performs several tests to ensure the packet is valid. If a packet passes these tests, the ingress port consults its destination ID lookup table (LUT) to determine the egress port for the packet.
Page 87: Transfer Modes
When a port is configured for cut-through mode, the port is permitted to start sending the packet before the packet has fully arrived at the Tsi578. This is possible because the RapidIO destination ID (routing information) appears near the front of a RapidIO packet.
Page 88: Arbitration For Egress Port
3 packets are being presented for arbitration by any port, those packets are accepted ahead of any priority 2 packets. Similar behavior holds for priority 2 packets being chosen over priority 1; and priority 1 over priority 0 packets. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 89: Weighted Round Robin (Wrr) Arbitration
1x mode with 16 ports (~5.89%) which is the same as a unicast port. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 90: Table 10: Sample Register Settings For Wrr In A Given Priority Group (Wrr_En=1)
The percent values in the table assumes all opportunity for transmission is filled by either the selected or un-selected types. When there is 100% utilization of either unicast or multicast, lack of transfer of the other type of packet can be encountered in the system. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 91: Packet Queuing
4. Internal Switching Fabric > Packet Queuing Packet Queuing The Tsi578 has a queuing system on both the ingress and egress ports. Figure 19: Ingress and Egress Packet Queues in Tsi578 Ingress Egress Packet Queue Packet Queue 4.4.1 Output Queuing on the Egress Port Each egress port has a queue that holds up to eight packets.
Page 92 “RapidIO Port x ISF Watermarks” on page 397. Rules for Programming Watermarks The following rules are applied to Tsi578 watermarks: • No watermark is associated with Priority 3 packets • A priority x packet is accepted in the buffer if the number of free buffers is greater than the programmed watermark of the associated priority.
Page 93: Table 11: Examples Of Use Of Watermarks
The packet offered for selection by the output port is subject to the input queuing arbitration. For information on how the ingress port selects which packet to offer for transmission, see “Input Arbitration” on page Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 94: Input Queue For The Isf Port
The default watermark values are 1 for priority 2, 2 for priority 1, and 3 for priority 0. This maximizes the number of buffers that can accept lower priority packets, which maximizes the throughput of these packets. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 95: Input Arbitration
4 bytes of the packet. This allows the link partner to select another packet for transmission that has a higher probability of being accepted by the link partner. The Tsi578 provides performance registers that system software can use to determine the extent of input congestion on the switch (refer to “IDT-Specific Performance Registers”...
Page 96 • Else if there are no such packets, Select the priority 0 packet closest to the head of the queue.Note that this packet cannot make progress. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 97 The Tsi578 never violates the RapidIO protocol when it selects the switching order for packets.
Page 98 “Fabric Control Register” on page 380. Enabling this feature is recommended. Note that reorder limiting applies to all ports and all packets in the Tsi578. The number of times a packet is permitted to be delayed by a lower or same priority packet is configurable through the RDR_LIMIT register field in the “Fabric Control Register”...
Page 99: Input Queuing Model For The Multicast Work Queue
If there is sufficient space for at least one maximum sized (276 byte) packet to be received, all ingress ports are signalled that packets of any priority can be accepted by the multicast work queue. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 100: Input Queuing Model For The Broadcast Buffer
Broadcast buffers always operate in store-and-forward mode. This ensures that packet transmission to the egress port is never delayed by packet replication. IDT recommends that multicast packets within a system all have the same priority. 4.4.7 ISF Bandwidth The ISF delivers full 10 Gbits/s of bandwidth in both transmit and receive directions.
Page 101 Refer to the TRANS_MODE bit in “RapidIO Port x Control Independent Register” on page 319 for more information on how to control cut-through mode. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 102 4. Internal Switching Fabric > Packet Queuing Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 103: Multicast
70 Gbits/s for seven egress ports operating at maximum width of 4x and a lane speed of of 3.125 Gbit/s, based on the the number of ports on the Tsi578.
Page 104: Multicast Operation With Multiple Tsi57X Switches
5. Multicast > Overview The Tsi578 includes the following features: • One multicast engine provides dedicated multicast resources without impacting throughput on the ports • Eight multicast groups • Sustained multicast output bandwidth, up to 10 Gbit/s per egress port •...
Page 105: Multicast Terminology
Packets which are sent to the multicast engine from ingress ports, and packets which are received from the multicast engine by egress ports. Unicast Traffic All packets which are not sent to or received from the multicast engine. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 106: Multicast Behavior Overview
Multicast packets received by an ingress port are routed to the Multicast Engine port based on the destination ID and transaction type (TT) field of the packet. A packet arriving at the Tsi578 is directed to the Multicast Engine (MCE) by the multicast group table on the packet’s ingress port. The multicast work queue selects a multicast group for the packet, again based on the packet’s destination ID and TT...
Page 107: Multicast Work Queue
1. Packets are stored in an 8-byte boundary. Packets with length of non-multiple of 8-bytes is rounded up to the nearest multiple of 8 for storage in the buffer. The packets are not altered and are transmitted exactly as they are received. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 108: Figure 22: Multicast Packet Flow In The Tsi578
In RapidIO technology, a datum means a word of data sent in a single clock cycle. When the Tsi578 is in 4x mode, a datum is 32 bits and in 1x mode, a datum is 8 bits. If a packet is STOMPed when it is received at the broadcast buffer, it is not dropped. The STOMPed packet is transmitted to the egress port.
Page 109 10 Gbps. Although represented by the same multicast vector, each individual broadcast buffer operates independently. 1. When the ISF clock speed is set to 156.25 MHz. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 110: Multicast Group Tables
A non-existent port number is a port number greater than that which exists on the device. For the Tsi578, port numbers greater than 15 are ignored. It is possible to add and remove powered down or otherwise disabled ports to/from the multicast masks.
Page 111 In this case, the multicast engine silently discards the packet. The following figure is a representation of the relationship between the destination ID, multicast group number, multicast vector, and egress port. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 112: Configuring Basic Associations
The individual association operations can be performed in any order. 1. Set up the operation to associate destination ID 0x1234 with multicast mask 0 • Write the value 0x1234_0000 to the “RapidIO Multicast DestID Configuration Register” on page 265 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 113: Configuring Multicast Masks
• Write the value 0x0000_0610 to the Multicast Mask Configuration Register 2. Add port 7 to multicast mask 0 • Write the value 0x0000_0710 to the Multicast Mask Configuration Register Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 114: Figure 24: Completed Tables At The End Of Configuration
Configured using the and egress port number performed using the RIO Multicast DestID RIO Multicast Mask Configuration Register Configuration Register "Large" field activated using the RIO Multicast DestID Association Register Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 115 6. Verify that port 5 is included in mask 2 • Write the value 0x0002_0500 to the Multicast Mask Configuration Register • Read the value 0x0002_0501 from the Multicast Mask Configuration Register Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 116: Configuring Multicast Masks Using The Idt Specific Registers
5.2.3 Configuring Multicast Masks Using the IDT Specific Registers The Tsi578 also has a device specific implementation to configuring the multicast masks. This implementation allows the direct writing of configuration information into the multicast group and vector tables a through the “RapidIO Multicast Write Mask x Register”...
Page 117: Arbitration For Multicast Engine Ingress Port
5. Multicast > Arbitration for Multicast Engine Ingress Port Figure 25: IDT-specific Multicast Mask Configuration Switch Port Number Multicast DEST_ID 0 = No Mask Port Participating in Vector 1 = Yes Large Small Number 0x10300 0x10320 0x10304 0x10324 0x10308 0x10328...
Page 118: Error Management Of Multicast Packets
When a packet arrives at the Tsi578 and a stomp control symbol is received part way though the packet, the packet is still multicast to the egress ports. However, the egress ports stomp the packet when they transmit the packet.
Page 119: Multicast Maximum Latency Timer
“RapidIO Broadcast Buffer Maximum Latency Expired Override” on page 386 can be used to verify the operation of software associated with “RapidIO Broadcast Buffer Maximum Latency Expired Error Register” on page 384. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 120: Silent Discard Of Packets
When one of the active ports is reset, the multicast mask is required to be re-bound to that port. Refer to “Port Power Down” on page 72 for more information Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 121: Event Notification
Event Notification This chapter describes the system of error and event notification in the Tsi578. It includes the following information: • “Overview” on page 121 • “Event Summary” on page 122 • “Error Rate Thresholds” on page 126 • “Error Stopped State Recovery” on page 128 •...
Page 122: Event Summary
6. Event Notification > Event Summary Event Summary Table 13 describes all the events that can be raised within the Tsi578 and whether these events generate a interrupt, a port-write, or both. Table 13: Tsi578 Events Interface Where Event Name...
Page 123 6. Event Notification > Event Summary Table 13: Tsi578 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write Error Rate Error This event occurs when the error rate counter in the RapidIO Degraded “RapidIO Port x Error Rate CSR”...
Page 124 6. Event Notification > Event Summary Table 13: Tsi578 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write TEA in Fabric Error This event is raised when a fabric transmission request times out and a packet is dropped.
Page 125 6. Event Notification > Event Summary Table 13: Tsi578 Events (Continued) Interface Where Event Name Event Generate Generate (Status Bit) Type Description Occurs Interrupt Port-write Illegal AckID Error This event is raised when a RapidIO port receives a packet RapidIO in Packet with an ackID that is not in sequence.
Page 126: Error Rate Thresholds
Error Rate Failed/ Degraded Threshold counter Error Rate Thresholds There are two event thresholds in the Tsi578: the Error Rate Failed Threshold Reached and the Error Rate Degraded Threshold Reached. These events notify the system that errors are occurring on a RapidIO interface at a rate that requires special attention.
Page 127: Maintaining Packet Flow
Error Rate Failed Threshold is reached the packet is discarded and the OUTPUT_DROP, OUTPUT_FAIL bits are asserted in the port “RapidIO Port x Error and Status CSR” on page 278 where the link failure occurred. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 128: Error Stopped State Recovery
When a link enters a error stopped state, there are multiple ways to clear the error conditions. However, the method described in this section uses IDT specific functionality and control symbols to clear the errors by forcing a hardware recovery situation through software.
Page 129: Link Error Clearing And Recovery
The standard RapidIO mechanism for recovering from errors uses Link Request/Input Status and Link Response control symbols. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 130: Figure 27: Control Symbol Format
The following steps show IDT specific functionality and control symbols that are used for clearing stop states: 1. The near-end link partner sends a Packet-not-accepted + General Error + Link Request + Input...
Page 131: Event Capture
The multicast engine does not distinguish between port-write packets and other types of packets. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 132: Table 14: Error Rate Error Events
Description Registers Implementation Specific The Tsi578 Switch uses the implementation specific error to combine with other error events, so that they can be included within the Error Rate reporting function. These events are: • Reserved Transport Type detected (tt field = 10 or 11 for all but maintenance packets with hop count =0) •...
Page 133: Port-Write Notifications
In the Tsi578, all RapidIO ports can generate port-write messages based on interrupt events. The system is notified of most events that occur in the Tsi578 RapidIO interfaces through the RapidIO port-write message. The port-write function is enabled by default, but can be disabled through the PW_DIS field in the “RapidIO Port x Mode CSR”...
Page 134: Destination Id
Port-writes are sent at the priority defined in the PW_PRIORITY field in the “RapidIO Port x Discovery Timer”. The default value is priority 3. Port-write packets are transmitted with a sourceID of 0x00. Port-writes are issued with a hop count of 0xFF. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 135: Servicing Port-Writes
Servicing Port-writes The Tsi578 supports a programming model for servicing port-writes. The first algorithm described minimizes the number of port writes generated by the Tsi578, and therefore the number of specific interrupt events that must be handled by a system host.
Page 136: Port-Writes And Hot Insertion/Hot Extraction Notification
Interrupt Notifications In the Tsi578 interrupts are hierarchical, which allows software to determine the cause of the interrupt with minimum register access. System designers must decide upon a maximum rate of interrupt notifications, and set the error thresholds appropriately.
Page 137: Figure 28: Rapidio Block Interrupt And Port Write Hierarchy
TEA_EN, bit[31] SP_CTL_INDEP MCT_TEA, bit[13] SP_INT_STATUS MCT_TEA_EN, bit[13] SP_CTL_INDEP LINK_INIT_NOTIFICATION, bit[14], SP_INT_STATUS LINK_INIT_NOTIFICATION_EN, bit[14], SP_CTL_INDEP PORT_ERR, bit[29] SP_ERR_STATUS PORT_ERR_EN, bit[12] SP_CTL_INDEP Logical/Transport Errors RIO_LOG_ERR_DET register RIO_LOG_ERR_DET_EN register RIO_LOG_ERR_DET register is not locked Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 138: Int_B Signal
Because there is only one logical layer error per device, the LOG_ERR bit is also in the“Global Interrupt Status Register” on page 388. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 139: Table 16: Port X Error And Status Register Status
“RapidIO Port x Interrupt Status Register” on page 326. The Tsi578 also provides the implementation specific option of sending an interrupt for some of the bits found in the“RapidIO Port x Error Detect CSR” on page 294.
Page 140: Interrupt Notification And Port-Writes
6.7.3 Interrupt Notification and Port-writes In the Tsi578, all RapidIO ports can also generate port-write messages based on interrupt events. Because of this architecture, the RapidIO interrupt enables also control whether a port-write message is issued for each interrupt. In each port the register bit IRQ_EN in “RapidIO Port x Control Independent...
Page 141: I 2 C Interface
Initializing device registers from an EEPROM after reset • Reading and writing external devices on the I C bus • Reading and writing Tsi578’s internal registers for management purposes by an external I master The I C Interface has the following features: •...
Page 142 – Slave address can be loaded from three sources: power-up signals, boot load from EEPROM, or by software configuration – Provides read and write accesses that are 32 bits in size to all Tsi578 registers – Ignores General-Call accesses –...
Page 143: Protocol Overview
Fast Mode or High-Speed Mode (HS-MODE) • Reserved 7-bit addresses should not be used as the Tsi578’s 7-bit address. If a reserved address is programmed, the Tsi578 will respond to that address as though it were any other 7-bit address with no consideration of any other meaning.
Page 144: Block Diagram
As a master, it enables access to other device registers (for example, during the I C load at power-up). In addition, various signals relate to the boot load sequencer, an interrupt signal connects to the Tsi578 Interrupt Controller, and device-level status connects to the EXI2C_STAT register in the externally visible registers.
Page 145: Figure 29: I 2 C Block Diagram
Internal Register Bus Arbiter The reference diagram in Figure 30 shows the I C bus and data protocol. Three basic signal relationships are defined by the bus timing: Start/Restart, Bit, and Stop. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 146: Figure 30: I 2 C Reference Diagram
I device will require a peripheral addressing phase. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 147: Tsi578 As I 2 C Master
For more information on how this issue may affect your application, and possible work around options, see “Masterless bus busy” in the Tsi578 Design Notes. Software can instruct the Tsi578 to read or write to an external slave device using the following registers: •...
Page 148: Figure 31: Software-Initiated Master Transactions
7. I C Interface > Tsi578 as I C Master Figure 31: Software-initiated Master Transactions Write Transaction (WRITE=1) From DEV_ADDR From PADDR From I2C_MST_WDATA Slave Address Peripheral Address Data Written to Device 7 Bit SlvAdr+Wr(0) PerAdrMsb PerAdrLsb WriteData WriteData WriteData...
Page 149: Example Eeprom Read And Write
For master operations, the clock frequency can be changed by modifying the timing parameter registers (see “Bus Timing”). Operation above 100 kHz is possible but the Tsi578 does not implement all the standards requirements for fast mode. Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 150: Master Bus Arbitration
C Specification. During the Start and Slave Address phase, any unexpected state on the bus causes the Tsi578 to back off, release the bus, and wait for a Stop before retrying the transaction. If the arbitration timer configured in the “I2C_SCLK Low and Arbitration Timeout Register”...
Page 151: Master Data Transactions
Slave Configuration Register”, or matches the fixed SMBus Alert Response address. The external master can then read or write to the Tsi578 through a small block of 256 addresses called the Tsi578 peripheral address space, and do the following: •...
Page 152 7. I C Interface > Tsi578 as I C Slave At the completion of any slave transaction, either the SA_OK or SA_FAIL interrupt status is updated in “I C Interrupt Status Register”. An optional interrupt can be sent to the Interrupt Controller, if enabled in SA_OK or SA_FAIL of the “I...
Page 153: Slave Clock Stretching
7.5.1 Slave Clock Stretching When the Tsi578 is a slave, the external master generates the I C clock (I2C_SCLK). If the Tsi578 must access the internal register bus, I2C_SCLK is held low until data is available on a register read, or until a register write completes.
Page 154: Slave Device Addressing
C Interface > Tsi578 as I C Slave 7.5.2 Slave Device Addressing The Tsi578 supports 7-bit device addressing. The device address of the Tsi578 is set in the SLV_ADDR field of the “I C Slave Configuration Register”. For the Tsi578 to respond to an external master, the...
Page 155: External I C Register Map
7. I C Interface > Tsi578 as I C Slave 7.5.4 External I C Register Map Table 17 lists the register map that is visible to external I C devices. The lowest peripheral address maps to the LSB of the register, while the highest peripheral address maps to the MSB of the register.
Page 156: Slave Write Data Transactions
17. In addition, a write that hits the most significant byte of the “Externally Visible I C Internal Write Address Register” (peripheral address 0x07) has the side-effect of triggering a write to a register on the Tsi578 internal register bus. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 157: Slave Read Data Transactions
For example, a read that hits the LSB of the “Externally Visible I C Internal Read Address Register” (peripheral address 0x14), also triggers a read from a register on the Tsi578 internal register bus. 7.5.7 Slave Internal Register Accesses The Tsi578 allows external masters to access all of its internal registers through the externally visible C registers.
Page 158: Slave Access Examples
This section shows a slave internal register access by an external master. The following abbreviations are used: <S> Start condition <R> Restart condition <SLVA> The 7-bit Tsi578 slave address (that matches SLV_ADDR) <PA=#> 8-bit peripheral address (current setting viewable in SLV_PA) <A> Acknowledge (ACK) <N> Not acknowledge (NACK) <P>...
Page 159 C Slave 3. External device does an Alert Response request. Because ALERT_FLAG is asserted, the alert response address is ACK’d and the Tsi578 slave address is returned. C Sequence: <S><0001100><W><A><RD=SLVA+0><N><P> Following the transaction, SLV_PA is 0x84 (unchanged from previous transaction) and interrupt status SA_OK asserts.
Page 160 7. I C Interface > Tsi578 as I C Slave 6. External device sets up “I2C_SCLK Low and Arbitration Timeout Register” address (0x354) in EXI2C_REG_WADDR, then writes three registers back-to-back with 0x11223344, 0x55667788, and 0x99AABBCC. Because of the register auto-increment, and because the PA auto-wraps from 0x07 to 0x04, the writes can be completed in a stream.
Page 161: Resetting The I 2 C Slave Interface
When a chip reset is applied, the I C slave interface immediately returns to the idle state. Any active transfer, to or from the Tsi578 when the reset is asserted, is interrupted. All registers are initialized by a full-chip reset.
Page 162: Figure 33: I 2 C Mailbox Operation
Polls Status Until Flag Up EXI2C_MBOX_OUT Reads Mailbox Host is Interrupted (OMB_EMPTY) EXI2C_MBOX_OUT Flag Goes Down The incoming and outgoing I C mailbox registers are discussed further in the following sections. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 163: Incoming Mailbox
As a host, the Tsi578 cannot effectively receive a SMBus Host Notify message sent by another non-host SMBus device acting as a master. In addition, the Tsi578 cannot effectively act as a non-host SMBus device and receive commands from an external SMHost. Although the Tsi578 responds as a slave to the SMBus protocols, they are processed relative to the slave interface functionality.
Page 164: Unsupported Smbus Features
The Tsi578 master interface functionality supports a subset of the SMBus Protocols (see Figure 34). In all cases, the Tsi578 masters a transaction to another SMBus device. All register and register field references are to the following I C master interface registers: •...
Page 165: Figure 34: Smbus Protocol Support
Shaded = Slave is driving the bus * For information about SIZE and WRITE, see “I C Master Control Register”. For information about PA_SIZE and DORDER, see “I C Master Configuration Register”. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 166: Smbus Alert Response Protocol Support
7.7.3 SMBus Alert Response Protocol Support The Tsi578 supports the SMBus Alert Response Protocol as either master or slave. As a master, an external device can be polled using a master read operation. As a slave, the Tsi578 slave interface responds to the Alert Response Address with the Tsi578’s slave device address based on the value of...
Page 167: Figure 36: Boot Load Sequence
9 Clocks with I2C_SD released High * For information about page mode boundary, see PAGE_MODE in “I C Boot Control Register”. For information about PA_SIZE, see “I C Master Configuration Register”. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 168: Idle Detect
If a device was in the middle of sending a byte, the clocks pulses will allow it to finish the transmission. The I2C_SD left high by the master (the Tsi578) will appear as a NACK to the device and it will not try to transmit another byte, but will leave the I2C_SD signal free so that another master can force a START or STOP condition.
Page 169: Eeprom Device Detection
EEPROMs that use the lower 3 bits of their address as a 256-byte page indicator. For each block of 8 bytes loaded, the first 4 bytes are the register address on the internal Tsi578 register bus, and the next 4 bytes are the 32-bit data value to be written to the register. No checking is completed for register address or data validity.
Page 170: Chaining
EEPROM. When 2-byte address mode is selected, any number of registers greater than 8191 (8 KB-1 = 0x1FFF) aborts the boot load from the EEPROM. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 171: Table 18: Format For Boot Loadable Eeprom
I2C_MST_CFG 0x01 0x02 0x03 0x04 RegData = 0x0102_0304 0x10 0x00 0x01 0xD1 0x14 RegAdr = 0x1D114 I2C_MST_TDATA 0x14 0x05 0x06 0x07 0x08 RegData = 0x0506_0708 >= 0x18 Unused by Boot Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 172: I2C Boot Time
The number of chaining operations • The clocking speeds of the master devices Because many of these parameters are outside the control of the Tsi578, the boot time cannot be predicted with complete accuracy. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 173: Accelerating Boot Load
2. If the EEPROM supports reading at higher than 100-kHz clock speeds, the timing parameters can be changed during boot load. The success of this depends on the bus properties because the Tsi578 does not contain the Schmitt Triggers or slope controlled outputs needed to guarantee conformance to the 400-kHz high-speed mode.
Page 174: Error Handling
7. I C Interface > Error Handling Error Handling The Tsi578 handles a number of I C errors and reports them with status bits, as summarized in Table Table 21: I C Error Handling Interrupt Status Bit Error Cause Access Type...
Page 175 Initialization load aborted BL_FAIL (BLERR) load, including bytes 2-7 of a register count not containing 0xFF. a. To determine the setting of the interrupt status bits, see “I C Interrupt Status Register”. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 176: Interrupt Handling
(see “Events versus Interrupts”. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 177: Events Versus Interrupts
As long as all event enables are set (the reset state), then the behavior is logical (see “Interrupt Handling”). Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 178: Figure 38: I 2 C Event And Interrupt Logic
IMBW (Incoming Mailbox Write Event) BL_FAIL (Boot Load Fail) BLTO (Boot Load Timeout Error) BLERR (Boot Load Error Event) BLSZ (Boot Load Size Error Event) BLNOD (Boot Load No Device Event) Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 179: Timeouts
It is up to software to decide how to handle this error. Because any operation was aborted without correct termination (no Stop), it is possible that the external device is left in an invalid state. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 180 If the Tsi578 I C master detects another master corrupting the <Start><Slave Address><Read/Write> bits it has transmitted, the Tsi578 I C master reverts to waiting for bus idle then tries again. The arbitration timeout continues to run in this case. If the...
Page 181 Register”. The boot_complete signal is asserted when the boot load timeout expires. If the boot timeout is not desired, then the EEPROM programming should immediately write the I2C_BOOT_DIAG_TIMER.COUNT to 0 to disable the timeout. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 182: Figure 39: I 2 C Timeout Periods
Idle Detect EEPROM Reset Wait for Bus Idle Boot Adr Boot Timeout Master Only Load Regs Chain Load Regs From existing hard reset to Stop condition that terminates the boot load sequence Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 183: Bus Timing
At the start of a master transaction through the “I C Master Control Register”, when the START condition is generated • Upon a chain operation during boot load Timing parameters are discussed further in the following sections. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 184: Figure 40: I 2 C Bus Timing Diagrams
I2C_SD Data Bit or Ack/Nack Master or Slave I2C_SCLK Setup Hold Nominal Low Nominal High I2C_SCLK High/Low Master Only Minimum Low Minimum High RESET Idle Detect Post-Reset Idle I2C_SCLK Not Idle Idle Timeout Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 185: Start/Restart Condition Setup And Hold
Stop would be a Start; therefore, the Start Setup fulfills the same use as a Stop Hold or Stop-to-Start buffer time. This parameter is used by the Tsi578 as a master when generating the Stop condition. If the I2C_SCLK signal was prematurely pulled low (0) by an external master or slave, this would be seen as a collision event.
Page 186: I2C_Sclk Nominal And Minimum Periods
7.13.4 I2C_SCLK Nominal and Minimum Periods These parameters are used by the Tsi578 as a master to generate the I2C_SCLK clock. The master must obey the minimum times to conform to the I C Specification, and must also attempt to regulate the overall I2C_SCLK frequency to a defined period.
Page 187: Performance
Performance This chapter is a detailed description of the packet switching performance characteristics of the Tsi578. It consists of the following general topics: • “Overview” on page 187 • “Performance Monitoring” on page 188 • “Configuring the Tsi578 for Performance Measurements” on page 192 •...
Page 188: Performance Monitoring
For example, if a single stream of packets passing from one ingress port to a single egress port is the only traffic handled by the Tsi578, it is possible to specify the latency for the packets in this stream.
Page 189: Table 23: Performance Monitoring Parameters
Threshold Register” on page 355 • “RapidIO Port x Receiver Input Queue Congestion Status Register” on page 357 • “RapidIO Port x Receiver Input Queue Congestion Period Register” on page 359 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 190: Traffic Efficiency
8. Performance > Performance Monitoring The following sub-sections describe the use of these parameters for monitoring the performance of the serial RapidIO ports in Tsi578. 8.2.1 Traffic Efficiency To characterize the efficiency of system traffic, the following parameters are used: 1.
Page 191: Bottleneck Detection
8.2.5 Resetting Performance Registers The Inbound and Outbound performance registers are both read and writable. These registers are cleared after every read and saturate at the maximum counter values. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 192: Configuring The Tsi578 For Performance Measurements
It is expected that configurations different from the two described will have performance figures between the two values specified. There are many controls in the Tsi578 that allow a system designer to optimize their system interconnect performance. These controls can be categorized as clock speeds, ISF arbitration settings, RapidIO packet scheduling and buffer management settings.
Page 193: Tsi578 Rapidio Transmission Scheduler Settings
0 packets are accepted. Port-to-Port Performance Characteristics The most intuitively obvious performance measurements of the Tsi578’s use port-to-port traffic models to characterize the maximum possible throughput and minimum latency performance of the Tsi578. In this case, all traffic is of uniform size and the same priority. Due to the simple type of traffic, the throughput and latency performance numbers do not change with the priority of the packets.
Page 194: Packet Throughput Performance
Due to the asynchronous ability of the clock frequencies within the device, the latency numbers can vary as much by ne 312.5 MHz clock period and one reference clock (S_CLK) period. The Tsi578 is designed to allow high priority traffic to bypass low priority traffic in periods of contention, as allowed in the RapidIO protocol specification. 8.4.2...
Page 195: Multicast Performance
Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 196: Congestion Detection And Management
DEPTH parameter. The behavior and effects of the various tick timers and counters is described in the flow chart shown in Figure Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 197: Figure 42: Congestion And Detection Flowchart
>= Congestion Threshold Clear Congestion Period Counter Set OUTB_DEPTH interrupt Error Rate Bias timer expire Decrement Congestion Counter Congestion Counter read by software Reset Error Rate Bias timer Wait for next packet Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 198: Congestion Registers
8. Performance > Congestion Detection and Management 8.5.1 Congestion Registers The Tsi578 contains registers in every port that can be used for the detection and monitoring of ingress and egress queue levels. The registers and their descriptions are as follows: •...
Page 199 Figure 43 on page 200 is an example of what the congestion registers may contain at various times during port operation. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 200: Figure 43: Congestion Example
326). When the OUTB_DEPTH interrupt is asserted, a port-write packet can be generated which causes an in-band notification of the condition that can be routed to any host in the system. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 201: Jtag Interface
“JTAG Register Access Details” on page 202 Overview The JTAG interface in Tsi578 is fully compliant with IEEE 1149.6 Boundary Scan Testing of Advanced Digital Networks as well as IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture standards. There are five standard pins associated with the interface (TMS, TCK, TDI, TDO and TRST_b) which allow full control of the internal TAP (Test Access Port) controller.
Page 202: Jtag Device Identification Number
The JTAG device ID number for the Tsi578 is 0x20573167 JTAG Register Access Details The Tsi578 has the capability to read and write registers through the JTAG interface. Prior to using the IEEE Register Access Command feature, the part must be reset by driving TRST_b low.
Page 203: Write Access To Registers From The Jtag Interface
Error and Ready bits. The next 32 bits are data. The rest of the shifted out data can be discarded. 5. Verify that the Error bit is at logic low and the Ready bit is at logic high. 6. Go back to step two to perform another read. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 204 9. JTAG Interface > JTAG Register Access Details Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 205: Clocks, Resets And Power-Up Options
“Power-up Options” on page 212 10.1 Clocks The Tsi578 has three input clocks (S_CLK_p/n, P_CLK and I2C_SCLK) that are used to produce the Tsi578’s internal clock domains. In addition to these reference clocks, each RapidIO ingress port contains independent receive clock domains, one for each lane.
Page 206: Clocking Architecture
10.1.1 Clocking Architecture The Tsi578 device relies on the reference clock (S_CLK_p/n) to generate most clocks inside device. S_CLK_p/n is fed into each SerDes. On the receive side, each SerDes recovers clocks from the data stream. In 4x mode, four different synchronous clocks are extracted (RXCLKA..D). In 1x mode, either one (RXCLKA) or two (RXCLKA..B) clocks are recovered.
Page 207: Serdes Clocks
10.1.2 SerDes Clocks All SerDes in Tsi578 use the same external reference clock (S_CLK_p/n). Depending on the pin or register setup, the SerDes generates the appropriate clocks to serialize/deserialize the data as well as the clocks for the internal logic. On the Receive side, each lane of the SerDes recovers their own clocks.
Page 208: Clock Domains
10. Clocks, Resets and Power-up Options > Clocks 10.1.4 Clock Domains The Tsi578 contains a number of clock domains that are generated from the two input reference clocks. These domains are detailed in Table 27. For more information about special line rate support see “Clocking”...
Page 209: Resets
1 (self-reset) In both cases, when the Tsi578 is reset it goes through its full reset and power-up sequence. All state machines and the configuration registers are reset to the original power on states. Lookup tables are left in an undefined state after reset. It is recommended that lookup tables be completely initialized after a reset to ensure deterministic operation.
Page 210 Self-reset of the Tsi578 may not be sufficient in systems which require other components to be reset at the same time as the Tsi578. The Tsi578 supports system control of resets in two ways. First, the Tsi578 can assert the INT_b interrupt so that a local processor can trigger a reset through the Tsi578’s HARD_RST_b pin.
Page 211: Per-Port Reset
10.2.4 JTAG Reset The JTAG TAP controller’s reset is independent of the Tsi578 functional resets. For boundary scan operation, the TAP controller can be reset with either the external pin TRST_b or by holding the pin TMS asserted for more than five TCK cycles.
Page 212: Power-Up Options
After power-up, the TAP controller can be reset at any time and this does not affect the Tsi578 operation. Normal functional reset is still required to reset the device’s internal registers. Reset of the Tsi578 does not reset the TAP.
Page 213: Table 28: Power-Up Options Signals
0 = A, B, C, D 1 = D, C, B, A Override SP_RX(TX)_SWAP using RX(TX)_SWAP field in the “SRIO MAC x Digital Loopback and Clock Selection Register” on page 377. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 214: Default Port Speed
When the SP_IO_SPEED[1:0] pins are left unconnected in the board, the device’s internal pull-ups configure the Tsi578 to 3.125 Gbit/s (default). The speed can be overridden by the IO_SPEED field in “SRIO MAC x Digital Loopback and Clock Selection Register” on page 377.
Page 215: Signals
Signals This chapter describes the signals and pinout of the Tsi578. It includes the following information: • “Overview” on page 215 • “Endian Ordering” on page 216 • “Port Numbering” on page 216 • “Signal Groupings” on page 218 •...
Page 216: Endian Ordering
The following table shows the mapping between port numbers and the physical ports. These port numbers are used within the destination ID lookup tables for ingress RapidIO ports and in numerous register configuration fields Table 30: Tsi578 Port Numbering Port Number RapidIO Port...
Page 217 11. Signals > Port Numbering Table 30: Tsi578 Port Numbering Port Number RapidIO Port Mode Serial Port 13 (SP13) Serial Port 14 (SP14) 1x or 4x Serial Port 15 (SP15) Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 218: Signal Groupings
S_CLK_[p,n] Ref Clks SP14_T[A,B,C,D]_[p,n] P_CLK SP14_R[A,B,C,D]_[p,n] REF_AVDD SP14_REXT Ports MCES Multicast 14,15 SP14_AVDD SP14_MODESEL SP14_PWRDN SP15_PWRDN Port SP_IO_SPEED[1:0] Config Logic SP0, 2, 4 …. 14 Pwr/Gnd SP_VDD VSS_IO VDD_IO Pwr/Gnd Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 219: Table 31: Tsi578 Signal Descriptions
11. Signals > Signal Groupings Table 31 describes the Tsi578 signals Table 31: Tsi578 Signal Descriptions Pin Name Type Description Recommended Termination Signal Port Numbering PORT n - 1x/4x Mode Serial RapidIO PORT (n+1) - 1x Mode Serial RapidIO Port {n} where {n} = 0, 2, 4, 6, 8, 10, 12, 14 Serial Port Transmit No termination required.
Page 220 11. Signals > Signal Groupings Table 31: Tsi578 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination SP{n}_RA_n I, SRIO Port n Lane A Differential Inverting Receive Data DC blocking capacitor of 0.1uF input (4x node) in series Port n Lane A Differential Inverting Receive Data...
Page 221 11. Signals > Signal Groupings Table 31: Tsi578 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination SP{n}_PWRDN I/O, Port n Transmit and Receive Power Down Control Pin must be tied off according to LVTTL, This signal controls the state of Port n and Port the required configuration.
Page 222 11. Signals > Signal Groupings Table 31: Tsi578 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Serial Port Speed Select SP_IO_SPEED[1] I/O, Serial Port Transmit and Receive operating Pin must be tied off according to LVTTL, frequency select, bit 1. When combined with the required configuration.
Page 223 11. Signals > Signal Groupings Table 31: Tsi578 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Serial Port Lane Ordering Select SP_RX_SWAP I, LVTTL, Configures the order of 4x receive lanes on serial No termination required. ports[[0,2,4,6, ...14]. Internal pull-down can be used 0 = A, B, C, D for logic 0.
Page 224 If self-reset is selected, this pin remains asserted until the self reset is complete. If the Tsi578 is reset from the HARD_RST_b pin, this pin is de-asserted and remains de-asserted after HARD_RST_b is released.
Page 225 No termination required. Internal pins represent the values for the lower 2 bits of the pull-up can be used for logic 1. 7-bit address of Tsi578 when acting as an I Pull up to VDD_IO through 10K slave (see “I C Slave Configuration Register”...
Page 226 C Pin Select. No termination required. Internal pull-up can be used for logic 1. Together with the I2C_SA[1,0] pins, the Tsi578 determines the lower 2 bits of the 7-bit address of Pull up to VDD_IO through a the EEPROM address it boots from.
Page 227: Pinlist And Ballmap
11. Signals > Pinlist and Ballmap Table 31: Tsi578 Signal Descriptions (Continued) Pin Name Type Description Recommended Termination Power Supplies SP_AVDD Port n and n+1: 3.3V supply for bias generator Refer to decoupling circuitry. This is required to be a low-noise supply.
Page 228 11. Signals > Pinlist and Ballmap Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 229: Serial Rapidio Registers
Serial RapidIO Registers This chapter describes the Tsi578 registers. The following topics are discussed: • “Overview” on page 229 • “Port Numbering” on page 231 • “Conventions” on page 231 • “Register Map” on page 233 • “RapidIO Logical Layer and Transport Layer Registers” on page 245 •...
Page 230: Reserved Register Addresses And Fields
(Section 12.5 to 12.7), the Reserved fields should always be written as 0. For the IDT implementation-specific registers (Section 12.8 to 13.2), a read modify write operation must be performed for register reserved fields that have an undefined reset value. Other reserved fields should always be written as 0 unless otherwise noted.
Page 231: Port Numbering
Two notations are used to refer to these registers. • In the first notation, a lower-case letter such as “x” is used as a wildcard character. For example, Sx_DESTID refers to S0_DESTID, S1_DESTID, S2_DESTID, and so on. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 232 0. Port 0 should not be powered-down. Refer to “Special Conditions for Port 0 Power Down” on page 73 for more information Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 233: Register Map
12. Serial RapidIO Registers > Register Map 12.4 Register Map Table 35 gives an overview of the Tsi578 register map. Table 35: Register map overview Register Group Start Address End Address “RapidIO Logical Layer and Transport Layer Registers” on page 245...
Page 234: Table 36: Register Map
12. Serial RapidIO Registers > Register Map Table 36 shows the Tsi578 register map. Table 36: Register Map Offset Register Name RapidIO Logical Layer and Transport Layer Registers 00000 RIO_DEV_ID “RapidIO Device Identity CAR” on page 246 00004 RIO_DEV_INFO “RapidIO Device Information CAR” on page 247...
Page 235 “RapidIO Serial Port x Local ackID Status CSR” on page 276 0014C - 00154 Reserved 00158 SP0_ERR_STATUS “RapidIO Port x Error and Status CSR” on page 278 0015C SP0_CTL “RapidIO Serial Port x Control CSR” on page 281 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 236 “RapidIO Logical and Transport Layer Address Capture CSR” on page 290 01018 RIO_LOG_ERR_DEVID “RapidIO Logical and Transport Layer Control Capture CSR” on page 292 0101C RIO_LOG_ERR_CTRL_INFO “RapidIO Logical and Transport Layer Device ID Capture CSR” on page 291 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 237 0105C - 1064 Reserved 01068 SP0_ERR_RATE “RapidIO Port x Error Rate CSR” on page 304 0106C SP0_ERR_THRESH “RapidIO Port x Error Rate Threshold CSR” on page 306 01070 - 0107C Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 238 “RapidIO Port x Route Config DestID CSR” on page 314 10074 SPBC_ROUTE_CFG_ “RapidIO Port x Route Config Output Port CSR” on page 315 PORT 10078 SPBC_ROUTE_BASE “RapidIO Port x Local Routing LUT Base CSR” on page 316 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 239 Serial Port 12 11D00 - 11DFC Serial Port 13 11E00 - 11EFC Serial Port 14 11F00 - 11FFC Serial Port 15 12000 - 12FFC Tsi578 Reserved Non-Broadcast Per Port Registers 13000 Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 240 Register” on page 350 13084 SP0_TX_Q_STATUS “RapidIO Port x Transmitter Output Queue Congestion Status Register” on page 352 13088 SP0_TX_Q_PERIOD “RapidIO Port x Transmitter Output Queue Congestion Period Register” on page 354 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 241 All registers as for SP0, offsets 0x13000 - 0x130FC. 13700 - 137AC Serial Port 7 Same set of registers as for SP0, offsets 0x13000 - 0x130AC. The registers at offsets 0x130B0 - 0x130FC are excluded. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 242 “RapidIO Port Write Outstanding Request Register” on page 393 1AFFC Reserved Multicast Registers 1B000 RIO0_MC_REG_VER “RapidIO Multicast Register Version CSR” on page 395 1B004 RIO0_MC_LAT_LIMIT “RapidIO Multicast Maximum Latency Counter CSR” on page 396 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 243 Serial Port 14 1BF00 - 1BFFC Serial Port 15 1C000 - 1CFFC Tsi578 Reserved C Registers 1D000-1DFFC See the I C Register Chapter for a full description of the I C registers. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 244 413 1E0B8-1E0BC Reserved 1E0E0 SMAC{0,2,4,6,8,10,12,14}_PG_CT “SerDes Lane 3 Pattern Generator Control Register” on page 406 1E0E4-1E0EC Reserved 1E0F0 SMAC{0,2,4,6,8,10,12,14}_PM_CT “SerDes Lane 3 Pattern Matcher Control Register” on page 410 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 245: Rapidio Logical Layer And Transport Layer Registers
When an individual port is powered down, the RapidIO Logical Layer and Transport Layer Registers for that port are read only and return 0. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs a self-reset. The registers within a port are also reset by a “Port...
Page 246: Rapidio Device Identity Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.1 RapidIO Device Identity CAR This register identifies the device and vendor information for the Tsi578. Register name: RIO_DEV_ID Register offset: 00000 Reset value: 0x0578_000D Bits 00:7 DEV_ID...
Page 247: Rapidio Device Information Car
28:31 METAL_REV Indicates the version of the metal layers for the given silicon 0b0000 version. This value may change with different metal revisions of the device. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 248: Rapidio Assembly Identity Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.3 RapidIO Assembly Identity CAR This register contains assembly identification information about the Tsi578. Register name: RIO_ASBLY_ID Register offset: 00008 Reset value: 0x0001_000D Bits 00:07 ASBLY_ID 08:15 ASBLY_ID...
Page 249: Rapidio Assembly Information Car
16:31 EXT_FEAT_PTR Extended Features Pointer 0x0100 This is the pointer to the first entry in the extended features list. In the Tsi578 it points to the Serial Physical Layer (see “RapidIO Physical Layer Registers” on page 268). Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 250: Rapidio Processing Element Features Car
1 = Processing element is a switch. Ftype 8 packets with hop count equal to 0 are routed to the register bus. 4:20 Reserved Multicast 0 = Does not support the multicast extensions 1 = Supports the multicast extensions Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 251 For the Tsi578, packets are forwarded according to the configuration of the ingress port’s lookup table. This bit is not used in the control of any functionality in the Tsi578. 0 = Device supports 8-bit destination IDs only 1 = Device supports 8-bit and 16-bit destination IDs...
Page 252: Rapidio Switch Port Information Car
Port Number Undefined The port number that received the maintenance read packet that caused this register to be read. This value is undefined if the register is read through JTAG. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 253: Rapidio Source Operation Car
12.5.7 RapidIO Source Operation CAR This register defines the set of RapidIO I/O logical operations that can be issued by the Tsi578. The device can generate I/O logical maintenance read and write requests if it is required to access CARs and CSRs in other processing elements.
Page 254 12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers (Continued) Reset Bits Name Description Type Value PORT_WR Port-write operation The RapidIO ports support port-write generation to report errors. 30:31 Reserved Implementation defined Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 255: Rapidio Switch Multicast Support Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.8 RapidIO Switch Multicast Support CAR This register identifies the multicast programming model supported by a switch. The Tsi578 does not support the simple programming model (for more information, see the “RapidIO Multicast Mask Configuration Register”...
Page 256: Rapidio Route Lut Size Car
12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 12.5.9 RapidIO Route LUT Size CAR This register tells host software that the Tsi578 supports 512 destination IDs in its lookup table (LUT). When the LUT_512 bit in the “RapidIO Port x Mode CSR” on page 310...
Page 257: Rapidio Switch Multicast Information Car
0 = Single associate. One “associate” write is required per association between a destinationID and a multicast mask. 1 = Block association is supported (Not implemented in the Tsi578) ASSOC_SCOPE Defines the capabilities of a switch to associate a destination ID with a multicast mask on a per-inbound-port basis.
Page 258: Rapidio Host Base Device Id Lock Csr
Base Device ID for the processing element that is initializing this processing element. The HOST_BASE_ID set in this register does not enforce exclusive access to the device. It coordinates device identification during initialization and discovery. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 259: Rapidio Component Tag Csr
Register name: RIO_COMP_TAG Register offset: 0006C Reset value: 0x0000_0000 Bits 00:07 CTAG[0:7] 08:15 CTAG[8:15] 16:23 CTAG[16:23] 24:31 CTAG[24:31] Reset Bits Name Description Type Value 00:31 CTAG Component Tag Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 260: Rapidio Route Configuration Destid Csr
This field specifies the destination ID used to select an entry in the LUT when the “RapidIO Port x Route Config Output Port CSR” on page 315 register is read or written. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 261: Rapidio Route Configuration Output Port Csr
For future compatibility, write the value 0xFF to indicate an unmapped destination ID. When reading an unmapped value from the LUT, this field is set to 0xFF. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 262: Rapidio Route Lut Attributes (Default Port) Csr
If a packet needs to consult the default route and the default route is unmapped, the packet is discarded. “Port Numbering” on page 67 for a mapping of port numbers to physical ports. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 263: Rapidio Multicast Mask Configuration Register
This field is ignored when the MASK_CMD field indicates “Delete All Ports” or “Add All Ports”. When the register is read, this field returns the contents that were previously written. Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 264 1 = Port is enabled as an outbound port in the specified multicast mask. The Multicast_Mask and Egress_Port_Number were specified in a prior write to this register using the “Write_to_Verify” command. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 265: Rapidio Multicast Destid Configuration Register
The 8-bit destination ID or the least significant 8 bits of a 16-bit destination ID to be associated with the mask MASK_NUM_BASE. 16:31 MASK_NUM_ The multicast mask number [0:7] to be associated with the BASE destination ID configured above (0x0000 to 0x0007). Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 266: Rapidio Multicast Destid Association Register
0 = The association is for a small transport destination IDs 1 = The association is for a large transport destination IDs This field returns the previously written value when this register is read. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 267 “Write_To_Verify” with the LARGE field set accordingly. 0 = No association present 1 = Association present This bit is reserved on a write to this register. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 268: Rapidio Physical Layer Registers
When an individual port is powered down, the RapidIO Physical Layer Registers for that port are read only and return undetermined values. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs a self-reset. The registers within a port are also reset by a “Port...
Page 269 1x/4x serial port 0x0260 1x serial port 0x0280 1x/4x serial port 0x02A0 1x serial port 0x02C0 1x/4x serial port 0x02E0 1xserial port 0x0300 1x/4x serial port 0x0320 1x serial port Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 270: Rapidio 1X Or 4X Switch Port Maintenance Block Header
EF_PTR Extended Features Pointer 0x1000 Hard-wired pointer to the next block in the features data structure. 16:31 EF_ID Hard-wired Extended Features ID 0x0009 0x0009 = Switch with software recovery capability Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 271: Rapidio Switch Port Link Timeout Control Csr
5.4 seconds. When TVAL is 0, the timer is disabled. Note: Refer to “P_CLK Programming” on page 493 for information on programming options for the P_CLK frequency. 24:31 Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 272: Rapidio Switch Port General Control Csr
Reserved DISC Discovered This device has been located by the processing element responsible for system configuration. 1 = Device discovered by system host 0 = Device not discovered 3:31 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 273: Rapidio Serial Port X Link Maintenance Request Csr
011 = Reset. Writing this value causes the device to send four consecutive reset control symbols. 100 = Input-status Other values are reserved, but the Tsi578 sends a control symbol with the requested value. Integrated Device Technology Tsi578 User Manual www.idt.com...
Page 274 12. Serial RapidIO Registers > RapidIO Physical Layer Registers Writing to this register on a port in normal operation affects traffic on that port. This register should only be used on ports in an error state. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 275: Rapidio Serial Port X Link Maintenance Response Csr
27:31 LINK_STAT Link Status Link status field from the link-response control symbol. Other values are reserved. 0b00010 = Error 0b00100 = Retry-stopped 0b00101 = Error-stopped 0b10000 = OK Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 276: Rapidio Serial Port X Local Ackid Status Csr
8:18 Reserved 19:23 OUTSTANDING Outstanding Acknowledge IDs The first unacknowledged ackID. Note: When software writes to OUTBOUND field, the OUTSTANDING is also updated with the value in OUTBOUND. 24:26 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 277 Caution: Changing the OUTBOUND field when there are packets being exchanged with a link partner results in non-deterministic ackID values. It is likely that a fatal error due to ackID mismatch will result. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 278: Rapidio Port X Error And Status Csr
Port x Error Rate CSR” on page 304. 8:10 Reserved OUTPUT_RE Output Retry-encountered R/W1C Outbound port has encountered a retry condition.This bit is set when the Output Retry-stopped bit (bit 13) is set. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 279 Inbound port is in the input error-stopped state. 24:26 Reserved PORT_W_PEND Port-write Pending R/W1C Port has encountered a condition which required it to issue an I/O logical port-write maintenance request. Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 280 PORT_UNINIT Port Un-initialized Inbound and Outbound ports are not initialized. This bit and bit 30, PORT_OK, are mutually exclusive. This bit is set to a 1 after reset. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 281: Rapidio Serial Port X Control Csr
(that is, a 4x port degrades to a 1x port). • 000 = 1x port, lane 0 • 001 = 1x port, lane 2 • 010 = 4x port Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 282 0 = Inbound port is stopped and only routes or responds to maintenance requests. Other packets generate packet-not-accepted control symbols to force an error condition on the sending device. 1 = Inbound port responds to any packet. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 283 Caution: If error checking is disabled, corrupt maintenance packets may be accepted by the Tsi578. Even when error checking is disabled, a corrupt maintenance write request is ignored by the registers. If error checking is enabled, corrupt maintenance packets are not accepted.
Page 284 Packet ackIDs are not modified in the RapidIO Serial Port x Local ackID Status CSR. PORT_TYPE Port Type Indicates the port type 1 = Serial port Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 285: Rapidio Error Management Extension Registers
Not all Error Management Extension registers are supported in the Tsi578. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs a self-reset. The registers within a port are also reset by a “Port...
Page 286: Port Behavior When Error Rate Failed Threshold Is Reached
“RapidIO Port x Error and Status CSR” on page 278. Caution: When both bits are set, only the stored packets in the queue are discarded. Any packets sent after are forwarded. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 287: Rapidio Error Reporting Block Header
Hard wired pointer to the next block in the data structure. 0000 = Last extended feature block 16:31 EF_ID Hard-wired Extended Features ID 0x0007 0x0007 = EF ID for error management capability Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 288: Rapidio Logical And Transport Layer Error Detect Csr
Illegal Response R/W0C A maintenance response was received with a hop count of 0. L_UNSUP_TRANS Unsupported Transaction R/W0C A port-write transaction was received with a hop count of 0. 10:31 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 289: Rapidio Logical And Transport Layer Error Enable Csr
0 = disable L_UNSUP_TRANS 1 = enable L_UNSUP_TRANS 10:31 Reserved a. All bits in this register enable bits in “RapidIO Logical and Transport Layer Error Detect CSR” on page 288. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 290: Rapidio Logical And Transport Layer Address Capture Csr
Reserved WDPTR Reserved Reset Bits Name Description Type Value Reserved 8:28 ADDRESS Address of the illegal maintenance request received. Reserved WDPTR Word pointer from the illegal maintenance request received Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 291: Rapidio Logical And Transport Layer Device Id Capture Csr
Source ID Most Significant Byte Most significant byte of the source ID associated with the error (large transport systems only) 24:31 SRCID Source ID The sourceID associated with the error. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 292: Rapidio Logical And Transport Layer Control Capture Csr
Value FTYPE Format type associated with the error TTYPE Transaction type associated with the error 8:31 Reserved A value of 0x00000000 must be written to this register to clear it. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 293: Rapidio Port-Write Target Device Id Csr
16-bit DestID used in locally-generated port-write requests. LARGE_DESTID 0 = Port-write transactions are generated with an 8-bit destination ID. 1 = Port-write transactions are generated with a 16-bit destination ID. 17:31 Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 294: Rapidio Port X Error Detect Csr
1340, 1380, 13C0, 1400 Bits 00:07 IMP_SPEC Reserved _ERR 08:15 Reserved CS_CRC_E CS_ILL_ID CS_NOT_A PKT_ILL_A PKT_CRC_ PKT_ILL_ Reserved CKID SIZE 16:23 Reserved 24:31 Reserved LR_ACKID PROT_ Reserved DELIN_ CS_ACK_ LINK_TO _ILL Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 295 Received packet-not-accepted control symbol. R/W0C PKT_ILL_ACKID Received packet with unexpected ackID. R/W0C PKT_CRC_ERR Received a packet with a CRC error. R/W0C PKT_ILL_SIZE Received packet exceeds 276 bytes. R/W0C 15:25 Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 296 The link response it got back is supposed to contain the ACK_ID that the link partner is expecting in the next new packet it receives. The Tsi578 is indicating that it has already sent a packet with that ACK_ID and has received a packet accepted control symbol for it, and has moved to the next ACK_ID value.
Page 297: Rapidio Port X Error Rate Enable Csr
Reserved CS_CRC_ERR_ Enable error rate counting. Received Control Symbol with a CRC error. CS_ILL_ID_EN Enable error rate counting. Received an acknowledge control symbol with an unexpected ackID (packet-accepted or packet_retry). Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 298 Received unaligned /SC/or/PD/ or undefined code-group. CS_ACK_ILL_EN Enable error rate counting An unexpected acknowledge control symbol was received. LINK_TO_EN Enable error rate counting An acknowledge or Link-response is not received within the specified time-out interval. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 299: Rapidio Port X Error Capture Attributes Csr And Debug 0
For control symbols, only capture register 0 contains meaningful information. Software writes 0 to clear this bit and unlock all capture registers of port x. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 300: Table 40: Err_Type Values
Protocol Error 11100 Bit 28 = Reserved 11101 Bit 29 = DELIN_ERR Delineation Error 11110 Bit 30 = CS_ACKID_ILL Control Symbol Illegal AckID 11111 Bit 31 = LINK_TO Link Timeout Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 301: Rapidio Port X Packet And Control Symbol Error Capture Csr 0 And Debug 1
134C, 138C, 13CC, 140C Bits 00:7 CAPT_0[0:7] 8:15 CAPT_0[8:15] 16:23 CAPT_0[16:23] 24:31 CAPT_0[24:31] Reset Bits Name Description Type Value 0:31 CAPT_0 Character and control symbol or bytes 0 to 3 of packet header. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 302: Rapidio Port X Packet Error Capture Csr 1 And Debug 2
Reset value: 0x0000_0000 1354, 1394, 13D4, 1414 Bits CAPT_2[0:7] 8:15 CAPT_2[8:15] 16:23 CAPT_2[16:23] 24:31 CAPT_2[24:31] Reset Bits Name Description Type Value 0:31 CAPT_2 Byte 8 to 11 of the packet Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 303: Rapidio Port X Packet Error Capture Csr 3 And Debug 4
Reset value: 0x0000_0000 1358, 1398, 13D8, 1418 Bits CAPT_3[0:7] 8:15 CAPT_3[8:15] 16:23 CAPT_3[16:23] 24:31 CAPT_3[24:31] Reset Bits Name Description Type Value 0:31 CAPT_3 Byte 12 to 15 of the packet Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 304: Rapidio Port X Error Rate Csr
• 11 = No limit 16:23 PEAK The maximum value attained by the error rate counter. This value increments with ERR_RATE_CNT, but does not decrement except through a host controlled register write. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 305 If the value of the counter equals the error rate threshold trigger register, an error is reported. For more information see the RapidIO Interconnect Specification (Revision 1.3), Part 8: Error Management Extensions Specification. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 306: Rapidio Port X Error Rate Threshold Csr
• 01 = Set the error reporting threshold to 1 • 02 = Set the error reporting threshold to 2 • ... • FF - Set the error reporting threshold to 255 16:31 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 307: Idt-Specific Rapidio Registers
“RapidIO Serial Port x Control CSR” on page 281, both of which return 0x00000001 when read. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs a self-reset. The registers within a port are also reset by a “Port Reset”.
Page 308: Table 42: Idt-Specific Per-Port Performance Registers
11F00 1x Serial port Non-Broadcast Per-Port Registers The following table shows the IDT-specific per-port registers not defined by the RapidIO Interconnect Specification (Revision 1.3). It is not possible to broadcast to these registers. Table 42: IDT-Specific Per-Port Performance Registers Port...
Page 309: Rapidio Port X Discovery Timer
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.1 RapidIO Port x Discovery Timer This register defines discovery-timer value for the serial ports in 4x mode.. Register name: SP{BC,0..15}_DISCOVERY_TIMER Register offset: 10000, 11000, 11100, 11200, 11300, 11400, 11500, 11600, 11700, 11800, 11900,...
Page 310: Rapidio Port X Mode Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.2 RapidIO Port x Mode CSR This register defines the mode of operation for the ports, and contains the interrupt enables for the Multicast-Event control symbol and Reset control symbol. Register name: SP{BC,0..15}_MODE...
Page 311 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value LUT_512 LUT_512 Sets the mode of the destination ID lookup table 0 = Global LUT (64K destination IDs, assigned with resolution of 256 destination IDs)
Page 312: Rapidio Port X Multicast-Event Control Symbol And Reset Control Symbol Interrupt Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.3 RapidIO Port x Multicast-Event Control Symbol and Reset Control Symbol Interrupt CSR This register contains the interrupt status for Multicast-Event control symbols and Reset control symbols. Register name: SP{BC,0..15}_CS_INT_STATUS Register offset: 10008, 11008, 11108, 11208, 11308,...
Page 313: Rapidio Port X Rapidio Watermarks
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.4 RapidIO Port x RapidIO Watermarks This register controls ingress buffer allocation for reception of packets for each port (see “Egress Watermark” on page 95). Register name: SP{BC,0..15}_RIO_WM Register offset: 1000C, 1100C, 1110C, 1120C, 1130C,...
Page 314: Rapidio Port X Route Config Destid Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.5 RapidIO Port x Route Config DestID CSR This register and SPx_ROUTE_CFG_PORT operate together to provide indirect read and write access to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and RIO_ROUTE_CFG_PORT, except the “RapidIO Port x Route Config Output Port CSR”...
Page 315: Rapidio Port X Route Config Output Port Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.6 RapidIO Port x Route Config Output Port CSR This register and SPx_ROUTE_CFG_DESTID operate together to provide indirect read and write access to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and...
Page 316: Rapidio Port X Local Routing Lut Base Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.7 RapidIO Port x Local Routing LUT Base CSR This register is required for switch devices that operate in a large system. For small systems, this register is ignored. The serial port supports local and global routing LUT pages. The number of entries is defined by the “RapidIO Route LUT Size CAR”...
Page 317: Rapidio Multicast Write Id X Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.8 RapidIO Multicast Write ID x Register This register contains the Multicast ID, which is associated to the multicast mask registers. The switch supports eight multicast groups and the Multicast ID registers for each multicast group must contain unique values.
Page 318: Rapidio Multicast Write Mask X Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.9 RapidIO Multicast Write Mask x Register This register contains the set of egress ports where a multicast packet is sent when it matches the destination ID associated with the mask. These bits form the multicast vector used by the broadcast buffer to determine which egress ports the packet is copied to.
Page 319: Rapidio Port X Control Independent Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.10 RapidIO Port x Control Independent Register This register is used for error recovery. Register name: SP{0..15}_CTL_INDEP Register offset: 13004, 13104, 13204, 13304, 13404, 13504, 13604, 13704, 13804, 13904, 13A04, Reset value: 0x0100_0000...
Page 320 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value DEBUG_MODE Mode of operation 0 = Normal 1 = Debug mode Debug mode unlocks the capture registers for writing and enables the debug packet generator feature.
Page 321 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value IRQ_EN Interrupt Error Report Enable If enabled, the interrupt signal is high when the IRQ_ERR bit is set to MAX_RETRY_EN Maximum Retry Report Enable If enabled, the port-write and interrupt report an error when the...
Page 322: Rapidio Port X Send Multicast-Event Control Symbol Register
Reserved DONE 0= The Tsi578 sets this field to 0 when system software sets SEND to 1. 1 = The Tsi578 sets this field to 1 once it has sent the Multicast-Event control symbol. It indicates that the Tsi578 is ready to send another Multicast Event control symbol.
Page 323: Rapidio Port X Lut Parity Error Info Csr
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.12 RapidIO Port x LUT Parity Error Info CSR The RapidIO Port x LUT Parity Error Info CSR contains information about the look up operation that caused the parity error, as well as the LUT information associated with the parity error.
Page 324 “Lookup Table Parity” on page 26:27 Reserved 28:31 PORT_NUM The Tsi578 port number where packets are routed. If the port is unmapped (LUT_VLD = 0), then the field reads 0xF. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 325: Rapidio Port X Control Symbol Transmit
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.13 RapidIO Port x Control Symbol Transmit Writing to this register transmits a single control symbol to RapidIO. This register is only used for debug purposes. All control symbol fields are defined according to the RapidIO Interconnect Specification (Revision 1.3).
Page 326: Rapidio Port X Interrupt Status Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.14 RapidIO Port x Interrupt Status Register Register name: SP{0..15}_INT_STATUS Register offset: 13018, 13118, 13218, 13318, 13418, 13518, 13618, 13718, 13818, 13918, 13A18, Reset value: 0x0000_0000 13B18, 13C18, 13D18, 13E18, 13F18 Bits...
Page 327 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value ILL_TRANS_ERR Illegal Transfer Error R/W1C This bit is set to 1 when the following occurs: • Received transaction has reserved tt field for all but maintenance packets with hop count = 0 •...
Page 328 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value INB_DEPTH Inbound Depth Interrupt R/W1C This value is set when Input Queue Depth Count reaches the maximum number defined in the Input Queue Depth Threshold field in “RapidIO Port x Receiver Input Queue...
Page 329: Rapidio Port X Interrupt Generate Register
12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 12.8.15 RapidIO Port x Interrupt Generate Register This register can be used to generate the corresponding error in the “RapidIO Port x Interrupt Status Register” on page 326. When bits in the register are set, behavior associated with the error (port writes, interrupts) occur.
Page 330 12. Serial RapidIO Registers > IDT-Specific RapidIO Registers (Continued) Reset Bits Name Description Type Value INB_RDR_GEN Forces the INB_RDR bit to be set to 1. R/W1S This bit always reads as zero. Reserved Reserved R/W1S TEA_GEN Forces the TEA bit to be set to 1.
Page 331: Idt-Specific Performance Registers
12.9 IDT-Specific Performance Registers The registers in this section are specific to IDT’s switching products. The following table shows the IDT-specific per-port registers not defined by the RapidIO Interconnect Specification (Revision 1.3). It is not possible to broadcast to these registers...
Page 332: Rapidio Port X Performance Statistics Counter 0 And 1 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.1 RapidIO Port x Performance Statistics Counter 0 and 1 Control Register This register is used to control the performance statistics counters PS0 and PS1 registers. For every performance statistics register SPx_PSCy (where y refers to the Performance Statistics counter PS0 and PS1), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC0n1_CTRL register:...
Page 333 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS0_PRIO2 Performance Stats Reg PS0 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 334 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS0_TYPE Performance Stats Reg PS0 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 0 Register”...
Page 335 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS1_PRIO0 Performance Stats Reg PS1 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 336: Rapidio Port X Performance Statistics Counter 2 And 3 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.2 RapidIO Port x Performance Statistics Counter 2 and 3 Control Register This register is used to control the performance statistics counters PS2 and PS3 registers. For every performance stats register SPx_PSCy (where y refers to the Performance Statistics counter PS2 and PS3), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC2n3_CTRL register:...
Page 337 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS2_PRIO2 Performance Stats Reg PS2 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 338 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS2_TYPE Performance Stats Reg PS2 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 4 and 5 Control Register”...
Page 339 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS3_PRIO0 Performance Stats Reg PS3 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 340: Rapidio Port X Performance Statistics Counter 4 And 5 Control Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.3 RapidIO Port x Performance Statistics Counter 4 and 5 Control Register This register is used to control the performance statistics counters PS4 and PS5 registers. For every performance stats register SPx_PSCy (where y refers to the Performance Statistics counter PS4 to PS5), the following configurations (direction, type, and priority) are selected through the SP{0..15}_PSC4n5_CTRL register:...
Page 341 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS4_PRIO2 Performance Stats Reg PS4 Priority 2 Selection This value represents the packet priority 2 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 342 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 13:15 PS4_TYPE Performance Stats Reg PS4 Type Selection This value determines the type of performance statistics that is collected in the “RapidIO Port x Performance Statistics Counter 4 Register”...
Page 343 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value PS5_PRIO0 Performance Stats Reg PS5 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the “RapidIO Port x...
Page 344: Rapidio Port X Performance Statistics Counter 0 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.4 RapidIO Port x Performance Statistics Counter 0 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 345: Rapidio Port X Performance Statistics Counter 1 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.5 RapidIO Port x Performance Statistics Counter 1 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 346: Rapidio Port X Performance Statistics Counter 2 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.6 RapidIO Port x Performance Statistics Counter 2 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 347: Rapidio Port X Performance Statistics Counter 3 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.7 RapidIO Port x Performance Statistics Counter 3 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 348: Rapidio Port X Performance Statistics Counter 4 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.8 RapidIO Port x Performance Statistics Counter 4 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 349: Rapidio Port X Performance Statistics Counter 5 Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.9 RapidIO Port x Performance Statistics Counter 5 Register This register is used to collect performance statistics. These counters provide the means of accumulating statistics for the purposes of performance monitoring measurements: throughput and latency.
Page 350: Rapidio Port X Transmitter Output Queue Depth Threshold Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.10 RapidIO Port x Transmitter Output Queue Depth Threshold Register Queue depth registers are designed to allow for the rapid detection and notification of congestion. This register sets the Transmitter Queue Depth threshold, which is used in conjunction with “RapidIO...
Page 351 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:19 DEPTH This number is used to decide the congestion state of the output buffers. If the number of packets in the output queue meets or exceeds this number, the congestion counter is incremented.
Page 352: Rapidio Port X Transmitter Output Queue Congestion Status Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.11 RapidIO Port x Transmitter Output Queue Congestion Status Register This register is used to monitor data congestion in the output buffer. New packets accumulate in the output buffers, destined for the switching fabric. When the number of buffers in use equals or exceeds the threshold set in DEPTH field of the “RapidIO Port x Transmitter Output Queue Depth Threshold...
Page 353 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:31 CONG_THRESH Output Queue Depth Threshold 0x0000 If the CONG_CTR count is equal to the value in this field, an interrupt is reported to the system through the OUTB_DEPTH status bit in the “RapidIO Port x Interrupt Status Register”...
Page 354: Rapidio Port X Transmitter Output Queue Congestion Period Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.12 RapidIO Port x Transmitter Output Queue Congestion Period Register This register is used to monitor the duration of time that the output buffer is in congestion state. The CONG_PERIOD_CTR counter value is incremented for every N clock cycles specified by the CONG_PERIOD field in the “RapidIO Port x Transmitter Output Queue Depth Threshold...
Page 355: Rapidio Port X Receiver Input Queue Depth Threshold Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.13 RapidIO Port x Receiver Input Queue Depth Threshold Register Queue depth registers are designed to allow for the rapid detection and notification of congestion. This register sets the Receiver Queue Depth threshold, which is used in conjunction with “RapidIO...
Page 356 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:19 DEPTH This number is used to decide the congestion state of the input buffers. If the number of packets in the input queue meets or exceeds this number, the congestion counter is incremented.
Page 357: Rapidio Port X Receiver Input Queue Congestion Status Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.14 RapidIO Port x Receiver Input Queue Congestion Status Register This register is used to monitor data congestion in the input buffer. New packets accumulate in the input buffers, destined for the switching fabric. When the number of buffers in use equals or exceeds the threshold set in DEPTH field of the “RapidIO Port x Receiver...
Page 358 12. Serial RapidIO Registers > IDT-Specific Performance Registers (Continued) Reset Bits Name Description Type Value 16:31 CONG_THRESH Input Queue Depth Threshold 0x0000 If the CONG_CTR count is equal to the value in this field, an interrupt is reported to the system through the INB_DEPTH status bit in the “RapidIO Port x Interrupt Status Register”...
Page 359: Rapidio Port X Receiver Input Queue Congestion Period Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.15 RapidIO Port x Receiver Input Queue Congestion Period Register This register is used to monitor the duration of time that the input buffer is in congestion state. The CONG_PERIOD_CTR counter value is incremented for every N clock cycles specified by the CONG_PERIOD field in the “RapidIO Port x Receiver Input Queue Depth Threshold...
Page 360: Rapidio Port X Reordering Counter Register
12. Serial RapidIO Registers > IDT-Specific Performance Registers 12.9.16 RapidIO Port x Reordering Counter Register When a packet cannot make forward progress due to internal switching congestion, the internal switching fabric selects packets in an order different from the order in which the packets were received.
Page 361: Serial Port Electrical Layer Registers
The Serial Port Electrical Layer Registers are not defined in the RapidIO Interconnect Specification (Revision 1.3). They are specific to IDT’s switching products. These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs a self-reset. The registers within a port are also reset by a “Port...
Page 362: Bypass_Init Functionality
• RX_PLL_PWRON in the SMACx_CFG_CH3 register • RX_EN in the SMACx_CFG_CH0 register • RX_EN in the SMACx_CFG_CH1 register • RX_EN in the SMACx_CFG_CH2 register • RX_EN in the SMACx_CFG_CH3 register Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 363: Srio Mac X Serdes Configuration Channel 0
011 = transmitter fully enabled, all clocks running Other values are Reserved. This bit is read only unless BYPASS_INIT bit “SRIO MAC x SerDes Configuration Global” on page 372 is set to 1. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 364 Other values are reserved. RX_ALIGN_ Enable Word Alignment 0 = Alignment (framer) disabled 1 = Alignment enabled Note: Must be disabled during PRBS test (see “Bit Error Rate Testing (BERT)” on page Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 365 12. Serial RapidIO Registers > Serial Port Electrical Layer Registers (Continued) Reset Bits Name Description Type Value Reserved Note: Only write 1 to this reserved field. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 366: Srio Mac X Serdes Configuration Channel 1
011 = Transmitter fully enabled, all clocks running Other values are Reserved. This bit is read only unless BYPASS_INIT bit “SRIO MAC x SerDes Configuration Global” on page 372 is set to 1. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 367 Other values are reserved. RX_ALIGN_ Enable Word Alignment Must be disabled turned off during PRBS test (“Bit Error Rate Testing (BERT)” on page Reserved Note: Only write 1 to this reserved field. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 368: Srio Mac X Serdes Configuration Channel 2
Transmitter enable 000 = Off, no clocks running 011 = Transmitter fully enabled, all clocks running Other values are Reserved. This bit is read only unless SMACx_CFG_GBL[BYPASS_INIT] is set to Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 369 Other values are reserved. RX_ALIGN_E Enable Word Alignment Has to be turned off during PRBS test (“Bit Error Rate Testing (BERT)” on page Reserved Note: Only write 1 to this reserved field. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 370: Srio Mac X Serdes Configuration Channel 3
011 = transmitter fully enabled, all clocks running Other values are Reserved. This bit is read only unless BYPASS_INIT bit “SRIO MAC x SerDes Configuration Global” on page 372 is set to 1. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 371 Other values are reserved. RX_ALIGN_ Enable Word Alignment This bit must be disabled during PRBS test (“Bit Error Rate Testing (BERT)” on page Reserved Note: Only write 1 to this reserved field. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 372: Srio Mac X Serdes Configuration Global
ACJT Receiver Comparator Level 0x06 This sets the hysterisis level for AC JTAG (Table 47 on page 374). Refer to IEEE 1149.6 for setting the correct voltage levels. 16:18 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 373: Table 46: Tx_Lvl Values
949.1 0x03 5'b00011 958.8 0x04 5'b00100 968.5 0x05 5'b00101 978.2 0x06 5'b00110 987.9 0x07 5'b00111 997.6 0x08 5'b01000 1007.2 0x09 5'b01001 1016.9 5'b01010 1026.6 5'b01011 1036.3 5'b01100 1046.0 5'b01101 1055.7 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 374: Table 47: Ac Jtag Level Programmed By Acjt_Lvl[4:0]
0x1E 5'b11110 1220.3 0x1F 5'b11111 1230.0 Table 47: AC JTAG level programmed by ACJT_LVL[4:0] Vmin level peak-to-peak Vmin level peak ACJT_LVL[4:0] differential (mV) single-ended (mV) 5’h02 5’h03 5’h04 5’h05 5’h06 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 375 Table 47: AC JTAG level programmed by ACJT_LVL[4:0] Vmin level peak-to-peak Vmin level peak ACJT_LVL[4:0] differential (mV) single-ended (mV) 5’h07 5’h08 5’h09 5’h0A 5’h0B 5’h14 5’h15 5’h16 5’h17 5’h18 5’h19 5’h1A 5’h1B 1065 3176 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 376: Srio Mac X Serdes Configuration Globalb
Reserved Reserved 10:11 MPLL_PRES Controls the MPLL’s REF_CLK prescaler. CALE[1:0] Should be set to 2’b10 in Tsi578. Mapping: 00 = Reserved 01 = Reserved 10 = Divide REF_CLK by 2 11 = Unused Transition only during RESET or when the MPLL Is disabled.
Page 377: Srio Mac X Digital Loopback And Clock Selection Register
This timer is used to determine when a link is powered-up and enabled, but dead (that is, there is no link partner responding). When a link is declared dead, the transmitting port on the Tsi578 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue.
Page 378 CDR and elastic buffering from receive to transmit is not available. Reserved MAC_MODE After the Tsi578 is reset, this field reflects the configuration of the SPx_MODESEL. Writing to this register overrides the pin settings of SPx_MODESEL. 0 = MAC supports a single 1x/4x port.
Page 379 01 = 2.5Gbps 10 = 3.125Gbps 11 = Reserved Note: This field reflects the value on SP_IO_SPEED after reset. Writing to this register overrides a power up value of SP_IO_SPEED speed selection. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 380: Internal Switching Fabric (Isf) Registers
RDR_LIMIT Reorder Limit Enable. 0 = No limit 1 = Reordering of lower or same priority packets is limited by the value in RDR_LIMIT (recommended) Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 381 156.25 MHz, and TEA_OUT is at its default value of 0x0200. The TEA timeout period is: (0x0200) 2^15 * 6.4 ns = 107.4 ms. A value of 0x0000 disables the TEA timer. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 382: Fabric Interrupt Status Register
Indicates that a TEA has occurred on this port. Writing a 1 to this bit clears it and causes the IRQ signal to be de-asserted. PORT6_IRQ Serial port 6 IRQ R/W1C Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 383 PORT4_IRQ Serial port 4 IRQ R/W1C PORT3_IRQ Serial port 3 IRQ R/W1C PORT2_IRQ Serial port 2 IRQ R/W1C PORT1_IRQ Serial port 1 IRQ R/W1C PORT0_IRQ Serial port 0 IRQ R/W1C Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 384: Rapidio Broadcast Buffer Maximum Latency Expired Error Register
Port 8 violated the maximum multicast latency time, and will not be R/W1C multicast to. P7_ERR Port 7 violated the maximum multicast latency time, and will not be R/W1C multicast to. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 385 Port 1 violated the maximum multicast latency time, and will not be R/W1C multicast to. P0_ERR Port 0 violated the maximum multicast latency time, and will not be R/W1C multicast to. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 386: Rapidio Broadcast Buffer Maximum Latency Expired Override
Port 9 multicast mask is overridden once, every time this bit is written R/W1S as a 1. P8_SET Port 8 multicast mask is overridden once, every time this bit is written R/W1S as a 1. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 387 Port 1 multicast mask is overridden once, every time this bit is written R/W1S as a 1. P0_SET Port 0 multicast mask is overridden once, every time this bit is written R/W1S as a 1. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 388: Utility Unit Registers
12.12.1 Global Interrupt Status Register This register indicates which block within the Tsi578 has generated an interrupt. The interrupt requests from a given block are “ORed” together and the value of the output is reflected in this register. Register name: GLOB_INT_STATUS...
Page 389 Port 7 Interrupt PORT6 Port 6 Interrupt PORT5 Port 5 Interrupt PORT4 Port 4 Interrupt PORT3 Port 3 Interrupt PORT2 Port 2 Interrupt PORT1 Port 1 Interrupt PORT0 Port 0 Interrupt Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 390: Global Interrupt Enable Register
PORT13_EN Port 13 Interrupt Enable PORT12_EN Port 12 Interrupt Enable PORT11_EN Port 11 Interrupt Enable PORT10_EN Port 10 Interrupt Enable PORT9_EN Port 9 Interrupt Enable PORT8_EN Port 8 Interrupt Enable Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 391 PORT5_EN Port 5 Interrupt Enable PORT4_EN Port 4 Interrupt Enable PORT3_EN Port 3 Interrupt Enable PORT2_EN Port 2 Interrupt Enable PORT1_EN Port 1 Interrupt Enable PORT0_EN Port 0 Interrupt Enable Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 392: Rapidio Port-Write Timeout Control Register
0000 = Disabled and a port-write is sent once per event. 0001 = 167.7ms 0010 = 335.5ms 0100 = 671.1ms 1000 = 1.34s 1111 = 1.3us (Debug only) Other values are reserved. 4:31 Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 393: Rapidio Port Write Outstanding Request Register
16:31 PORTX_OREG Port x Port Write Outstanding Request When a bit is set, it indicates that an outstanding port-write still exists in the port-write arbiter. Bit 31 is Port 0. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 394: Mces Pin Control Register
10 = MCES pin is an output (see “MCS Reception” on page 11 = Reserved 4:31 Reserved Changing MCES_CTRL setting during operation may result in spurious Multicast Event Control Symbols being sent. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 395: Multicast Registers
12.13 Multicast Registers 12.13.1 RapidIO Multicast Register Version CSR This register identifies the multicast register interface version of the IDT specific registers that is supported by this device. Register name: RIO{0..15}_MC_REG_VER Register offset: 1B000,1B100, 1B200, 1B300, 1B400, 1B500, 1B600, 1B700, 1B800, 1B900, 1BA00, 1BB00,...
Page 396: Rapidio Multicast Maximum Latency Counter Csr
“RapidIO Broadcast Buffer Maximum Latency Expired Error Register” on page 384. Note: If MAX_MC_LAT is set to its maximum value, it is equivalent to the maximum time-to-live timeout value for packets. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 397: Rapidio Port X Isf Watermarks
Note: It is a programming error for this value to be greater than 7. This register must only be programmed after reset and not while traffic is flowing. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 398: Port X Prefer Unicast And Multicast Packet Prio 0 Register
Set the preferred traffic type within the same priority group. 0 = Multicast 1 = Unicast 8:27 Reserved 28:31 WEIGHT This sets the number of packets of the chosen type to be sent between non-chosen type. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 399: Port X Prefer Unicast And Multicast Packet Prio 1 Register
Set the preferred traffic type within the same priority group. 0 = Multicast 1 = Unicast 8:27 Reserved 28:31 WEIGHT Weight This sets the number of packets of the chosen type to be sent between non-chosen type. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 400: Port X Prefer Unicast And Multicast Packet Prio 2 Register
Set the preferred traffic type within the same priority group. 0 = Multicast 1 = Unicast 8:27 Reserved 28:31 WEIGHT Weight This sets the number of packets of the chosen type to be sent between non-chosen type. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 401: Port X Prefer Unicast And Multicast Packet Prio 3 Register
Set the preferred traffic type within the same priority group. 0 = Multicast 1 = Unicast 8:27 Reserved 28:31 WEIGHT Weight This sets the number of packets of the chosen type to be sent between non-chosen type. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 402: Serdes Per Lane Register
12.14 SerDes Per Lane Register This section details the access registers that control the functionality of the SerDes in Tsi578. The SerDes register offsets in this section are based on lane 0. In order to define lanes 1, 2, and 3 the offset is incremented by 0x40 for each lane. For example, 0x1E000 represents lane 0 of SerDes 0, 0x1E040 represents lane 1 of SerDes 0, 0x1E080 represents lane 2 of SerDes 0, and 0x1E0C0 represents lane 3 of SerDes 0.
Page 403: Serdes Lane 0 Pattern Generator Control Register
3 = Fixed word (pat0) 4 = DC balanced word (pat0, ~pat0) 5 = Fixed pattern: (000, pat0, 3FF, ~pat0) 6:7 = Reserved Note: This field returns to its reset value on reset Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 404: Serdes Lane 1 Pattern Generator Control Register
3 = Fixed word (pat0) 4 = DC balanced word (pat0, ~pat0) 5 = Fixed pattern: (000, pat0, 3FF, ~pat0) 6:7 = Reserved Note: This field returns to its reset value on reset Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 405: Serdes Lane 2 Pattern Generator Control Register
3 = Fixed word (pat0) 4 = DC balanced word (pat0, ~pat0) 5 = Fixed pattern: (000, pat0, 3FF, ~pat0) 6:7 = Reserved Note: This field returns to its reset value on reset Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 406: Serdes Lane 3 Pattern Generator Control Register
3 = Fixed word (pat0) 4 = DC balanced word (pat0, ~pat0) 5 = Fixed pattern: (000, pat0, 3FF, ~pat0) 6:7 = Reserved Note: This field returns to its reset value on reset Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 407: Serdes Lane 0 Pattern Matcher Control Register
0 = Disabled 1 = lfsr15 2 = lfsr7 3 = d[n] = d[n-10] 4 = d[n] = !d[n-10] 5:7 = Reserved Note: This field returns to its reset value on reset Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 408: Serdes Lane 1 Pattern Matcher Control Register
0 = Disabled 1 = lfsr15 2 = lfsr7 3 = d[n] = d[n-10] 4 = d[n] = !d[n-10] 5:7 = Reserved Note: This field returns to its reset value on reset Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 409: Serdes Lane 2 Pattern Matcher Control Register
0 = Disabled 1 = lfsr15 2 = lfsr7 3 = d[n] = d[n-10] 4 = d[n] =!d[n-10] 5:7 = Reserved Note: This field returns to its reset value on reset Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 410: Serdes Lane 3 Pattern Matcher Control Register
0 = Disabled 1 = lfsr15 2 = lfsr7 3 = d[n] = d[n-10] 4 = d[n] =!d[n-10] 5:7 = Reserved Note: This field returns to its reset value on reset Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 411: Serdes Lane 0 Frequency And Phase Value Register
Bits below the useful resolution Note: Read operations on this register is pipelined. Two reads needed to get current value. The values are volatile and the value may change at any time Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 412: Serdes Lane 1 Frequency And Phase Value Register
Bits below the useful resolution Note: Read operations on this register is pipelined. Two reads needed to get current value. The values are volatile and the value may change at any time Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 413: Serdes Lane 2 Frequency And Phase Value Register
Bits below the useful resolution Note: Read operations on this register is pipelined. Two reads needed to get current value. The values are volatile and the value may change at any time Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 414: Serdes Lane 3 Frequency And Phase Value Register
Bits below the useful resolution Note: Read operations on this register is pipelined. Two reads needed to get current value. The values are volatile and the value may change at any time Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 415: I2C Registers
C Master Receive Data Register” 0x1D114 I2C_MST_TDATA “I C Master Transmit Data Register” 0x1D118 I2C_ACC_STAT “I C Access Status Register” 0x1D11C I2C_INT_STAT “I C Interrupt Status Register” 0x1D120 I2C_INT_ENABLE “I C Interrupt Enable Register” Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 416 EXI2C_MBOX_IN “Externally Visible I C Incoming Mailbox Register” 0x1D298– 0x98–0xFF Reserved 0x1D2FC 0x1D300 I2C_EVENT “I C Event and Event Snapshot Registers” 0x1D304 I2C_SNAP_EVENT “I C Event and Event Snapshot Registers” Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 417 “I C Boot and Diagnostic Timer” 0x1D360– Reserved 0x1D3B4 0x1D3B8 I2C_BOOT_DIAG_PROGRESS “I C Boot Load Diagnostic Progress Register” 0x1D3BC I2C_BOOT_DIAG_CFG “I C Boot Load Diagnostic Configuration Register” 0x1D3C0– Reserved 0x1D3FC Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 418: Register Descriptions
This section describes the I C registers. These registers are reset by a chip reset. 13.2.1 C Device ID Register This register identifies the version of the IDT I C block in this device. Register name: I2C_DEVID Register offset: 0x1D100...
Page 419: I 2 C Reset Register
The boot load sequence will not be invoked upon exit from reset, although the bus idle detect sequence will be invoked. Power-up latch values will not be re-latched, and the fields will remain at their pre-soft-reset value. 01:31 Reserved Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 420: C Master Configuration Register
0x000 25:31 DEV_ADDR Device Address Undefined Specifies the 7-bit device address to select the I C device for a read or write transaction initiated through the “I Master Control Register”. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 421 13. I2C Registers > Register Descriptions Do not change this register while a master operation is active. The effect on the transaction cannot be determined. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 422: C Master Control Register
Register”. Note: Software must not set the peripheral address and the SIZE parameters such that unintended page wrap-arounds occur in the target device. The Tsi578 does not force repeated start conditions within a single software initiated access. Register name: I2C_MST_CNTRL...
Page 423 “I C Master Configuration Register”. Do not change this register while a master operation is active. The effect on the transaction cannot be determined. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 424: Table 50: Master Operation Sequence
Respond with ACK to each, except for final byte respond with a NACK. 7. Complete Issue STOP. Except for arbitration loss, master always tries to force a STOP condition. Clear I2C_MST_CNTRL[START]. Set MSD event. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 425: C Master Receive Data Register
Received I C data — Byte 2 0x00 16:23 RBYTE1 Received I C data — Byte 1 0x00 24:31 RBYTE0 Received I C data — Byte 0 (least significant) 0x00 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 426: C Master Transmit Data Register
TBYTE0 Transmitted I C data — Byte 0 (least significant) 0x00 Do not change this register while a master operation is active. The effect on the transaction cannot be determined. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 427: C Access Status Register
Note: This bit is zeroed on a reset controlled by the “I Reset Register”, and is not set to 1 until a START condition is seen after reset is de-asserted in the “I C Reset Register”. 02:03 Reserved Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 428 SLV_PA Slave Peripheral Address 0x00 This field indicates the current peripheral address that is used when the Tsi578 is accessed by an external master. MST_ACTIVE Master Active 0 = No master operation in progress 1 = Master operation is in progress This status is the same as the START bit in the “I...
Page 429 SIZE field from the “I C Master Control Register”. If an operation aborts prematurely, this field will indicate the number of bytes transferred before the error occurred. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 430: C Interrupt Status Register
“Externally Visible I C Incoming Mailbox Register”. 8:13 Reserved Reserved 0x00 BL_FAIL Boot Load Failed R/W1C 0 = Interrupt status not asserted 1 = Boot load sequence failed to complete Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 431 SA_OK Slave Access OK R/W1C 0 = Interrupt status not asserted 1 = Access completed successfully The Tsi578 was addressed as a slave device and the transaction completed without error. MA_DIAG Master Diagnostic Event R/W1C 0 = Interrupt status not asserted...
Page 432 1 = Access completed and successful A transaction initiated through the “I C Master Control Register” completed without error. The write-1-to-clear (W1C) operation requires that this register first be read to create an event snapshot. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 433: C Interrupt Enable Register
Enable BL_OK Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled 16:19 Reserved Reserved SA_FAIL Enable SA_FAIL Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 434 1 = Interrupt is enabled MA_ATMO Enable MA_ATMO Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled MA_OK Enable MA_OK Interrupt 0 = Interrupt is disabled 1 = Interrupt is enabled Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 435: C Interrupt Set Register
Set BL_OK Interrupt R/W1S 0 = No effect 1 = Interrupt is set 16:19 Reserved Reserved SA_FAIL Set SA_FAIL Interrupt R/W1S 0 = No effect 1 = Interrupt is set Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 436 1 = Interrupt is set MA_ATMO Set MA_ATMO Interrupt R/W1S 0 = No effect 1 = Interrupt is set MA_OK Set MA_OK Interrupt R/W1S 0 = No effect 1 = Interrupt is set Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 437: C Slave Configuration Register
RD_EN Register Bus Read Enable This bit controls whether external masters can read registers internal to the Tsi578. The SLV_EN bit must also be set for this option to have any effect. 0 = Transactions that read the “Externally Visible I C Internal Read Data Register”...
Page 438 Alert Response Address read, if ALRT_EN is 1. This bit controls access to the peripheral address space of the Tsi578. Access to the internal register space is also controlled by the RD_EN and WR_EN bits. If SLV_EN is 0 then internal register access is also disabled.
Page 439 The LSB two bits [30:31] of this field are latched at power-up from the state of input pins. This allows board configuration of up to four unique Tsi578 devices on the I2C bus. These two bits are then locked for writing until the SLV_UNLK bit is set to 1 during a write.
Page 440: C Boot Control Register
C Boot Control Register This register controls the boot load sequence that is initiated following a chip reset of the Tsi578. The initial boot load operation is controlled by the reset state of this register. Some of the fields are also latched from device pins at power-up.
Page 441 To change the bits, this BUNLK bit must be written as 1 on the write performed to this register that is changing the BOOT_ADDR[14:15] bits. 04:08 Reserved Reserved 0x00 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 442 BOOT_ADDR Boot Device Address Undefined This is the device address that the Tsi578 will access during the boot load sequence. The least significant two bits [14:15] of this field are latched at power-up from the state of the I2C_SA[1:0] pins. This allows board configuration of up to four unique Tsi578 devices on the I2C bus, each of which access a different EEPROM during boot load.
Page 443 0x09 and the second byte is 0x38. This field can be changed during the boot load, in conjunction with setting the CHAIN bit, in order to jump the boot load to a new peripheral address. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 444: Externally Visible I C Internal Write Address Register
Only the least significant 24 bits are significant to the Tsi578. Bits [00:07] can be written but will not have any effect. This address auto-increments by 4 if WINC in the “Externally...
Page 445: Externally Visible I C Internal Write Data Register
WINC in the “Externally Visible I Internal Access Control Register” is set to auto-increment the WADDR. When 0x07 is read, the peripheral address increments to 0x08. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 446: Externally Visible I C Internal Read Address Register
Only the least significant 24 bits are significant to the Tsi578. Bits [00:07] can be written, but will not have any effect. This address auto-increments by 4 if RINC in the “Externally...
Page 447: Externally Visible I C Internal Read Data Register
RINC in the “Externally Visible I Internal Access Control Register” is set to auto-increment the RADDR. When 0x17 is written, the peripheral address increments to 0x18. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 448: Externally Visible I C Slave Access Status Register
(through peripheral address 0x20), the bit is then cleared to 0. The bit is not cleared to 0 when read by a host or indirectly through the EXI2C_REG_RADDR / EXI2C_REG_RDATA function. 25:27 Reserved Reserved Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 449 Alert Response Address or if the global status no longer requires the alert to be asserted. On a hard reset, this flag will assert immediately due to EXI2C_STAT[RESET] asserting. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 450: Externally Visible I C Internal Access Control Register
Register”. The read is performed when the LSB of the data register is read (peripheral address 0x14). 11 = 8 bytes (Reserved) All Reserved settings will result in internal read accesses being disabled. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 451 0x07 back to 0x04. If auto-incrementing is off, then the same internal register can be written multiple times in a single I C transaction. 30:31 Reserved Reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 452: Externally Visible I C Status Register
Externally Visible I C Status Register This register provides a summary view of status of the Tsi578. It can be polled by an external system management device. Any bit masked by its related enable, changing from 0 to 1, will cause ALERT_FLAG to be set in the “Externally Visible I...
Page 453 1 = TEA asserted by one or more ports. TEA occurred in the switching fabric. Reset Control Symbol Status 0 = No status asserted 1 = Status asserted Combined Reset Control Symbol interrupt status from all ports. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 454 1 = Port 11 has asserted an interrupt to the processor PORT10 Port 10 Interrupt 0 = No interrupt 1 = Port 10 has asserted an interrupt to the processor Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 455 1 = Port 1 has asserted an interrupt to the processor PORT0 Port 0 Interrupt 0 = No interrupt 1 = Port 0 has asserted an interrupt to the processor Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 456: Externally Visible I C Enable Register
1 = Status asserted will enable setting ALERT_FLAG OMBW Enable Outgoing Mailbox Written 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 457 1 = Status asserted will enable setting ALERT_FLAG 10:12 Reserved Reserved These bits are unused in the Tsi578. The enables can be changed, but have no effect. LOGICAL Enable LOGICAL Alert Response 0 = Status asserted will not enable setting ALERT_FLAG...
Page 458 1 = Status asserted will enable setting ALERT_FLAG PORT2 Enable PORT2 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 459 1 = Status asserted will enable setting ALERT_FLAG PORT0 Enable PORT0 Alert Response 0 = Status asserted will not enable setting ALERT_FLAG 1 = Status asserted will enable setting ALERT_FLAG Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 460: Externally Visible I C Outgoing Mailbox Register
Note: A read is considered complete when the STOP condition is seen on the I C bus, and one or more bytes in this register were read by the external master since the preceding START condition. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 461: Externally Visible I C Incoming Mailbox Register
C Slave Access Status Register”, and asserts an IMB_FULL interrupt. When software reads this register, the IMB_FLAG is cleared. Note: This register is writable only through the I C slave interface. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 462: C Event And Event Snapshot Registers
Slave Transaction Done Event R/W1C 0 = Event not asserted 1 = Slave interface completed an I C transaction for an external master with no detectable error Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 463 SBTTO Slave Byte Timeout Event R/W1C 0 = Event not asserted 1 = Byte timer expired during a slave transaction initiated by an external master Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 464 0 = Event not asserted 1 = The boot load sequencer received a NACK 6 times when trying to address the slave device. No device is responding to the boot load device address. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 465 0 = Event not asserted 1 = Arbitration timeout timer expired during a transaction initiated through the “I C Master Control Register”. Another master has control of the I C bus. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 466: C New Event Register
DTIMER Diagnostic Timer Expired Event R/W1S 0 = Event not asserted 1 = Event asserted DHIST Diagnostic History Filling Event R/W1S 0 = Event not asserted 1 = Event asserted Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 467 BLTO Boot Load Timeout Event R/W1S 0 = Event not asserted 1 = Event asserted BLERR Boot Load Error Event R/W1S 0 = Event not asserted 1 = Event asserted Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 468 Master I2C_SCLK Low Timeout Event R/W1S 0 = Event not asserted 1 = Event asserted MARBTO Master Arbitration Timeout Event R/W1S 0 = Event not asserted 1 = Event asserted Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 469: C Enable Event Register
1 = Event will assert in the interrupt status DCMDD Diagnostic Command Done Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 470 1 = Event will assert in the interrupt status BLSZ Boot Load Size Error Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 471 1 = Event will assert in the interrupt status MARBTO Master Arbitration Timeout Enable 0 = Event does not assert to interrupt status 1 = Event will assert in the interrupt status Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 472: C Time Period Divider Register
This field divides the USDIV period down further for use by the Arbitration Timeout Timer, the Transaction Timeout Timer, and the Boot/Diag Timeout Timer. Period(MSDIV) = Period(USDIV) * (MSDIV + 1). Reset period is 1 millisecond. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 473: I 2 C Start Condition Setup/Hold Timing Register
I2C_SD seen low to I2C_SCLK pulled low. This is a master only timing parameter. Period(START_HOLD) = (START_HOLD * Period(PCLK)), where PCLK is 10 ns. Reset time is 4.01 microseconds. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 474: C Stop/Idle Timing Register
“I C Time Period Divider Register”. A value of zero results in no idle detect period, meaning the bus will be sensed as idle immediately. Reset time is 51 microseconds. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 475: I2C_Sd Setup And Hold Timing Register
I2C_SD valid past the falling edge of I2C_SCLK. This applies to both slave and master interface. Period(SDA_HOLD) = (SDA_HOLD * Period(P_CLK)), where P_CLK is 10 ns. Reset time is 310 nanoseconds. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 476: I2C_Sclk High And Low Timing Register
The observed period may be longer if other devices pull the clock low. Period(SCL_LOW) = (SCL_LOW * Period(P_CLK)), where P_CLK is 10 ns. Reset time is 5.00 microseconds (100 kHz). Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 477: I2C_Sclk Minimum High And Low Timing Register
The observed period may be longer if other devices pull the clock low. Period(SCL_MINL) = (SCL_MINL * Period(P_CLK)), where P_CLK is 10 ns. Reset time is 4.71 microseconds. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 478: I2C_Sclk Low And Arbitration Timeout Register
MSDIV is the millisecond time defined in “I C Time Period Divider Register”. The reset value of this timeout is 51 milliseconds. However, this timeout is not active during the boot load sequence. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 479: I 2 C Byte/Transaction Timeout Register
Period(TRAN_TO) = (TRAN_TO * Period(MSDIV)) where MSDIV is the millisecond time defined in “I C Time Period Divider Register”. This timeout is disabled on reset, and is not used during boot load. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 480: I 2 C Boot And Diagnostic Timer
The reset value for the boot load timeout is 4 seconds. If the boot load completes before the timer expires, the timer is set to zero (disabled). Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 481: I 2 C Boot Load Diagnostic Progress Register
(with the 3 LSBs set to zero). This is a diagnostic register. Documentation is provided for reference purposes only. The function of this register is not guaranteed in future versions and usage thereof is not supported. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 482: C Boot Load Diagnostic Configuration Register
This is a diagnostic register. Documentation is provided for reference purposes only. The function of this register is not guaranteed in future versions and usage thereof is not supported. Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 483: Serial Rapidio Protocol Overview
The sum of all of the bit fields adds 20 bytes to the encapsulated data packet size. The maximum data field size is 256 bytes resulting in a maximum packet size of 276 bytes. Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 484: Control Symbols
Detailed explanation of the encoding values and names can be found in Chapter 4, “PCS and PMA Layers” of “Part VI Physical Layer 1x/4x LP-Serial RapidIO Specification”. Tsi578 User Manual Integrated Device Technology June 6, 2016...
Page 485: Table 51: Special Characters And Encoding
0xFB or //A// //K// 4x Idle /K28.5/K28.5/K2 0xBC on each 8.5/K28.5/ lane //R// 4x Sync /K29.7/K29.7/K2 0xFD on each 9.7/K29.7/ lane //A// 4x Skip /K27.7/K27.7/K2 0xFB on each 7.7/K27.7/ lane Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 486: Table 52: Control Symbol Construction
CRC 00011 non-maint pkt reception is stopped 00100 recvd pkt w/ bad 00101 recvd invalid char or valid but illegal char 000110-11 reserved 11111 general error Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 487 000-010 reserved reset device input status 101-111 reserved multicast reserved event reserved reserved reserved Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 488 A. Serial RapidIO Protocol Overview > Physical Layer Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 489: Clocking
“P_CLK Programming” on page 493 Line Rate Support The Tsi578 supports all of the RapidIO Interconnect Specification (Revision 1.3) specified line rates of 1.25, 2.50, and 3.125 Gbaud. The device also supports line rates that are outside of the RapidIO specification.
Page 490: Register Requirements Using 125 Mhz S_Clk For A 3.125 Gbps Link Rate
This information assumes a +/- 100 ppm clock tolerance that must be obeyed between link partners. All bit and register settings that are documented for operation with S_CLK = 156.25 .MHz also apply to the use of 153.6 MHz and 125 MHz. For more clocking information, see “Clocks” in the Tsi578 User Manual.
Page 491 The example EEPROM loading script in the “EEPROM Scripts” appendix of the Tsi578 User Manual configures ports six and eight of the Tsi578. Other ports can be added to the script and configured by editing the text. The script is written assuming that no other contents are required in the EEPROM.
Page 492 14. Set the RX_EN bit in the SMACx_CFG_CH0-3 register — Write offset 0x132B0 with 0x203CE513 — Write offset 0x132B4 with 0x203CE513 — Write offset 0x132B8 with 0x203CE513 — Write offset 0x132BC with 0x203CE513 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 493: P_Clk Programming
RapidIO Specifications Directly Affected by Changes in the P_CLK Frequency The following sections describe how changing the P_CLK frequency to below the recommended 100 MHz operation affect the counters and state machines in the Tsi578 that are defined in the RapidIO Interconnect Specification (Revision 1.3). B.2.1.1 Port Link Time-out CSR RapidIO Part 6: 1x/4x LP-Serial Physical Layer Specification Revision 1.3: Section...
Page 494: Table 54: Timer Values With P_Clk And Tval Variations
SILENCE_TIMER_EN to be de-asserted. When the state machine is not in the SILENT state, SILENCE_TIMER_DONE is de-asserted IDT Implementation The Tsi578’s silence timer does not have user programmable registers. The silence timer is sourced from the P_CLK and any changes to P_CLK are directly reflected in the timer timeout period. Tsi578 User Manual...
Page 495: Table 55: Timer Values With Discovery_Timer And P_Clk Variations
DISCOVERY state, DISCOVERY_TIMER_DONE is de-asserted. IDT Implementation The Tsi578’s discovery timer is programmed in the RapidIO Port x Discovery Timer. The DISCOVERY_TIMER field is used by serial ports configured to operate in 4x mode. The DISCOVERY_TIMER allows time for the link partner to enter its discovery state, and if the link partner supports 4x mode, for all four lanes to be aligned.
Page 496: Idt Specific Timers
When enabled, this timer is used to determine when a link is powered up and enabled, but dead (that is, there is no link partner responding). When a link is declared dead, the transmitting port on the Tsi578 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue.
Page 497: I 2 C Interface And Timers
• P_CLK is 10 ns • Tsi578 reset value is 0x0063 MSDIV Period Divider for Milli-Second Based Timers The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer, the Transaction Timeout Timer, and the Boot/Diagnostic Timeout Timer.
Page 498: I 2 C Stop/Idle Timing Register
Period (START_SETUP) = (START_SETUP * Period(PCLK)) — PCLK is 10ns — Reset time is 4.71 microseconds. — Tsi578 reset value is 0x01D7 START_HOLD Count for the START Condition Hold Period The START_HOLD field defines the minimum hold time for the START condition; that is, from I2C_SD seen low to I2C_SCLK pulled low.
Page 499 A value of zero results in no idle detect period, meaning the bus will be sensed as idle immediately. — Reset time is 51 microseconds — Tsi578 reset value is 0x0033 B.2.3.4 I2C_SD Setup and Hold Timing Register The I2C_SD Setup and Hold Timing Register programs the setup and hold times for the I2C_SD signal when output by either the master or slave interface.
Page 500 — P_CLK is 10 ns — Reset time is 5.00 microseconds (100 kHz) — Tsi578 reset value is 0x01F4 SCL_LOW Count for I2C_SCLK Low Period The SCL_LOW field defines the nominal low period of the clock, from falling edge to rising edge of I2C_SCLK.
Page 501 Period(SCL_MINL) = (SCL_MINL * Period(P_CLK)) — P_CLK is 10 ns — Reset time is 4.71 microseconds — Tsi578 reset value is 0x01D7 B.2.3.7 I2C_SCLK Low and Arbitration Timeout Register The I2C_SCLK Low and Arbitration Timeout Register programs the I2C_SCLK low timeout and the Arbitration timeout.
Page 502 — USDIV is the microsecond time defined in I2C Time Period Divider Register. — This timeout is disabled on reset, and is not used during boot load. — Tsi578 reset value is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus. This covers the period from Start to Stop.
Page 503: Other Performance Factors
— Tsi578 reset value is 0x0FA0 B.2.4 Other Performance Factors This section describes any other factors that may impact the performance of the Tsi578 if P-CLK is programmed to operate lower than the recommended 100 MHz frequency. B.2.4.1 Internal Register Bus Operation The internal register bus, where all the internal registers reside, is a synchronous bus clocked by the P_CLK source.
Page 504 B. Clocking > P_CLK Programming Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 505: Prbs Scripts
//Port 2 w 1e220 00000002 //Start 2^7 Pattern Generator w 1e260 00000002 w 1e2a0 00000002 w 1e2e0 00000002 //Port 4 w 1e420 00000002 //Start 2^7 Pattern Generator w 1e460 00000002 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 506 1ec20 00000002 //Start 2^7 Pattern Generator w 1ec60 00000002 w 1eca0 00000002 w 1ece0 00000002 //Port e w 1ee20 00000002 //Start 2^7 Pattern Generator w 1ee60 00000002 w 1eea0 00000002 w 1eee0 00000002 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 507: Tsi578_Framer_Disable.txt Script
134b8 A03CE511 w 134bc A03CE511 //Port 6 w 136b0 A03CE511 //Clear RX_ALIGN_EN w 136b4 A03CE511 w 136b8 A03CE511 w 136bc A03CE511 //Port 8 w 138b0 A03CE511 //Clear RX_ALIGN_EN w 138b4 A03CE511 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 508: Tsi578_Sync_Prbs_All.txt Script
//Port 0 w 1e030 0000000a //turn on Sync pattern matcher w 1e070 0000000a w 1e0b0 0000000a w 1e0f0 0000000a w 1e030 00000002 //turn off sync pattern matcher w 1e070 00000002 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 509 1e4f0 00000002 //Port 6 w 1e630 0000000a //Sync pattern matcher w 1e670 0000000a w 1e6b0 0000000a w 1e6f0 0000000a w 1e630 00000002 w 1e670 00000002 w 1e6b0 00000002 w 1e6f0 00000002 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 510 1ec30 0000000a //Sync pattern matcher w 1ec70 0000000a w 1ecb0 0000000a w 1ecf0 0000000a w 1ec30 00000002 w 1ec70 00000002 w 1ecb0 00000002 w 1ecf0 00000002 //Port e w 1ee30 0000000a //Sync pattern matcher Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 511: Tsi578_Read_Prbs_All.txt Script
1e030 r 1e070 r 1e070 r 1e0b0 r 1e0b0 r 1e0f0 r 1e0f0 //Port2 r 1e230 r 1e230 r 1e270 r 1e270 r 1e2b0 r 1e2b0 r 1e2f0 r 1e2f0 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 512 1e670 r 1e6b0 r 1e6b0 r 1e6f0 r 1e6f0 //Port8 r 1e830 r 1e830 r 1e870 r 1e870 r 1e8b0 r 1e8b0 r 1e8f0 r 1e8f0 //Porta r 1ea30 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 513 1ec30 r 1ec70 r 1ec70 r 1ecb0 r 1ecb0 r 1ecf0 r 1ecf0 //Porte r 1ee30 r 1ee30 r 1ee70 r 1ee70 r 1eeb0 r 1eeb0 r 1eef0 r 1eef0 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 514 C. PRBS Scripts > Tsi578_read_prbs_all.txt Script Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 515: Eeprom Scripts
18 138B0 ew 1c 203CA513 ew 20 138B4 ew 24 203CA513 ew 28 138B8 ew 2c 203CA513 ew 30 138BC ew 34 203CA513 ew 38 138B0 ew 3c 203C2513 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 516 68 138B8 ew 6c 200C2513 ew 70 138BC ew 74 200C2513 /F -- ew 78 138c0 ew 7c CA060004 ew 80 138c0 ew 84 CA060044 ew 88 138C4 ew 8c 002C0545 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 517 138B0 ew bc 203C2513 ew c0 138B4 ew c4 203C2513 ew c8 138B8 ew cc 203C2513 ew d0 138BC ew d4 203C2513 ew d8 138B0 ew dc 203CA513 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 518 110 138BC ew 114 203CE513 ew 118 138c8 ew 11c 7FFF0002 /24 start of port 6 initialization ew 120 136c8 ew 124 7FFF0012 ew 128 136c0 ew 12c CA060084 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 519 158 136B4 ew 15c 203C2513 ew 160 136B8 ew 164 203C2513 ew 168 136BC ew 16c 203C2513 ew 170 136B0 ew 174 200C2513 ew 178 136B4 ew 17c 200C2513 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 520 1a8 136c0 ew 1ac CA060045 ew 1b0 136c0 ew 1b4 CA060005 ew 1b8 136c0 ew 1bc 4A060005 ew 1c0 136c0 ew 1c4 CA060005 ew 1c8 136c0 ew 1cc CA060085 Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 521 1f8 136B4 ew 1fc 203CA513 ew 200 136B8 ew 204 203CA513 ew 208 136BC ew 20c 203CA513 ew 210 136B0 ew 214 203CE513 ew 218 136B4 ew 21c 203CE513 Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 522 D. EEPROM Scripts > Script ew 220 136B8 ew 224 203CE513 ew 228 136BC ew 22c 203CE513 ew 230 136c8 ew 234 7FFF0002 ew 238 8 ew 23c deadbeef Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 523: Index
Electrical Layer Line Rate Support Lane Synchronization and Alignment Logical Line Loopback Programmable Driver Current and Equalization Loopback Error Management Digital Equipment Loopback Error Management of Multicast Packets Logical Line Loopback Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 524 Conventions Removing a Destination ID to Multicast Mask Asso- Overview ciation Reset Removing a Port from a Multicast Mask Device Reset Configuring Multicast Masks Using the IDT Specific HARD_RST_b Reset Registers I2C Boot Multicast Operation RapidIO Reset Requests Multicast Terminology...
Page 525 Signals Supported Line Rates System Behaviour Input Queuing Model Output Arbitration Output Queuing Model Transfer Modes Throughput Traffic Efficiency Utility Unit Registers Write Access to Registers from the JTAG Interface Integrated Device Technology Tsi578 User Manual www.idt.com June 6, 2016...
Page 526 Index Tsi578 User Manual Integrated Device Technology June 6, 2016 www.idt.com...
Page 527 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 srio@idt.com San Jose, CA 95138 www.idt.com June 6, 2016...

IDT Tsi578 User Manual

About this Document

1 Functional Overview

2 Serial Rapidio Interface

3 Serial Rapidio Electrical Interface

4 Internal Switching Fabric

5 Multicast

6 Event Notification

7 I C Interface

8 Performance

9 JTAG Interface

10 Clocks, Resets and Power-Up Options

Quick Links

User Manual

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Summary of Contents for IDT Tsi578