Physical Layer Control And Status Registers - IDT 89HPES64H16G2 User Manual

IDT PCI to PCI Bridge and Proprietary Port Specific Registers

Physical Layer Control and Status Registers

SERDESCFG - SerDes Configuration (0x510)
Bit
Field
7:0 RCVD_OVRD
15:8
16
31:17
LANESTS0 - Lane Status 0 (0x51C)
Bit
Field
7:0
15:8
23:16
31:24
PES64H16G2 User Manual
Field Default
Type
Name Value
RW 0x0
SWSticky
Reserved RO 0x0
LSE RW 0x0
SWSticky
Reserved RO 0x0
Field Default
Type
Name Value
PDE RW1C 0x0
Reserved RO 0x0
E8B10B RW1C 0x0
Reserved RO 0x0
Description
Receiver Detect Override. Each bit in this register corresponds to
a SerDes lane. Setting this bit causes the lane associated with this
bit to indicate that a receiver has been detected on the line.
For even numbered ports, the upper 4 bits are only valid when a
port operates in merged mode.
For odd numbered ports, the upper 4 bits are never valid (i.e.,
undefined).
This field is not valid when the port operates in SerDes Test Mode.
Reserved field.
Low-Swing Mode Enable. When set, this bit enables Low-Swing
mode operation at the SerDes Transmit logic. Please refer to sec-
tion Low-Swing Transmitter Voltage Mode on page 8-13 for further
details.
0x0 - Full-Swing Mode
0x1 - Low-Swing Mode
Reserved field.
Description
Phy Disparity Error. Each bit in this field corresponds to a SerDes
lane associated with the port. A bit is set when an 8B10B coding
violation has resulted in a running disparity error in the received
data stream.
For even numbered ports, the upper 4 bits are only valid when a
port operates in merged mode.
For odd numbered ports, the upper 4 bits are never valid (i.e.,
undefined).
A bit can only be set when the LTSSM is in the L0 state.
Reserved field.
8B10B Error. Each bit in this field corresponds to a SerDes lane
associated with the port. A bit is set when an 8B10B decode error
is detected in the received data stream.
For even numbered ports, the upper 4 bits are only valid when a
port operates in merged mode.
For odd numbered ports, the upper 4 bits are never valid (i.e.,
undefined).
A bit can only be set when the LTSSM is in the L0, Configuration,
Disabled, or Hot-Reset states.
Reserved field.
16 - 67 April 5, 2013