IDT 89HPES32NT8xG2 Manuals

Manuals and User Guides for IDT 89HPES32NT8xG2. We have 1 IDT 89HPES32NT8xG2 manual available for free PDF download: User Manual

IDT 89HPES32NT8xG2 User Manual

IDT 89HPES32NT8xG2 User Manual (722 pages)

PCI Express switch

Brand: IDT | Category: Switch | Size: 4.09 MB

Table of Contents

User Manual
1
About this Manual

3
- Content Summary
  3
- Signal Nomenclature
  4
- Numeric Representations
  5
- Data Units
  5
- Register Terminology
  6
- Use of Hypertext
  7
- Reference Documents
  7
- Revision History
  7
- Table of Contents
  13
Pes32Nt8Xg2 Device Overview

39
Clocking

59
Reset and Initialization

67
Switch Core

81
Switch Partition and Port Configuration

103
Failover

127
- Overview
  127
- Failover Initiation
  127
Link Operation

131
- Overview
  131
- Port Merging
  131
- Port Maximum Link Width
  132
- Polarity Inversion
  132
- Lane Reversal
  132
- Figure 7.1 Lane Reversal for Highest Achievable Link Width of X2
  132
- Figure 7.2 Lane Reversal for Highest Achievable Link Width of X4
  133
- Link Width Negotiation
  134
  - Figure 7.3 Lane Reversal for Highest Achievable Link Width of X8
    134
  - Link Width Negotiation in the Presence of Bad Lanes
    135
- Dynamic Link Width Reconfiguration
  135
  - Dynamic Link Width Reconfiguration in the Pes32Nt8Xg2
    136
- Link Speed Negotiation
  136
  - Link Speed Negotiation in the Pes32Nt8Xg2
    137
  - Software Management of Link Speed
    138
- Link Retraining
  139
- Link States
  139
- Link down Handling
  140
- Figure 7.4 Pes32Nt8Xg2 ASPM Link State Transitions
  140
- Slot Power Limit Support
  141
  - Upstream Port
    141
  - Downstream Switch Port
    142
- Link Active State Power Management (ASPM)
  142
  - L0S ASPM
    142
  - L1 Aspm
    143
- Link Status
  146
- De-Emphasis Negotiation
  146
- Crosslink
  147
- Gen 1 Compatibility Mode
  148
- Table 7.2 Gen 1 Compatibility Mode: Bits Cleared in Training Sets
  148
Serdes

151
Power Management

167
Transparent Switch Operation

173
Hot-Plug and Hot-Swap

199
Smbus Interfaces

207
General Purpose I/O

243
- Overview
  243
- GPIO Configuration
  243
  - Input
    243
  - Output
    243
  - Alternate Function
    243
  - Table 13.1 GPIO Pin Configuration
    243
  - Table 13.2 GPIO Alternate Function Pin Assignment
    244
  - Table 13.3 GPIO Alternate Function Pins
    244
Non-Transparent Switch Operation

245
DMA Controller

285
Switch Events

321
- Overview
  321
  - Link up
    322
  - Figure 16.1 Switch Event Detection and Signaling Mechanism
    322
  - Link down
    323
  - Fundamental Reset
    323
  - Hot Reset
    323
  - Failover
    323
  - Global Signals
    324
  - Figure 16.2 Global Signaling Mechanism
    324
  - Port AER Errors
    325
Multicast

327
- Transparent Multicast Operation
  327
- Non-Transparent Multicast Operation
  332
  - NT Multicast Configuration
    333
  - Figure 17.3 Transparent and Non-Transparent Multicast
    333
  - NT Multicast TLP Determination
    334
  - NT Multicast TLP Routing
    334
  - NT Multicast Egress Processing
    335
  - Usage Restrictions
    337
Temperature Sensor

339
- Overview
  339
Register Organization

341
- Overview
  341
- Address Maps
  343
PCI-To-PCI Bridge Registers

379
Proprietary Port Specific Registers

443
- Port Control Register
  443
- Upstream PCI-To-PCI Bridge Interrupt and Signaling
  443
- Port AER Mask Register
  445
- Port Slot Control
  447
- Internal Error Control and Status Registers
  449
- Physical Layer Control and Status Registers
  465
- Request Metering
  470
- WRR Port Arbitration Counts
  471
- Non-Transparent Multicast Overlay
  474
- AER Error Emulation
  476
- Global Address Space Access Registers
  479
NT Endpoint Registers

481
- Type 0 Configuration Header Registers
  481
- PCI Express Capability Structure
  493
- PCI Power Management Capability Structure
  507
- Message Signaled Interrupt Capability Structure
  508
- Subsystem ID and Subsystem Vendor ID
  510
- Extended Configuration Space Access Registers
  510
- Advanced Error Reporting (AER) Extended Capability
  512
- Device Serial Number Extended Capability
  522
- PCI Express Virtual Channel Capability
  523
- ACS Extended Capability
  527
- Multicast Extended Capability
  529
- NT Registers
  532
  - NT Control & Status
    532
  - NT Interrupt and Signaling
    533
  - Internal Error Reporting Masks
    535
  - Doorbell Registers
    541
  - Message Registers
    542
  - BAR Configuration
    544
  - Mapping Table
    562
- Lookup Table
  565
- AER Error Emulation
  566
- Punch-Through Configuration Registers
  569
- NT Multicast
  571
- Global Address Space Access Registers
  572
DMA Function Registers

573
- Type 0 Configuration Header Registers
  573
- PCI Express Capability Structure
  581
- PCI Power Management Capability Structure
  593
- Message Signaled Interrupt Capability Structure
  595
- Extended Configuration Space Access Registers
  596
- Advanced Error Reporting (AER) Extended Capability
  598
- ACS Extended Capability
  608
- DMA Registers
  610
  - BAR Configuration
    610
  - DMA AER Error Emulation
    611
  - Internal Error Reporting Masks
    613
  - DMA Multicast Control
    619
  - DMA Channel Registers
    620
- Global Address Space Access Registers
  629
Switch Configuration and Status Registers

631
- Switch Control and Status Registers
  631
- Internal Switch Timers
  635
- Switch Partition and Port Registers
  637
- Failover Capability Registers
  643
- Protection
  645
- Switch Event Registers
  646
- Global Doorbells and Message Registers
  653
- Serdes Control and Status Registers
  654
- General Purpose I/O Registers
  661
- Hot-Plug and Smbus Interface Registers
  663
- Temperature Sensor Registers
  674
JTAG Boundary Scan

681
- Introduction
  681
- Test Access Point
  681
- Signal Definitions
  681
- Figure 25.1 Diagram of the JTAG Logic
  681
- Table 25.1 JTAG Pin Descriptions
  682
- Figure 25.2 State Diagram of the TAP Controller
  682
- Boundary Scan Chain
  683
- Table 25.2 Boundary Scan Chain
  683
- Test Data Register (DR)
  684
- Instruction Register (IR)
  686
  - Figure 25.5 Diagram of Bidirectional Cell
    686
  - Bypass
    687
  - Extest
    687
  - Sample/Preload
    687
  - Table 25.3 Instructions Supported by the JTAG Boundary Scan
    687
  - Clamp
    688
  - Extest_Train
    688
  - Figure 25.6 Device ID Register Format
    688
  - Idcode
    688
  - Table 25.4 System Controller Device Identification Register
    688
  - Validate
    688
  - Extest_Pulse
    689
  - Reserved
    689
  - Usage Considerations
    689
Usage Models

691

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