IDT 89HPES24T6G2 Manuals

IDT 89HPES24T6G2 Manuals

Manuals and User Guides for IDT 89HPES24T6G2. We have 1 IDT 89HPES24T6G2 manual available for free PDF download: User Manual

IDT 89HPES24T6G2 User Manual

IDT 89HPES24T6G2 User Manual (172 pages)

PCI Express Switch

Brand: IDT | Category: Switch | Size: 1.96 MB

Table of Contents

User Manual
1
About this Manual

3
- Content Summary
  3
- Signal Nomenclature
  3
- Numeric Representations
  4
- Data Units
  4
- Register Terminology
  5
- Use of Hypertext
  6
- Reference Documents
  6
- Revision History
  6
- Table of Contents
  9
PES24T6G2 Device Overview

21
- Introduction
  21
- Features
  21
- Logic Diagram - PES24T6G2
  24
- Vendor ID
  25
- Device ID
  25
- Revision ID
  25
- Jtag ID
  25
- Ssid/Ssvid
  25
- Pin Description
  26
- Table 1.3 PCI Express Interface Pins
  26
- Table 1.4 Smbus Interface Pins
  27
- Table 1.5 General Purpose I/O Pins
  27
- Table 1.6 System Pins
  28
- Table 1.7 Test Pins
  29
- Table 1.8 Power, Ground, and Serdes Resistor Pins
  30
- Pin Characteristics
  31
- Table 1.9 Pin Characteristics
  31
- Port Configuration
  32
- Figure 1.3 All Ports Unmerged Configuration
  33
- Figure 1.4 some Ports Merged Configuration
  34
- Figure 1.5 All Ports Merged Configuration
  34
Clocking, Reset and Initialization

35
Link Operation

43
- Polarity Inversion
  43
- Lane Reversal
  43
- Figure 3.1 Unmerged Port Lane Reversal
  43
- Introduction
  43
- Link Width Negotiation
  44
- Figure 3.2 Merged Port Lane Reversal
  44
- Dynamic Link Width Reconfiguration
  45
  - Dynamic Link Width Reconfiguration Support in the PES24T6G2
    45
- Link Speed Negotiation
  46
  - Link Speed Negotiation in the PES24T6G2
    46
  - Software Management of Link Speed
    47
- Link Reliability
  47
- Link Retraining
  49
- Link down
  50
- Slot Power Limit Support
  50
  - Upstream Port
    50
  - Downstream Port
    50
- Link States
  50
- Active State Power Management
  51
- Figure 3.3 PES24T6G2 ASPM Link Sate Transitions
  51
- Link Status
  52
- De-Emphasis Negotiation
  52
- Low-Swing Transmitter Voltage Mode
  52
- Crosslink
  52
General Purpose I/O

55
- Introduction
  55
- GPIO Configuration
  55
Smbus Interfaces

57
Power Management

79
Hot-Plug and Hot-Swap

83
Configuration Registers

89
- Configuration Space Organization
  89
- Register Definitions
  98
JTAG Boundary Scan

163
- Introduction
  163
- Test Access Point
  163
- Signal Definitions
  163
- Figure 9.1 Diagram of the JTAG Logic
  163
- Table 9.1 JTAG Pin Descriptions
  164
- Figure 9.2 State Diagram of Pes24T6G2'S TAP Controller
  164
- Boundary Scan Chain
  165
- Table 9.2 Boundary Scan Chain
  165
- Test Data Register (DR)
  166
- Instruction Register (IR)
  168
  - Figure 9.5 Diagram of Bidirectional Cell
    168
  - Bypass
    169
  - Extest
    169
  - Sample/Preload
    169
  - Table 9.3 Instructions Supported by Pes24T6G2'S JTAG Boundary Scan
    169
  - Clamp
    170
  - Figure 9.6 Device ID Register Format
    170
  - Idcode
    170
  - Reserved
    170
  - Table 9.4 System Controller Device Identification Register
    170
  - Usage Considerations
    170
  - Validate
    170

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