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IDT 89HPES34H16 User Manual

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®
IDT
89HPES34H16
™
PCI Express® Switch

User Manual

October 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89HPES34H16

  • Page 1: User Manual

    ® 89HPES34H16 ™ PCI Express® Switch User Manual October 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Content Summary Chapter 1, “PES34H16 Device Overview,” provides a complete introduction to the performance capa- bilities of the 89HPES34H16. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

  • Page 4: Numeric Representations

    Notes To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included. Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition.

  • Page 5: Register Terminology

    Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCIe root configura- tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial- ization.

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Link Operation Introduction ............................. 4-1 Polarity Inversion ..........................4-1 Link Width Negotiation........................4-1 Lane Reversal..........................4-1 Link Retraining..........................4-4 Link Down ............................4-5 Slot Power Limit Support ........................ 4-5 Upstream Port ........................4-5 Downstream Port........................4-5 Link States ............................
  • Page 9 IDT Table of Contents Notes Power Management Capability Structure ................9-35 Message Signaled Interrupt Capability Structure ..............9-36 Subsystem ID and Subsystem Vendor ID ................9-38 Extended Configuration Space Access Registers ..............9-38 Advanced Error Reporting (AER) Enhanced Capability ............9-39 Device Serial Number Enhanced Capability.................
  • Page 10 IDT Table of Contents Notes PES34H16 User Manual October 30, 2008...

  • Page 11: List Of Tables

    List of Tables ® Table 1.1 PES34H16 Device IDs......................1-4 Notes Table 1.2 PES34H16 Revision ID......................1-4 Table 1.3 PCI Express Interface Pins....................1-5 Table 1.4 SMBus Interface Pins ......................1-7 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins........................1-10 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes PES34H16 User Manual October 30, 2008...
  • Page 13 List of Figures ® Notes Figure 1.1 PES34H16 Architectural Block Diagram ................1-2 Figure 1.2 PES34H16 Logic Diagram ....................1-3 Figure 1.3 All Ports Unmerged Configuration ...................1-15 Figure 1.4 Three Ports Merged Configuration ...................1-16 Figure 2.1 Upstream Port Failover Architecture ..................2-1 Figure 2.2 Upstream Failover Mode Data Configurations ..............2-2 Figure 3.1 Common Clock on Upstream and Downstream (option to enable or disable Spread...
  • Page 14 IDT List of Figures Notes Figure 10.1 Diagram of the JTAG Logic ....................10-1 Figure 10.2 State Diagram of PES34H16’s TAP Controller ..............10-2 Figure 10.3 Diagram of Observe-only Input Cell .................10-6 Figure 10.4 Diagram of Output Cell ....................10-6 Figure 10.5 Diagram of Output Enable Cell ..................10-7 Figure 10.6...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-39 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-44 AERCES - AER Correctable Error Status (0x110) ................. 9-43 AERCTL - AER Control (0x118) ......................9-44 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-45 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCIECAP - PCI Express Capability (0x040) ...................9-22 PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-23 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-33 PCIEDCTL - PCI Express Device Control (0x048)..................9-24 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-33 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-25...
  • Page 17 IDT Register List Notes SWTOCNT - Switch Time-Out Count (0x75C) ..................9-79 SWTORCTL - Switch Time-Out Reporting Control (0x758) ..............9-78 SWTOSTS - Switch Time-Out Status (0x754) ..................9-77 USPFCTL - Upstream Port Failover Control (0x474) ................9-75 USPFSTS - Upstream Port Failover Status (0x470) ................9-74 USPFTIMER - Upstream Port Failover Watchdog Timer (0x478)............9-75...
  • Page 18 IDT Register List Notes PES34H16 User Manual October 30, 2008...

  • Page 19: Pes34H16 Device Overview

    Introduction Notes The 89HPES34H16 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES34H16 is a 34-lane, 16-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/ networking.

  • Page 20: Figure 1.1 Pes34H16 Architectural Block Diagram

    IDT PES34H16 Device Overview – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards –...

  • Page 21: Logic Diagram

    IDT PES34H16 Device Overview Logic Diagram PEREFCLKP[3:0] Reference PEREFCLKN[3:0] Clock REFCLKM PE0RP[0] PE0TP[0] PCIe Switch PCIe Switch PE0RN[0] PE0TN[0] SerDes Input SerDes Output Port 0 Port 0 PE0RP[3] PE0TP[3] PE0RN[3] PE0TN[3] PE1RP[0] PE1TP[0] PCIe Switch PCIe Switch PE1RN[0] PE1TN[0] SerDes Input...

  • Page 22: System Identification

    IDT PES34H16 Device Overview System Identification Notes Vendor ID All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES34H16 device ID is shown in Table 1.1. PCIe Device...

  • Page 23: Pin Description

    IDT PES34H16 Device Overview Pin Description Notes The following tables lists the functions of the pins provided on the PES34H16. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
  • Page 24 IDT PES34H16 Device Overview Notes Signal Type Name/Description PE8RP[0] PCI Express Port 8 Serial Data Receive. Differential PCI Express receive PE8RN[0] pair for port 8. PE8TP[0] PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit PE8TN[0] pair for port 8.

  • Page 25: Table 1.4 Smbus Interface Pins

    IDT PES34H16 Device Overview Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the master SMBus.
  • Page 26 IDT PES34H16 Device Overview Notes Signal Type Name/Description GPIO[9] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[10] General Purpose I/O.
  • Page 27 IDT PES34H16 Device Overview Notes Signal Type Name/Description GPIO[19] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P14RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 14 GPIO[20] General Purpose I/O.
  • Page 28 IDT PES34H16 Device Overview Notes Signal Type Name/Description GPIO[29] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[30] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[31] General Purpose I/O.

  • Page 29: Table 1.7 Test Pins

    IDT PES34H16 Device Overview Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside the PES34H16 and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES34H16 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 30: Pin Characteristics

    IDT PES34H16 Device Overview Notes Signal Type Name/Description CORE Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator.
  • Page 31 IDT PES34H16 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor PCI Express Interface PE4TN[3:0] Serial Link (cont.) PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0] PE5TP[3:0] PE6RN[0] PE6RP[0] PE6TN[0] PE6TP[0] PE7RN[0] PE7RP[0] PE7TN[0] PE7TP[0] PE8RN[0] PE8RP[0] PE8TN[0] PE8TP[0] PE9RN[0] PE9RP[0]...
  • Page 32 IDT PES34H16 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor PCI Express Interface PE14RN[0] Serial Link (cont.) PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0] PE15TN[0] PE15TP[0] PEREF- LVPECL/ Diff. Clock Refer to CLKN[3:0] Input Table 9 in the...

  • Page 33: Port Configuration

    IDT PES34H16 Device Overview Port Configuration Notes The PES34H16 contains up to 6 x4 ports and ten x1 ports labeled 0 through 15. Port 0 is always the upstream port and ports 1 through 15 are always downstream ports. An even port n and its odd counterpart, port n+1, may be merged into a single x8 port (ports 0 through 3 only).

  • Page 34: Disabled Ports

    IDT PES34H16 Device Overview Notes Port 0 Dev. 0 PES34H16 PCI to PCI Bridge Virtual PCI Bus Dev. 4 Dev. 7 Dev. 2 Dev. 6 Dev. 8 Dev. 15 PCI to PCI PCI to PCI PCI to PCI PCI to PCI...

  • Page 35: Upstream Port Failover

    Chapter 2 Upstream Port Failover ® Introduction Notes The PES34H16 supports an upstream port failover mechanism that enables the construction of fault tolerant systems. Upstream port failover allows port 0 or port 2 to be selected as the upstream switch port. The failover feature is disabled by default.

  • Page 36: Failover

    IDT Upstream Port Failover Notes When the PES34H16 is configured to operate in an upstream port failover switch mode, port 2 is always disabled. If the upstream port is configured to operate in x8 merged mode, then both ports two and three are disabled.

  • Page 37: Static Upstream Port Failover

    IDT Upstream Port Failover Notes At a system level, a dynamic upstream port failover appears as a full link retrain of the upstream port, i.e., the Link State Sequence State Machine (LTSSM) transitions to the Detect state, and the data link layer transitions to a DL_Down state.
  • Page 38 IDT Upstream Port Failover Notes When a dynamic upstream port failover is initiated, the PES34H16 takes the following actions: – The LTSSM associated with the upstream port immediately transitions to the Detect state and the data link layer transitions to the DL_Down state. This causes data in the replay buffer associated with the upstream port and upstream port data queued in the switch core to be discarded.
  • Page 39 IDT Upstream Port Failover Notes When a watchdog timer failover is initiated, the new upstream port becomes the one that is not selected by the CUSP field in the USPFSTS register. For example, if the current upstream port is port 0, then the new upstream port following the failover is port 2.
  • Page 40 IDT Upstream Port Failover Notes PES34H16 User Manual 2 - 6 October 30, 2008...

  • Page 41: Clocking, Reset, And Initialization

    Chapter 3 Clocking, Reset, and Initialization ® Introduction Notes The PES34H16 has four differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. It is recommended that all reference clock input pairs be driven from a common clock source.

  • Page 42: Figure 3.2 Non-Common Clock On Upstream; Common Clock On Downstream

    IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES34H16 Port 0 Root Complex Port 15 CCLKUS CCLKDS REFCLK0 REFCLK1 REFCLK2 REFCLK3 Clock Generator Clock Generator Figure 3.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum...

  • Page 43: Table 3.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES34H16 Port 0 Root Complex Port 15 CCLKUS CCLKDS REFCLK0 REFCLK1 REFCLK2 REFCLK3 Clock Generator Clock Generator Clock Generator Figure 3.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 3.2 is sampled by the PES34H16...

  • Page 44: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes May Be Signal Description Overridden P23MERGEN Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a single x8 port. The SerDes lanes associated with port 3 become lanes 4 through 7 of port 2.

  • Page 45: Fundamental Reset

    IDT Clocking, Reset, and Initialization Clock Operation Fundamental Reset Notes A fundamental reset may be initiated by any of the following conditions: – A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input pin.

  • Page 46: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes The PCIe base specification indicates that normal operation should begin within 1.0 second after a fundamental reset of a device. The reset sequence above guarantees that normal operation will begin within this period as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master SMBus operating frequency of 100 KHz.

  • Page 47: Upstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes The initiation of a hot reset due to the data link layer of the upstream port transitioning to the DL_Down state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control (SWCTL) register.

  • Page 48: Downstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes When an upstream secondary bus reset occurs, the following sequence is executed. 1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set.

  • Page 49: Power Enable Controlled Reset Output

    IDT Clocking, Reset, and Initialization Clock Operation Power Enable Controlled Reset Output Notes In this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. The operation of this mode is illustrated in Figure 3.6. A downstream port’s slot power is...
  • Page 50 IDT Clocking, Reset, and Initialization Clock Operation Notes Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter time interval may implement this functionality external to the PES34H16.

  • Page 51: Link Operation

    Chapter 4 Link Operation Introduction Notes The PES34H16 contains six x4 ports which may be merged in pairs to form up to three x8 ports. The remaining 10 ports are x1. The default link width for ports zero through five is x4 and the SerDes lanes are statically assigned to a port.

  • Page 52: Figure 4.1 Unmerged Port Lane Reversal For Maximum Link Width Of X4 (Maxlnkwdth[5:0]=0X4)

    IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES34H16 PES34H16 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal...

  • Page 53: Figure 4.3 Merged Port Lane Reversal For Maximum Link Width Of X2 (Maxlnkwdth[5:0]=0X2)

    IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES34H16 PES34H16 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal...

  • Page 54: Link Retraining

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES34H16 PES34H16 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5]...

  • Page 55: Link Down

    IDT Link Operation Link Down Notes When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR).

  • Page 56: Active State Power Management

    IDT Link Operation Notes L2/L3 Ready Figure 4.6 PES34H16 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.

  • Page 57: General Purpose I/O

    Chapter 5 General Purpose I/O ® Introduction Notes The PES34H16 has 32 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 58: Gpio Configuration

    IDT General Purpose I/O Notes Alternate Alternate GPIO Function Alternate Function Description Function Pin Name Pin Type IOEXPINTN6 SMBus I/O expander interrupt 6 Input IOEXPINTN7 SMBus I/O expander interrupt 7 Input IOEXPINTN10 SMBus I/O expander interrupt 10 Input Table 5.1 General Purpose I/O Pin Alternate Function (Part 2 of 2) After reset, all GPIO pins default to the GPIO input function.

  • Page 59: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES34H16 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES34H16, allowing every register in the device to be read or written by an external SMBus master.

  • Page 60: Master Smbus Interface

    IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.

  • Page 61: Table 6.2 Pes34H16 Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Any serial EEPROM compatible with those listed in Table 6.2 may be used to store the PES34H16 initialization values. Some of these devices are larger than the total size of all of the PCI configuration spaces in the PES34H16 that may be initialized and thus may not be fully utilized.

  • Page 62: Figure 6.2 Sequential Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.2 Sequential Double Word Initialization Sequence Format...

  • Page 63: Figure 6.4 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes sum is placed in the checksum field. The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence.

  • Page 64: I/O Expanders

    IDT SMBus Interfaces Notes SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access. I/O Expanders The PES34H16 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus inter- face for hot-plug and port status signals.

  • Page 65: Figure 6.6 I/O Expander Default Output Signal Value

    IDT SMBus Interfaces Notes SMBus I/O Section Function Expander Lower Link activity (ports 0 through 7) Upper Link activity (ports 8 through 15) Lower Power good inputs (ports 0 through 7) Upper Power good inputs (ports 8 through 15) Figure 6.5 I/O Expander Function Allocation (Part 2 of 2)
  • Page 66 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES34H16 to I/O expanders zero through seven (i.e., the ones that contain hot-plug signals). – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 67 IDT SMBus Interfaces Notes Each I/O expander has an open drain interrupt output that is asserted when a pin configured as an input changes state from the value previously read. Each interrupt output from an I/O expander should be connected to the corresponding PES34H16 I/O expander interrupt input. Since the PES34H16 I/O expander interrupt inputs are GPIO alternate functions, the corresponding GPIOs should be initialized during configuration to operate in alternate function mode.

  • Page 68: Table 6.3 I/O Expander 0 Signals

    – I/O expander outputs are not modified when the device transitions from normal operation to a fundamental reset. In systems where I/O expander output values must be reset during a funda- mental reset, an I/O expander reset circuit may be used to reset the I/O expanders. Contact IDT for more information.

  • Page 69: Table 6.4 I/O Expander 1 Signals

    IDT SMBus Interfaces Notes I/O Expander 1 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P2APN Port 2 attention push button input 1 (I/O-0.1) P2PDN Port 2 presence detect input 2 (I/O-0.2) P2PFN Port 2 power fault input 3 (I/O-0.3)

  • Page 70: Table 6.6 I/O Expander 3 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 8 (I/O-1.0) P7APN Port 7 attention push button input 9 (I/O-1.1) P7PDN Port 7 presence detect input 10 (I/O-1.2) P7PFN Port 7 power fault input 11 (I/O-1.3) P7MRLN Port 7 manually-operated retention latch (MRL) input 12 (I/O-1.4)

  • Page 71: Table 6.7 I/O Expander 4 Signals

    IDT SMBus Interfaces Notes I/O Expander 4 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P9APN Port 9 attention push button input 1 (I/O-0.1) P9PDN Port 9 presence detect input 2 (I/O-0.2) P9PFN Port 9 power fault input 3 (I/O-0.3)

  • Page 72: Table 6.9 I/O Expander 6 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 8 (I/O-1.0) P12APN Port 12 attention push button input 9 (I/O-1.1) P12PDN Port 12 presence detect input 10 (I/O-1.2) P12PFN Port 12 power fault input 11 (I/O-1.3) P12MRLN Port 12 manually-operated retention latch (MRL) input 12 (I/O-1.4)

  • Page 73: Table 6.10 I/O Expander 7 Signals

    IDT SMBus Interfaces Notes I/O Expander 7 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P14APN Port 14 attention push button input 1 (I/O-0.1) P14PDN Port 14 presence detect input 2 (I/O-0.2) P14PFN Port 14 power fault input 3 (I/O-0.3)

  • Page 74: Table 6.12 I/O Expander 9 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 9 (I/O-1.1) P9LINKUPN Port 9 link up status output 10 (I/O-1.2) P10LINKUPN Port 10 link up status output 11 (I/O-1.3) P11LINKUPN Port 11 link up status output 12 (I/O-1.4) P12LINKUPN Port 12 link up status output 13 (I/O-1.5)

  • Page 75: Slave Smbus Interface

    IDT SMBus Interfaces Notes I/O Expander 10 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) Unused 1 (I/O-0.1) P1PWRGDN Port 1 power good input 2 (I/O-0.2) P2PWRGDN Port 2 power good input 3 (I/O-0.3) P3PWRGDN Port 3 power good input 4 (I/O-0.4)

  • Page 76: Smbus Transactions

    IDT SMBus Interfaces Notes Address Address Bit Value SSMBADDR[5] Table 6.14 Slave SMBus Address When a Static Address is Selected (Part 2 of 2) SMBus Transactions The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.

  • Page 77: Table 6.16 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Name Field Description FUNCTION This field encodes the type of SMBus operation. 0 - CSR register read or write operation 1 - Serial EEPROM read or write operation 2 through 7 - Reserved SIZE This field encodes the data size of the SMBus transaction.

  • Page 78: Table 6.17 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Positio Description Name DATALM Data Lower Middle. Bits [15:8] of data doubleword. DATAUM Data Upper Middle. Bits [23:16] of data doubleword. DATAUU Data Upper. Bits [31:24] of data doubleword. Table 6.16 CSR Register Read or Write Operation Byte Sequence (Part 2 of 2) The format of the CMD field is shown in Figure 6.8 and described in Table 6.17.

  • Page 79: Table 6.18 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Positio Name Description CCODE Command Code. Slave Command Code field described in Table 6.15. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses to not contain this field.

  • Page 80: Figure 6.10 Csr Register Read Using Smbus Block Write/Read Transactions With Pec Disabled

    IDT SMBus Interfaces Notes Name Type Description Field NAERR No Acknowledge Error. This bit is set if an unexpected NACK is observed during a master SMBus transaction when accessing the serial EEPROM. This bit has the same function as the NAERR bit in the SMBUSSTS register.

  • Page 81: Figure 6.11 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES34H16 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES34H16 Slave CCODE (PES34H16 not ready with data) SMBus Address START,END PES34H16 Slave CCODE PES34H16 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address...

  • Page 82: Figure 6.15 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES34H16 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES34H16 Slave CCODE ADDRU SMBus Address END, Byte PES34H16 Slave CCODE (PES34H16 not ready with data) SMBus Address START,Word PES34H16 Slave CCODE SMBus Address START,Word PES34H16 Slave...

  • Page 83: Power Management

    Chapter 7 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES34H16 is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 84: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 85: Power Budgeting Capability

    IDT Power Management Notes When the PES34H16 receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message on all active downstream ports. The PES34H16 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its down- stream ports.
  • Page 86 IDT Power Management Notes PES34H16 User Manual 7 - 4 October 30, 2008...

  • Page 87: Hot-Plug And Hot-Swap

    Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES34H16 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 88: Figure 8.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES34H16 Port x Port y PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES34H16 Master SMBus...

  • Page 89: Table 8.1 Downstream Port Hot-Plug Signals

    IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES34H16 in an application in which one or more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a downstream slot.

  • Page 90: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes The state of a port’s Power Fault (PxPFN) input is not latched by the PES34H16. For proper operation the system designer should ensure that once the PxPFN signal is asserted, it remains asserted until the power enable (PxPEP) signal is toggled.

  • Page 91: Figure 8.4 Pes34H16 Hot-Plug Event Signalling

    IDT Hot-Plug and Hot-Swap The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.

  • Page 92: Hot-Swap

    IDT Hot-Plug and Hot-Swap Hot-Swap Notes The PES34H16 is hot-swap capable and meets the following requirements – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.) – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

  • Page 93: Configuration Registers

    Chapter 9 Configuration Registers ® Configuration Space Organization Notes Each software visible registers in the PES34H16 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES34H16 that cannot be accessed by the root. Each software visible register in the PES34H16 has a system address.

  • Page 94: Figure 9.1 Port Configuration Space Organization

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting...

  • Page 95: Upstream Port (Port 0)

    IDT Configuration Registers Upstream Port (Port 0) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 96 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-20 0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-21 0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 9-21...
  • Page 97 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 9- 0x128 Dword P0_AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page 9- 0x180...
  • Page 98 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x300 Dword P0_PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page 9-58 0x304 Dword P0_PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300) on page 9-58 0x308...
  • Page 99 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x744 Dword P0_SWPESTS SWPESTS - Switch Parity Error Status (0x744) on page 9-76 0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page 9-77 0x74C Dword...

  • Page 100: Downstream Ports (Ports 1 Through 15)

    IDT Configuration Registers Downstream Ports (Ports 1 through 15) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 101 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-20 0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-21 0x03E Word Px_BCTL BCTL - Bridge Control Register (0x03E) on page 9-21...
  • Page 102 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F8 Word Px_ECFGADDR ECFGADDR - Extended Configuration Space Access Address (0x0F8) on page 9-38 0x0FC Word Px_ECFGDATA ECFGDATA - Extended Configuration Space Access Data (0x0FC) on page 9-39 0x100...

  • Page 103: Register Definitions

    VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-4. PES34H16 User Manual 9 - 11 October 30, 2008...
  • Page 104 Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. See section Device ID on page 1-4. PCICMD - PCI Command Register (0x004) Field Default Type Description Field...
  • Page 105 IDT Configuration Registers Notes Field Default Type Description Field Name Value SERRE SERR Enable. Non-fatal and fatal errors detected by the bridge are reported to the Root Complex when this bit is set or the bits in the PCI Express Device Control register are set (see PCIEDCTL - PCI Express Device Control (0x048)).
  • Page 106 IDT Configuration Registers Notes Field Default Type Description Field Name Value RTAS Received Target Abort. Not applicable. RMAS Received Master Abort. Not applicable. RW1C Signalled System Error. This bit is set when the bridge sends a ERR_FATAL or ERR_NONFATAL message and the SERR Enable (SERRE) bit is set in the PCICMD register.
  • Page 107 IDT Configuration Registers Notes PLTIMER - Primary Latency Timer (0x00D) Field Default Type Description Field Name Value PLTIMER 0x00 Primary Latency Timer. Not applicable. HDR - Header Type Register (0x00E) Field Default Type Description Field Name Value 0x01 Header Type. This value indicates a type 1 header with a sin- gle function bridge layout.
  • Page 108 IDT Configuration Registers Notes SBUSN - Secondary Bus Number Register (0x019) Field Default Type Description Field Name Value SBUSN Secondary Bus Number. This field is used to record the bus number of the PCI bus segment to which the secondary inter- face of the bridge is connected.
  • Page 109 IDT Configuration Registers Notes IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
  • Page 110 IDT Configuration Registers Notes MBASE - Memory Base Register (0x020) Field Default Type Description Field Name Value Reserved Reserved field. 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable trans- actions between the primary and secondary interfaces of the bridge.
  • Page 111 IDT Configuration Registers Notes PMLIMIT - Prefetchable Memory Limit Register (0x026) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. This bit always reflects the value in the PMCAP field in the PMBASE register.
  • Page 112 IDT Configuration Registers Notes IOLIMITU - I/O Limit Upper Register (0x032) Field Default Type Description Field Name Value 15:0 IOLIMITU Prefetchable IO Limit Upper. This field specifies the upper 16-bits of IOLIMIT. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 113 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot-plug by the downstream ports.

  • Page 114: Pci Express Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
  • Page 115 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. The default value corresponds to 2048 bytes.
  • Page 116 IDT Configuration Registers Notes Field Default Type Description Field Name Value 25:18 CSPLV Captured Slot Power Limit Value. This field in combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot. Power limit (in Watts) calcu- lated by multiplying the value in this field by the value in the Slot Power Limit Scale field.
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value ETFEN Extended Tag Field Enable. Since the bridge never gener- ates a transaction that requires a completion, this bit has no functional effect on the device during normal operation.
  • Page 118 IDT Configuration Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNK- Maximum Link Speed. This field indicates the supported link speeds of the port. 1 - (gen1) 2.5 Gbps 2 - (gen2) 5 Gbps...
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value Link Bandwidth Notification Capability. When set, this bit indicates support for the link bandwidth notification status and interrupt mechanisms. The PES34H16 downstream ports support the capability. This field is not applicable for the upstream port and must be zero.
  • Page 120 IDT Configuration Registers Notes Field Default Type Description Field Name Value LRET Link Retrain. Writing a one to this field initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. This field always returns zero when read.
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value SCLK HWINIT Slot Clock Configuration. When set, this bit indicates that the component uses the same physical reference clock that the platform provides. The initial value of this field is the state of the CCLKUS signal for the upstream port and the CCLKDS signal for downstream ports.
  • Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power sup- plied by the slot. A Set_Slot_Power_Limit message is generated using this field whenever this register is written or when the link transi- tions from a non DL_Up status to a DL_Up status.
  • Page 123 IDT Configuration Registers Notes PCIESCTL - PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. This bit when set enables generation of a Hot-Plug interrupt or wake-up event on an attention button pressed event.
  • Page 124 IDT Configuration Registers Notes Field Default Type Description Field Name Value Power Indicator Control. When read, this register returns the current state f the Power Indicator. Writing to this register sets the indicator and causes the port to send the appropriate POWER_INDICATOR_* message.
  • Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Command Completed. This bit is set when the Hot-Plug Controller completes an issued command. If the bit is already set, then it remains set. A single write to the PCI Express Slot Control (PCIESCTL) register is considered to be a single command even if it affects more than one field in that register.
  • Page 126 IDT Configuration Registers Notes PCIEDSTS2 - PCI Express Device Status 2 (0x06A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) Field Default Type Description Field Name Value 31:0 Reserved Reserved field.

  • Page 127: Power Management Capability Structure

    IDT Configuration Registers Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. Power Management Capability Structure PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name...

  • Page 128: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes PMCSR - PCI Power Management Control and Status (0x0C4) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state and to set a new power state.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 NXTPTR Next Pointer. This field contains a pointer to the next capa- bility structure. This field is set to 0x0 indicating that it is the last capability. Enable. This bit enables MSI.

  • Page 130: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) Field Default Type Description Field Name Value 15:0 MDATA Message Data. This field contains the lower 16-bits of data that are written when a MSI is signalled. 31:16 Reserved Reserved field.

  • Page 131: Advanced Error Reporting (Aer) Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value Register Number. This field selects the configuration register number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev. 1.0a 11:8 EREG Extended Register Number. This field selects the extended configuration register number as defined by Section 7.2.2 of...
  • Page 132 IDT Configuration Registers Notes AERUES - AER Uncorrectable Error Status (0x104) Field Default Type Description Field Name Value UDEF RW1C Undefined. This bit is no longer used in this version of the Sticky specificiation. Reserved Reserved field. DLPERR RW1C Data Link Protocol Error Status. This bit is set when a data Sticky link layer protocol error is detected.
  • Page 133 IDT Configuration Registers Notes AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specificiation. Reserved Reserved field. DLPERR Data Link Protocol Error Mask. When this bit is set, the cor- Sticky responding bit in the AERUES register is masked.
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Mask. When this bit is set, the corresponding bit in the Sticky AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 135 IDT Configuration Registers Notes Field Default Type Description Field Name Value UECOMP Unexpected Completion Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported error.
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value RPLYTO RW1C Replay Timer Time-Out Status. This bit is set when the Sticky replay timer in the data link layer times out. ADVISO- RW1C Advisory Non-Fatal Error Status. This bit is set when an...
  • Page 137 IDT Configuration Registers Notes AERCTL - AER Control (0x118) Field Default Type Description Field Name Value FEPTR First Error Pointer. This field contains a pointer to the bit in Sticky the AERUES register that resulted in the first reported error.

  • Page 138: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 4th doubleword of the Sticky TLP header that resulted in the first reported uncorrectable error.

  • Page 139: Pci Express Virtual Channel Capability

    IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capability structure. 19:16 CAPVER Capability Version.
  • Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:8 Reserved Reserved field. 31:24 VCATBL- VC Arbitration Table Offset. This field contains the offset of the VC arbitration table from the base address of the Virtual Channel Capability structure in double quad words (16 bytes).
  • Page 141 IDT Configuration Registers Notes VCR0CAP- VC Resource 0 Capability (0x210) Field Default Type Description Field Name Value PARBC Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Arbitration capability. When more than one arbitration scheme is supported, multiple bits may be set.
  • Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:17 PARBSEL Port Arbitration Select. This field configures the VC resource to provide a particular Port Arbitration service. The permissible values of this field is a number that corre- sponds to one of the asserted bits in t he Port Arbitration Capability field of the VC resource.
  • Page 143 IDT Configuration Registers Notes Field Default Type Description Field Name Value RJST Reject Snoop Transactions. No supported for switch ports. 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field.
  • Page 144 IDT Configuration Registers Notes VCR1STS - VC Resource 1 Status (0x224) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PATS Port Arbitration Table Status. This bit indicates the coher- ency status of the port arbitration table associated with the VC resource and is valid only when the port arbitration table is used by the selected arbitration algorithm.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:20 PHASE5 Phase 5. This field contains the port ID for the corresponding port arbitration period. 27:24 PHASE6 Phase 6. This field contains the port ID for the corresponding port arbitration period.
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:20 PHASE21 0x10 Phase 21. This field contains the port ID for the correspond- ing port arbitration period. 27:24 PHASE22 0x11 Phase 22. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 147 IDT Configuration Registers Notes VCR1TBL0 - VC Resource 1 Arbitration Table Entry 0 (0x240) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the corresponding port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.
  • Page 148 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:12 PHASE11 Phase 11. This field contains the port ID for the correspond- ing port arbitration period. 19:16 PHASE12 Phase 12. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 149: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:12 PHASE27 Phase 27. This field contains the port ID for the correspond- ing port arbitration period. 19:16 PHASE28 Phase 28. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 150 IDT Configuration Registers Notes PWRBD - Power Budgeting Data (0x288) Field Default Type Description Field Name Value 31:0 DATA Data. If the Data Value Select (DVSEL) field in the Power Budgeting Data Select register contains a value of zero through 31, then this field returns the contents of the corre- sponding Power Budgeting Data Value (PWRBDVx) register.

  • Page 151: Switch Control And Status Registers

    IDT Configuration Registers Switch Control and Status Registers Notes SWSTS - Switch Status (0x400) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. These configuration pins determine the PES34H16 switch operating mode. These pins should be static and not change following the negation of PERSTN.
  • Page 152 IDT Configuration Registers Notes Field Default Type Description Field Name Value P67MERGEN Port 6 and 7 Merge. This bit reflects the value of the P67MERGEN signal sampled during the fundamental reset. P89MERGEN Port 8 and 9 Merge. This bit reflects the value of the P89MERGEN signal sampled during the fundamental reset.
  • Page 153 IDT Configuration Registers Notes SWCTL - Switch Control (0x404) Field Default Type Description Field Name Value FRST Fundamental Reset. Writing a one to this bit initiates a fun- damental reset. Writing a zero has no effect. This field always returns a value of zero when read.
  • Page 154 IDT Configuration Registers Notes HPCFGCTL - Hot-Plug Configuration Control (0x408) Field Default Type Description Field Name Value IPXAPN Invert Polarity of PxAPN. When this bit is set, the polarity of Sticky the PxAPN input is inverted in all ports. IPXPDN Invert Polarity of PxPDN.
  • Page 155 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:14 RSTMODE Reset Mode. This field controls the manner in which down- Sticky stream port reset outputs are generated. 0x0 -(pec) Power enable controlled reset output 0x1 - (pgc) Power good controlled reset output...
  • Page 156 IDT Configuration Registers Notes GPIOD - General Purpose I/O Data (0x420) Field Default Type Description Field Name Value 31:0 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding Sticky GPIO pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate func-...
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value ICSERR RW1C Initialization Checksum Error. This bit is set if an invalid checksum is computed during Serial EEPROM initialization or when a configuration done command is not found in the serial EEPROM.
  • Page 158 IDT Configuration Registers Notes Field Default Type Description Field Name Value 21:20 MSMB- Master SMBus Mode. The master SMBus contains internal MODE Sticky glitch counters on the MSMBCLK and MSMBDAT signals that wait approximately 1µ S before sampling or driving these sig- nals.
  • Page 159 IDT Configuration Registers Notes IOEXPINTF - I/O Expander Interface (0x430) ‘ Field Default Type Description Field Name Value 15:0 IOEDATA I/O Expander Data. Each bit in this field corresponds to an I/ O expander input/output signal. Reading this field returns the...
  • Page 160 IDT Configuration Registers Notes Field Default Type Description Field Name Value 29:26 SELECT I/O Expander Select. This field selects the I/O expander on which fields in this register operate. 0x0 -(ioe0) I/O expander 0 0x1 -(ioe1) I/O expander 1 0x2 -(ioe2) I/O expander 2...
  • Page 161 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:17 IOE2ADDR I/O Expander 2 Address. This field contains the SMBus Sticky address assigned to I/O expander 2 on the master SMBus interface. Reserved Reserved field. 31:25 IOE3ADDR I/O Expander 3 Address. This field contains the SMBus...
  • Page 162 IDT Configuration Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. 23:17 IOE10ADDR I/O Expander 10 Address. This field contains the SMBus Sticky address assigned to I/O expander 10 on the master SMBus interface. 31:24 Reserved Reserved field.
  • Page 163 IDT Configuration Registers Notes Field Default Type Description Field Name Value P6GPEE Port 6 General Purpose Event Enable. When this bit is set, Sticky the hot-plug INTx, MSI and PME event notification mecha- nisms defined by the PCIe base 1.1 specification are disabled for port 6 and are instead signalled through General Purpose Event (GPEN) signal assertions.
  • Page 164 IDT Configuration Registers Notes Field Default Type Description Field Name Value P14GPEE Port 14 General Purpose Event Enable. When this bit is set, Sticky the hot-plug INTx, MSI and PME event notification mecha- nisms defined by the PCIe base 1.1 specification are disabled for port 14 and are instead signalled through General Purpose Event (GPEN) signal assertions.
  • Page 165 IDT Configuration Registers Notes Field Default Type Description Field Name Value P5GPES Port 5 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal. This bit is never set if the corre- sponding general purpose event is not enabled in the GPECTL register.
  • Page 166 IDT Configuration Registers Notes Field Default Type Description Field Name Value P12GPES Port 12 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal. This bit is never set if the corre- sponding general purpose event is not enabled in the GPECTL register.
  • Page 167 IDT Configuration Registers Notes USPFCTL - Upstream Port Failover Control (0x474) Field Default Type Description Field Name Value USPSEL HWINIT Upstream Port Software Select. Modifying the value in this Sticky field initiates an upstream port failover. When read, this field indicates the current upstream port or the previous value writ- ten if an upstream port failover is in progress.

  • Page 168: Internal Switch Error Control And Status Registers

    IDT Configuration Registers Internal Switch Error Control and Status Registers Notes SWPECTL - Switch Parity Error Control (0x740) Field Default Type Description Field Name Value DEEPC Disable End-to-End Parity Checking. When this bit is set, Sticky end-to-end parity is not checked by the port and errors are never generated.
  • Page 169 IDT Configuration Registers Notes SWPERCTL - Switch Parity Error Reporting Control (0x748) Field Default Type Description Field Name Value EEPE End-to-End Parity Error Reporting. This field controls the manner in which end-to-end parity errors detected at this port are reported. An end-to-end parity error is reported as speci-...
  • Page 170 IDT Configuration Registers Notes SWTORCTL - Switch Time-Out Reporting Control (0x758) Field Default Type Description Field Name Value PTLPTO Posted TLP Time-Out Reporting. This field controls the Sticky manner in which posted TLP time-outs are reported. A time- out is reported as specified in this field whenever the corre- sponding bit in the Switch Time-Out Status (SWTOSTS) reg- ister transitions from a zero to a one.
  • Page 171 IDT Configuration Registers Notes SWTOCNT - Switch Time-Out Count (0x75C) Field Default Type Description Field Name Value PTLPTOC Posted TLP Time-Out Count. This field is incremented each Sticky time a TLP is discarded from the port’s IFB posted queue because it is more than 50 ms old.
  • Page 172 IDT Configuration Registers Notes PES34H16 User Manual 9 - 80 October 30, 2008...

  • Page 173: Jtag Boundary Scan

    Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES34H16: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 174: Table 10.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 175: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0]...
  • Page 176 IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PCI Express Interface PE9RP[0] (cont.) PE9TN[0] PE9TP[0] PE10RN[0] PE10RP[0] PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] PE11TN[0] PE11TP[0] PE12RN[0] PE12RP[0] PE12TN[0] PE12TP[0] PE13RN[0] PE13RP[0] PE13TN[0] PE13TP[0] PE14RN[0] PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0]...

  • Page 177: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell System Pins CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN P45MERGEN PERSTN RSTHALT SWMODE[3:0] — EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — Table 10.2 Boundary Scan Chain (Part 3 of 3)
  • Page 178 IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 10.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 10.4. EXTEST To Next Cell...

  • Page 179: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 10.5 Diagram of Output Enable Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.

  • Page 180: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 181: Clamp

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x8034 This field identifies the silicon as PES34H16. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES34H16.

  • Page 182: Usage Considerations

    IDT JTAG Boundary Scan Usage Considerations Notes As previously stated, there are internal pull-ups on JTAG_TRST_N, JTAG_TMS, and JTAG_TDI. However, JTAG_TCK also needs to be driven to a known value. It is best to either drive a zero on the JTAG_TCK pin when it is not being used or to use an external pull-down resistor.

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