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IDT 89HPES16T4G2 Preliminary User's Manual

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IDT
89HPES16T4G2
™
PCI Express® Switch
Preliminary User Manual
January 2013
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2013 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89HPES16T4G2

  • Page 1 ® 89HPES16T4G2 ™ PCI Express® Switch Preliminary User Manual January 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

  • Page 4: Numeric Representations

    Notes Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These terms are illustrated in Figure 1. single clock cycle high-to-low transition low-to-high...

  • Page 5: Register Terminology

    Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCIe root configura- tion writes to registers made through the slave SMBus interface or serial EEPROM register initialization.

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Link Speed Negotiation in the PES16T4G2 ................3-4 Software Management of Link Speed ..................3-5 Link Retraining..........................3-6 Slot Power Limit Support ........................ 3-6 Upstream Port ........................3-6 Downstream Port........................3-7 Link States ............................3-7 Active State Power Management ....................
  • Page 9 IDT Table of Contents Notes Extended Configuration Space Access Registers ..............8-38 Advanced Error Reporting (AER) Enhanced Capability ............8-39 Device Serial Number Enhanced Capability................. 8-45 PCI Express Virtual Channel Capability ................8-46 Power Budgeting Enhanced Capability ................8-52 Switch Status and Control Registers ..................8-53 Physical Layer Control and Status Registers ...............
  • Page 10 IDT Table of Contents Notes PES16T4G2 User Manual January 28, 2013...
  • Page 11 List of Tables ® Table 1.1 PES16T4G2 Device ID ......................1-4 Notes Table 1.2 PES16T4G2 Revision ID .....................1-4 Table 1.3 PCI Express Interface Pins....................1-4 Table 1.4 SMBus Interface Pins ......................1-5 Table 1.5 General Purpose I/O Pins....................1-6 Table 1.6 System Pins......................... 1-7 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes PES16T4G2 User Manual January 28, 2013...
  • Page 13 List of Figures ® Figure 1.1 PES16T4G2 Architectural Block Diagram ................1-2 Notes Figure 1.2 PES16T4G2 Logic Diagram ....................1-3 Figure 1.3 PES16T4G2 Port & Device Numbering ................1-11 Figure 2.1 Fundamental Reset with Serial EEPROM Initialization ............2-4 Figure 2.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....2-5 Figure 2.3 Power Enable Controlled Reset Output Mode Operation ..........2-7 Figure 2.4...
  • Page 14 IDT List of Figures Notes PES16T4G2 User Manual viii January 28, 2013...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 8-39 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 8-44 AERCES - AER Correctable Error Status (0x110) ................. 8-43 AERCTL - AER Control (0x118) ......................8-44 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............8-45 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCIEDCTL - PCI Express Device Control (0x048)..................8-21 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................8-31 PCIEDSTS - PCI Express Device Status (0x04A) ..................8-22 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................8-32 PCIELCAP - PCI Express Link Capabilities (0x04C) ................8-23 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .................8-32...
  • Page 17 IDT Register List Notes VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............8-50 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............8-51 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C) .............8-51 VID - Vendor Identification Register (0x000)...................8-10...
  • Page 18 IDT Register List Notes PES16T4G2 User Manual January 28, 2013...

  • Page 19: Pes16T4G2 Device Overview

    Introduction Notes The 89HPES16T4G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/ networking.

  • Page 20: System Diagram

    IDT PES16T4G2 Device Overview  Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode –...

  • Page 21: Logic Diagram

    IDT PES16T4G2 Device Overview Logic Diagram Reference PEREFCLKP[0] ClockS PEREFCLKN[0] Reference Clock REFCLKM Frequency Selection PE0TP[0] PE0RP[0] PCI Express PCI Express PE0TN[0] PE0RN[0] Switch Switch SerDes Input SerDes Output PE0TP[3] PE0RP[3] Port 0 Port 0 PE0TN[3] PE0RN[3] PE2TP[0] PE2RP[0] PCI Express...

  • Page 22: System Identification

    IDT PES16T4G2 Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES16T4G2 device ID is shown in Table 1.1. PCIe Device...

  • Page 23: Table 1.4 Smbus Interface Pins

    IDT PES16T4G2 Device Overview Notes Signal Type Name/Description PE2TP[3:0] PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- PE2TN[3:0] mit pairs for port 2. PE4RP[3:0] PCI Express Port 4 Serial Data Receive. Differential PCI Express receive PE4RN[3:0] pairs for port 4.

  • Page 24: Table 1.5 General Purpose I/O Pins

    IDT PES16T4G2 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2.

  • Page 25: Table 1.6 System Pins

    IDT PES16T4G2 Device Overview Notes Signal Type Name/Description GPIO[13] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[14] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[15] General Purpose I/O.

  • Page 26: Table 1.7 Test Pins

    IDT PES16T4G2 Device Overview Notes Signal Type Name/Description JTAG_TCK JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle.

  • Page 27: Pin Characteristics

    IDT PES16T4G2 Device Overview Pin Characteristics Notes Note: Some input pads of the PES16T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

  • Page 28: Port Configuration

    IDT PES16T4G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor EJTAG / JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO JTAG_TMS pull-up JTAG_TRST_N pull-up SERDES Ref- REFRES0 Analog erence Resis- REFRES2 tors REFRES4 REFRES6 Table 1.9 Pin Characteristics (Part 2 of 2) Internal resistor values under typical operating conditions are 54K Ω...

  • Page 29: Figure 1.3 Pes16T4G2 Port & Device Numbering

    IDT PES16T4G2 Device Overview Notes Port 0 Dev. 0 PES16T4G2 PCI to PCI Bridge Virtual PCI Bus Dev. 2 Dev. 4 Dev. 6 PCI to PCI PCI to PCI PCI to PCI Bridge Bridge Bridge Port 2 Port 4 Port 6 Figure 1.3 PES16T4G2 Port &...
  • Page 30 IDT PES16T4G2 Device Overview Notes PES16T4G2 User Manual 1 - 12 January 28, 2013...

  • Page 31: Clocking, Reset And Initialization

    Chapter 2 Clocking, Reset and Initialization ® Clocking Notes The PES16T4G2 has a single differential reference clock input (PEREFCLKP[0]/PEREFCLKN[0]) that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. The frequency of the reference clock inputs may be selected by the Reference Clock Mode Select (REFCLKM) input (see Table 2.1).

  • Page 32: Reset

    IDT Clocking, Reset and Initialization Notes May Be Signal Description Overridden CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.

  • Page 33: Fundamental Reset

    IDT Clocking, Reset and Initialization Fundamental Reset Notes A Fundamental Reset may be initiated by any of the following conditions: – A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input pin. – A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power is on.

  • Page 34: Figure 2.1 Fundamental Reset With Serial Eeprom Initialization

    IDT Clocking, Reset and Initialization Notes remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external agent may read and write any internal control and status registers and may access the external serial EEPROM via the EEPROMINTF register.

  • Page 35: Hot Reset

    IDT Clocking, Reset and Initialization Notes RSTHALT bit in SWCTL cleared (i.e., by slave SMBus) Tperst-clk PExREFCLKP/N Tpvperl PERSTN 20 ms max. 1ms max PLL Lock Ready for Normal Operation SerDes Link Training CDR Reset & Lock RSTHALT RSTHALT bit in SWCTL register is set...

  • Page 36: Upstream Secondary Bus Reset

    IDT Clocking, Reset and Initialization Notes • If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the current link parameters.

  • Page 37: Downstream Port Reset Outputs

    IDT Clocking, Reset and Initialization Notes When a Downstream Secondary Bus Reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted All TLPs received from corresponding downstream port and queued in the PES16T4G2 are discarded.

  • Page 38: Power Good Controlled Reset Output

    IDT Clocking, Reset and Initialization Notes When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated.

  • Page 39: Link Operation

    Chapter 3 Link Operation ® Introduction Notes Link operation in the PES16T4G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 Gbps and 5.0 Gbps. The PES16T4G2 contains four ports. All ports operate with a maximum link width of x4. The SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES16T4G2 supports automatic polarity inversion as required by the PCIe specifica- tion.

  • Page 40: Link Width Negotiation

    IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PES16T4G2 PES16T4G2 PExRP[2] PExRP[2] PExRP[3] PExRP[3] (a) x2 Port without lane reversal (b) x2 Port with lane reversal PExRP[0] PExRP[0] lane 0 PExRP[1] lane 0...

  • Page 41: Dynamic Link Width Re-Configuration Support In The Pes16T4G2

    IDT Link Operation Notes Dynamic upconfiguration and downconfiguration is done on a per-link basis, and does not result in the link going into a DL_Down state. A link can be downconfigured down to x1. A link can be upconfigured up to the negotiated link width set after a full link train.

  • Page 42: Link Speed Negotiation In The Pes16T4G2

    IDT Link Operation Notes It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the link at the target link speed or at the highest common speed supported by both components of the link, whichever is lower.

  • Page 43: Software Management Of Link Speed

    IDT Link Operation Notes When operating at 5.0 Gbps, the PES16T4G2 port initiates a link speed downgrade in the following cases: – Link speed downgrade triggered when the PHY layer cannot achieve reliable operation at the higher speed. In this case, the PES16T4G2 port continues to support the higher speed in the training-sets it transmits during link training.

  • Page 44: Link Retraining

    IDT Link Operation Notes Software can verify the link speed by reading the Current Link Speed (CLS) field of the port’s Link Status Register (PCIELSTS). Note that to force link speed to a value other than the default value, the TLS field could be configured through Serial EEPROM initialization and full link retraining forced.

  • Page 45: Downstream Port

    IDT Link Operation Downstream Port Notes A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following events occur: – A configuration write is performed to the corresponding PCIESCAP register when the link associ- ated with the downstream port is up.

  • Page 46: Active State Power Management

    IDT Link Operation Active State Power Management Notes The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement. The PES16T4G2 ASPM supports the required L0s state as well as the optional L1 state.

  • Page 47: Low-Swing Transmitter Voltage Mode

    IDT Link Operation Notes During normal operation (i.e, not polling.compliance), de-emphasis selection is done during the Recovery state. The downstream component of the link (i.e., switch upstream port or endpoint) advertises its desired de-emphasis by transmission of training sets. The upstream component of the link (i.e., switch downstream port or root-complex port) notes its link partner desired de-emphasis, and makes a decision about the de-emphasis to be used in the link.
  • Page 48 IDT Link Operation Notes PES16T4G2 User Manual 3 - 10 January 28, 2013...

  • Page 49: General Purpose I/O

    Chapter 4 General Purpose I/O ® Introduction Notes The PES16T4G2 has 16 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 50: Gpio Pin Configured As An Input

    IDT General Purpose I/O GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.

  • Page 51: Smbus Interfaces

    Chapter 5 SMBus Interfaces ® Introduction Notes The PES16T4G2 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES16T4G2, allowing every register in the device to be read or written by an external SMBus master.

  • Page 52: Master Smbus Interface

    IDT SMBus Interfaces Master SMBus Interface Notes The master SMBus interface is used during a Fundamental Reset to load configuration values from an optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other status signals.

  • Page 53: Table 5.2 Pes16T4G2 Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 5.2 PES16T4G2 Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.

  • Page 54: Figure 5.3 Sequential Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 5.3 Sequential Double Word Initialization Sequence Format...

  • Page 55: Table 5.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence.

  • Page 56: I/O Expanders

    IDT SMBus Interfaces Notes To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), the write operation may be initiated by writing the value to be written to the...

  • Page 57: Table 5.5 I/O Expander Default Output Signal Value

    IDT SMBus Interfaces Notes Outputs for ports that are disabled or are not implemented in that configuration or bond option, are set to their negated value (e.g., the power indicator is turned off, the link is down, there is no activity, etc.). The default value of I/O expander outputs is shown in Table 5.5.
  • Page 58 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES16T4G2 to I/O expander four (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.

  • Page 59: Table 5.6 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes For example, a user who neglects to configure a GPIO as an alternate function may use this feature to determine that master SMBus transactions to the I/O expander function properly and that the issue is with the interrupt logic.

  • Page 60: Table 5.7 I/O Expander 2 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 13 (I/O-1.5) P4PIN Port 4 power indicator output 14 (I/O-1.6) P4PEP Port 4 power enable output 15 (I/O-1.7) P4ILOCKP Port 4 electromechanical interlock Table 5.6 I/O Expander 0 Signals (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

  • Page 61: Slave Smbus Interface

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 3 (I/O-0.3) Unused 4 (I/O-0.4) P4LINKUPN Port 4 link up status output 5 (I/O-0.5) Unused 6 (I/O-0.6) P6LINKUPN Port 6 link up status output 7 (I/O-0.7) Unused 8 (I/O-1.0) P0ACTIVEN Port 0 activity output 9 (I/O-1.1)

  • Page 62: Smbus Transactions

    IDT SMBus Interfaces SMBus Transactions Notes The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. See the SMBus 2.0 specification for a detailed description of these transactions. – Byte and Word Write/Read – Block Write/Read Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces undefined results.

  • Page 63: Table 5.11 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes CSR Register Read or Write Operation Table 5.11 indicates the sequence of data as it is presented on the slave SMBus following the byte address of the Slave SMBus interface. Byte Field Description Position Name CCODE Command Code.

  • Page 64: Table 5.12 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Name Type Description Field BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the data word is enabled. BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8] of the data word is enabled.

  • Page 65: Table 5.14 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Position Name Description ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to access. ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte to access. DATA Data. Serial EEPROM value read or to be written.

  • Page 66: Figure 5.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec Disabled

    IDT SMBus Interfaces Notes See Table 2 in the About This Manual chapter for a definition of these abbreviations. Sample Slave SMBus Operation This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES16T4G2’s slave SMBus interface and non-shaded items are driven by an SMBus host.

  • Page 67: Figure 5.11 Serial Eeprom Write Using Smbus Block Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES16T4G2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 5.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES16T4G2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 5.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled...
  • Page 68 IDT SMBus Interfaces Notes PES16T4G2 User Manual 5 - 18 January 28, 2013...

  • Page 69: Power Management

    Chapter 6 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES16T4G2 is a power management capability structure. The power management capability structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 70: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on Fundamental Reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 71: Power Budgeting Capability

    IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES16T4G2 receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message on all active downstream ports. The PES16T4G2 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 72 IDT Power Management Notes PES16T4G2 User Manual 6 - 4 January 28, 2013...

  • Page 73: Hot-Plug And Hot-Swap

    Chapter 7 Hot-Plug and Hot-Swap ® Hot-Plug Notes As illustrated in Figures 7.1 through 7.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 7.1 illustrates the use of the PES16T4G2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 74: Figure 7.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES16T4G2 Port x Port y PCI Express PCI Express Device Device Figure 7.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES16T4G2 Master SMBus...

  • Page 75: Table 7.1 Downstream Port Hot Plug Signals

    IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES16T4G2 in an application in which one or more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a downstream slot.

  • Page 76: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes (EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode the state of the Manually-oper- ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of corre- sponding PxILOCKP I/O expander signal output.

  • Page 77: Figure 7.4 Pes16T4G2 Hot-Plug Event Signalling

    IDT Hot-Plug and Hot-Swap Notes GPEN is an alternate function of GPIO[7] and GPIO[7] will not be asserted when GPEN is asserted unless it is configured to operate as an alternate function. Whenever a port signals a hot-plug event through assertion of the GPEN signal, the corresponding port’s status bit in the General Purpose Event Status...

  • Page 78: Hot-Swap

     The hot-swap I/O buffers of the PES16T4G2 may also be used to construct proprietary hot-swap systems.  See the PES16T4G2 Data Sheet at www.idt.com for a detailed specification of I/O buffer character- istics. PES16T4G2 User Manual 7 - 6...

  • Page 79: Configuration Registers

    Chapter 8 Configuration Registers ® Configuration Space Organization Notes Each software visible register in the PES16T4G2 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES16T4G2 that cannot be accessed by the root. Each soft- ware visible register in the PES16T4G2 has a system address.

  • Page 80: Figure 8.1 Port Configuration Space Organization

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting...

  • Page 81: Upstream Port (Port 0)

    IDT Configuration Registers Upstream Port (Port 0) Notes Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 8-10 0x002 Word P0_DID DID - Device Identification Register (0x002) on page 8-10 0x004...
  • Page 82 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 8-19 0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 8-20 0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 8-21...
  • Page 83 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x184 Dword P0_SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page 8-45 0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8-46 0x200 DWord P0_PCIEVCECAP...

  • Page 84: Downstream Ports

    IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 8-54 HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 8-55 0x408 DWord HPCFGCTL GPIOFUNC - General Purpose I/O Control Function (0x418) on page 8-...
  • Page 85 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x01C Byte Px_IOBASE IOBASE - I/O Base Register (0x01C) on page 8-14 0x01D Byte Px_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 8-14 0x01E Word Px_SECSTS SECSTS - Secondary Status Register (0x01E) on page 8-15...
  • Page 86 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x07A Word Px_PCIESSTS2 PCIESSTS2 - PCI Express Slot Status 2 (0x07A) on page 8-34 0x0C0 DWord Px_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page 8-34 0x0C4 DWord...
  • Page 87 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x210 DWord Px_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 8-48 0x214 DWord Px_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 8-48 0x218 DWord Px_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 8-49...

  • Page 88: Register Definitions

    Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. See section Device ID on page 1-4. PCICMD - PCI Command Register (0x004) Field Default Type Description Field...
  • Page 89 IDT Configuration Registers Notes Field Default Type Description Field Name Value SERRE SERR Enable. Non-fatal and fatal errors detected by the bridge are reported to the Root Complex when this bit is set or the bits in the PCI Express Device Control register are set (see PCIEDCTL - PCI Express Device Control (0x048)).
  • Page 90 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Signalled System Error. This bit is set when the bridge sends a ERR_FATAL or ERR_NONFATAL message and the SERR Enable (SERRE) bit is set in the PCICMD register.
  • Page 91 IDT Configuration Registers Notes HDR - Header Type Register (0x00E) Field Default Type Description Field Name Value 0x01 Header Type. This value indicates a type 1 header with a single function bridge layout. BIST - Built-in Self Test Register (0x00F)
  • Page 92 IDT Configuration Registers Notes SUBUSN - Subordinate Bus Number Register (0x01A) Field Default Type Description Field Name Value SUBUSN Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
  • Page 93 IDT Configuration Registers Notes SECSTS - Secondary Status Register (0x01E) Field Default Type Description Field Name Value Reserved Reserved field. MDPED Master Data Parity Error. Not applicable. 10:9 DVSEL Not applicable. STAS Signalled Target Abort Status. Not applicable. RTAS Received Target Abort Status. Not applicable.
  • Page 94 IDT Configuration Registers Notes PMBASE - Prefetchable Memory Base Register (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 - (prefmem32) 32-bit prefetchable memory addressing.
  • Page 95 IDT Configuration Registers Notes PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) Field Default Type Description Field Name Value 31:0 PMLIMITU Prefetchable Memory Address Limit Upper. This field specifies the upper 32-bits of PMLIMIT. When the PMCAP field in the PMBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 96 IDT Configuration Registers Notes INTRLINE - Interrupt Line Register (0x03C) Field Default Type Description Field Name Value INTRLINE Interrupt Line. This register communicates interrupt line routing information. Values in this register are programmed by system software and are system architecture specific. The bridge does not use the value in this register.

  • Page 97: Pci Express Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value VGAEN VGA Enable. Controls the routing of processor-initiated transac- tions targeting VGA. (block) Do not forward VGA compatible addresses from the primary interface to the secondary interface (forward) Forward VGA compatible addresses from the pri- mary to the secondary interface.
  • Page 98 IDT Configuration Registers Notes Field Default Type Description Field Name Value SLOT Slot Implemented. This bit is set when the PCI Express link asso- ciated with this Port is connected to a slot. This field does not apply to an upstream port and should be set to zero.
  • Page 99 IDT Configuration Registers Notes Field Default Type Description Field Name Value 25:18 CSPLV Captured Slot Power Limit Value. This field in combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot. Power limit (in Watts) calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field.
  • Page 100 IDT Configuration Registers Notes Field Default Type Description Field Name Value ETFEN Extended Tag Field Enable. Since the bridge never generates a transaction that requires a completion, this bit has no functional effect on the device during normal operation. To aid in debug, when the SEQTAG field is set in the TLCTL regis- ter, this field controls whether tags are generated in the range from 0 through 31 or from 0 through 255.
  • Page 101 IDT Configuration Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. This field indicates the supported link speeds of the port. 1 - (gen1) 2.5 Gbps 2 - (gen2) 5 Gbps...
  • Page 102 IDT Configuration Registers Notes Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indicates support for the link bandwidth notification status and Down- interrupt mechanisms. The PES16T4G2 downstream ports stream: support the capability.
  • Page 103 IDT Configuration Registers Notes Field Default Type Description Field Name Value LRET Link Retrain. Writing a one to this field initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. This field always returns zero when read.
  • Page 104 IDT Configuration Registers Notes PCIELSTS - PCI Express Link Status (0x052) Field Default Type Description Field Name Value Current Link Speed. This field indicates the current link speed of the port. 1 - (gen1) 2.5 Gbps 2 - (gen2) 5 Gbps...
  • Page 105 IDT Configuration Registers Notes Field Default Type Description Field Name Value LBWSTS RW1C Link Bandwidth Management Status. This bit is set to indicate that either of the following have occurred without the link transition- ing through the DL_Down state. A link retraining initiated by setting the LRET bit in the PCIELCTL register has completed.
  • Page 106 IDT Configuration Registers Notes Field Default Type Description Field Name Value Hot Plug Surprise. When set, this bit indicates that a device present in the slot may be removed from the system without notice. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 107 IDT Configuration Registers Notes PCIESCTL - PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. This bit when set enables generation of a Hot-Plug interrupt or wake-up event on an attention button pressed event.
  • Page 108 IDT Configuration Registers Notes Field Default Type Description Field Name Value Power Indicator Control. When read, this register returns the cur- rent state f the Power Indicator. Writing to this register sets the indicator. This bit is read-only and has a value of zero when the correspond- ing capability is not enabled in the PCIESCAP register.
  • Page 109 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Command Completed. This bit is set when the Hot-Plug Control- ler completes an issued command. If the bit is already set, then it remains set. A single write to the PCI Express Slot Control (PCIESCTL) register is considered to be a single command even if it affects more than one field in that register.
  • Page 110 IDT Configuration Registers Notes PCIEDSTS2 - PCI Express Device Status 2 (0x06A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) Field Default Type Description Field Name Value 31:0 Reserved Reserved field.
  • Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value Selectable De-emphasis. For switch downstream ports, this bit sets the de-emphasis level when the link operates at 5.0 Gbps. For the upstream port, this bit selects the de-emphasis preference advertised via training sets (the actual de-emphasis on the link is selected by the link partner).

  • Page 112: Power Management Capability Structure

    IDT Configuration Registers Notes PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value Current De-emphasis. The value of this bit indicates the current de-emphasis level when the link operates in 5.0 Gbps. 0x0 - De-emphasis level = -6.0 dB 0x1 - De-emphasis level = -3.5 dB...
  • Page 113 IDT Configuration Registers Notes Field Default Type Description Field Name Value 18:16 Power Management Capability Version. This field indicates compliance with version two of the specification. Complies with version the PCI Bus Power Management Interface Specification, Revision 1.2. PMECLK PME Clock. Does not apply to PCI Express.

  • Page 114: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value PMEE PME Enable. When this bit is set, PME message generation is Sticky enabled for the port. If a hot plug wake-up event is desired when exiting the D3...

  • Page 115: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIADDR - Message Signaled Interrupt Address (0x0D4) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction.

  • Page 116: Extended Configuration Space Access Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 NXTPTR 0x00 Next Pointer. This field contains a pointer to the next capability structure. 31:16 Reserved Reserved field. SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) Field...

  • Page 117: Advanced Error Reporting (Aer) Enhanced Capability

    IDT Configuration Registers Advanced Error Reporting (AER) Enhanced Capability Notes AERCAP - AER Capabilities (0x100) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x1 indicates an advanced error report- ing capability structure. 19:16 CAPVER Capability Version.
  • Page 118 IDT Configuration Registers Notes Field Default Type Description Field Name Value ACSV RW1C ACS Violation Status. This bit is set when an ACS violation is Sticky detected on the port. The PES16T4G2 does not support ACS and therefore this bit is hardwired to 0x0.
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value CABORT Completer Abort Mask. The PES16T4G2 never responds to a non-posted request with a completer abort. UECOMP Unexpected Completion Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is...
  • Page 120 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the speci- Sticky ficiation. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding event is...
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in the Sticky AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 122 IDT Configuration Registers Notes AERCEM - AER Correctable Error Mask (0x114) Field Default Type Description Field Name Value RCVERR Receiver Error Mask. When this bit is set, the corresponding bit in Sticky the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.

  • Page 123: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL1DW - AER Header Log 1st Doubleword (0x11C) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 1st doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error.

  • Page 124: Pci Express Virtual Channel Capability

    IDT Configuration Registers Notes SNUMUDW - Serial Number Upper Doubleword (0x188) Field Default Type Description Field Name Value 31:0 SNUM Upper 32-bits of Device Serial Number. This field contains the Sticky upper 32-bits of the IEEE defined 64-bit extended unique identifier (EUI-64) assigned to the device.
  • Page 125 IDT Configuration Registers Notes PVCCAP2- Port VC Capability 2 (0x208) Field Default Type Description Field Name Value VCARBCAP VC Arbitration Capability. This field indicates the type of VC arbitration that is supported by the port for the low priority VC group.
  • Page 126 IDT Configuration Registers Notes VCR0CAP- VC Resource 0 Capability (0x210) Field Default Type Description Field Name Value PARBC Upstream: Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Down- Arbitration capability.
  • Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:17 PARBSEL Port Arbitration Select. This field configures the VC resource to provide a particular Port Arbitration service. The permissible values of this field is a number that corresponds to one of the asserted bits in t he Port Arbitration Capability field of the VC resource.
  • Page 128 IDT Configuration Registers Notes VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the corresponding port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:20 PHASE13 Phase 13. This field contains the port ID for the corresponding port arbitration period. 27:24 PHASE14 Phase 14. This field contains the port ID for the corresponding port arbitration period.

  • Page 130: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:20 PHASE29 Phase 29. This field contains the port ID for the corresponding port arbitration period. 27:24 PHASE30 Phase 30. This field contains the port ID for the corresponding port arbitration period.

  • Page 131: Switch Status And Control Registers

    IDT Configuration Registers Notes PWRBPBC - Power Budgeting Power Budget Capability (0x28C) Field Default Type Description Field Name Value System Allocated. When this bit is set, it indicates that the power budget for the device is included within the system power budget and that reported power data for this device should be ignored.
  • Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:10 Reserved Reserved field. SWCTL - Switch Control (0x404) Field Default Type Description Field Name Value FRST Fundamental Reset. Writing a one to this bit initiates a Funda- mental Reset. Writing a zero has no effect. This field always returns a value of zero when read.
  • Page 133 IDT Configuration Registers Notes HPCFGCTL - Hot-Plug Configuration Control (0x408) Field Default Type Description Field Name Value IPXAPN Invert Polarity of PxAPN. When this bit is set, the polarity of the Sticky PxAPN input is inverted in all ports. IPXPDN Invert Polarity of PxPDN.
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 PWR2RST 0x14 Slot Power to Reset Negation. This field contains the delay from Sticky stable downstream port power to negation of the downstream port reset in units of 10 mS. A value of zero corresponds to no delay.
  • Page 135 IDT Configuration Registers Notes SMBUSSTS - SMBus Status (0x424) Field Default Type Description Field Name Value Reserved Reserved field. SSMBADD HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface. Reserved Reserved field. 15:9...
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value MSMBIOM Master SMBus Ignore Other Masters. When this bit is set, the Sticky master SMBus proceeds with transactions regardless of whether it won or lost arbitration. ICHECK- Ignore Checksum Errors. When this bit is set, serial EEPROM Sticky initialization checksum errors are ignored (i.e., the checksum...
  • Page 137 IDT Configuration Registers Notes IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) Field Default Type Description Field Name Value Reserved Reserved field. IOE0ADDR I/O Expander 0 Address. This field contains the SMBus address Sticky assigned to I/O expander 0 on the master SMBus interface.

  • Page 138: Physical Layer Control And Status Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value P6GPEE Port 6 General Purpose Event Enable. When this bit is set, the Sticky hot-plug INTx, MSI and PME event notification mechanisms defined by the PCIe base 2.0 specification are disabled for port 6 and are instead signalled through General Purpose Event (GPEN) signal assertions.

  • Page 139: Power Management Control And Status Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value Low-Swing Mode Enable. When set, this bit enables Low- Sticky Swing mode operation at the SerDes Transmit logic. Refer to section Low-Swing Transmitter Voltage Mode on page 3-9 for further details.
  • Page 140 IDT Configuration Registers Notes PES16T4G2 User Manual 8 - 62 January 28, 2013...

  • Page 141: Jtag Boundary Scan

    Chapter 9 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES16T4G2: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 142: Table 9.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 143: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE6RN[3:0] PE6RP[3:0] PE6TN[3:0] PE6TP[3:0] PEREFCLKN[0] — PEREFCLKP[0] — REFCLKM SMBus MSMBADDR[4:1]...

  • Page 144: Test Data Register (Dr)

    IDT JTAG Boundary Scan Test Data Register (DR) Notes The Test Data register contains the following:  Bypass register  Boundary Scan registers  Device ID register These registers are connected in parallel between a common serial input and a common serial data output and are described in the following sections.

  • Page 145: Figure 9.4 Diagram Of Output Cell

    IDT JTAG Boundary Scan Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 9.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 9.5.

  • Page 146: Instruction Register (Ir)

    IDT JTAG Boundary Scan Instruction Register (IR) Notes The Instruction register allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both.

  • Page 147: Sample/Preload

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x8060 This field identifies the silicon as PES16T4G2. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES16T4G2.

  • Page 148: Validate

    IDT JTAG Boundary Scan VALIDATE Notes The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std. 1149.1 specification. RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
  • Page 149 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

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