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IDT 89HPES24T6G2 User Manual

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®
IDT
89HPES24T6G2
™
PCI Express® Switch

User Manual

April 2013
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2013 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89HPES24T6G2

  • Page 1: User Manual

    ® 89HPES24T6G2 ™ PCI Express® Switch User Manual April 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

  • Page 4: Numeric Representations

    Notes Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These terms are illustrated in Figure 1. single clock cycle high-to-low transition low-to-high...

  • Page 5: Register Terminology

    Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCIe root configura- tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial- ization.

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.
  • Page 7 Notes August 25, 2008: In Chapter 2, deleted reference to FRSTS pins. October 24, 2008: In Chapter 1, updated Table 1.2 with additional silicon revisions. November 3, 2008: Updated the description for the following fields in Chapter 8: LDIS and LRET in the PCIELCTL register, ULD in the ALRSTS register, and TLW in the PHYLCFG0 register, and changed the last Reserved field in the PCIEDCTL2 register from 31:6 to 15:6.
  • Page 8 Notes PES24T6G2 User Manual April 30, 2013...

  • Page 9: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 10 IDT Table of Contents Notes Autonomous Link Reliability Management ................3-6 Link Retraining..........................3-7 Link Down ............................3-8 Slot Power Limit Support ........................ 3-8 Upstream Port ........................3-8 Downstream Port........................3-8 Link States ............................3-8 Active State Power Management ....................3-9 Link Status ............................
  • Page 11 IDT Table of Contents Notes Subsystem ID and Subsystem Vendor ID ................8-39 Extended Configuration Space Access Registers ..............8-39 Advanced Error Reporting (AER) Enhanced Capability ............8-40 Device Serial Number Enhanced Capability................. 8-48 PCI Express Virtual Channel Capability ................8-49 Power Budgeting Enhanced Capability ................
  • Page 12 IDT Table of Contents Notes PES24T6G2 User Manual April 30, 2013...
  • Page 13 List of Tables ® Table 1.1 PES24T6G2 Device ID ......................1-5 Notes Table 1.2 PES24T6G2 Revision ID ..................... 1-5 Table 1.3 PCI Express Interface Pins....................1-6 Table 1.4 SMBus Interface Pins ......................1-7 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins.........................1-8 Table 1.7...
  • Page 14 IDT List of Tables Notes PES24T6G2 User Manual April 30, 2013...
  • Page 15 List of Figures ® Figure 1.1 PES24T6G2 Architectural Block Diagram ................1-3 Notes Figure 1.2 PES24T6G2 Logic Diagram ....................1-4 Figure 1.3 All Ports Unmerged Configuration ...................1-13 Figure 1.4 Some Ports Merged Configuration ...................1-14 Figure 1.5 All Ports Merged Configuration ..................1-14 Figure 2.1 Fundamental Reset with Serial EEPROM initialization ............2-4 Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state .......2-5...
  • Page 16 IDT List of Figures Notes PES24T6G2 User Manual viii April 30, 2013...
  • Page 17 Register List ® AERCAP - AER Capabilities (0x100) ..................... 8-40 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 8-46 AERCES - AER Correctable Error Status (0x110) ................. 8-45 AERCTL - AER Control (0x118)......................8-47 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............8-47 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 18 IDT Register List Notes PBUSN - Primary Bus Number Register (0x018)..................8-14 PCICMD - PCI Command Register (0x004)....................8-10 PCIECAP - PCI Express Capability (0x040) ...................8-20 PCIEDCAP - PCI Express Device Capabilities (0x044) ................8-21 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............8-32 PCIEDCTL - PCI Express Device Control (0x048)..................8-22...
  • Page 19 IDT Register List Notes SUBUSN - Subordinate Bus Number Register (0x01A)................8-14 SWCTL - Switch Control (0x404) ......................8-57 SWSTS - Switch Status (0x400) ......................8-56 VCR0CAP- VC Resource 0 Capability (0x210)..................8-51 VCR0CTL- VC Resource 0 Control (0x214)....................8-51 VCR0STS - VC Resource 0 Status (0x218)....................8-52 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............8-53...
  • Page 20 IDT Register List Notes PES24T6G2 User Manual April 30, 2013...

  • Page 21: Pes24T6G2 Device Overview

    Introduction Notes The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port Gen2 peripheral chip that performs PCI Express base switching with a feature set optimized for high performance applications such as servers, storage, and communications systems.
  • Page 22 IDT PES24T6G2 Device Overview Notes  Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Power Management Interface specification (PCI-PM 1.1) • Supports device power management states: D0, D3 and D3 cold –...
  • Page 23 IDT PES24T6G2 Device Overview Switch Core D-Bus Bus Decoupler D-Bus U-Bus Arbiter Queue U-Bus Arbiter GPIO Controller Master SMBus Interface Slave Input Input Input Input Input Input SMBus Frame Frame Frame Frame Frame Frame Interface Buffer Buffer Buffer Buffer Buffer...

  • Page 24: Logic Diagram - Pes24T6G2

    IDT PES24T6G2 Device Overview Logic Diagram — PES24T6G2 Reference PEREFCLKP Clocks PEREFCLKN Reference Clock REFCLKM Frequency Selection PE0TP[0] PCI Express PE0TN[0] PE0RP[0] PCI Express Switch PE0RN[0] Switch SerDes Output PE0TP[3] SerDes Input Port 0 PE0TN[3] PE0RP[3] Port 0 PE0RN[3] PE1TP[0]...

  • Page 25: Vendor Id

    IDT PES24T6G2 Device Overview Vendor ID Notes All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES24T6G2 device ID is shown in Table 1.1. PCIe Device Device ID 0x806E Table 1.1 PES24T6G2 Device ID...

  • Page 26: Pin Description

    IDT PES24T6G2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES24T6G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 27: Table 1.4 Smbus Interface Pins

    IDT PES24T6G2 Device Overview Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus.

  • Page 28: Table 1.6 System Pins

    IDT PES24T6G2 Device Overview Notes Signal Type Name/Description GPIO[7] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] General Purpose I/O.

  • Page 29: Table 1.7 Test Pins

    IDT PES24T6G2 Device Overview Notes Signal Type Name/Description P45MERGEN Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled high internally via a 92K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port.

  • Page 30: Table 1.8 Power, Ground, And Serdes Resistor Pins

    IDT PES24T6G2 Device Overview Notes Signal Type Name/Description REFRES0 Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.

  • Page 31: Pin Characteristics

    IDT PES24T6G2 Device Overview Pin Characteristics Notes Note: Some input pads of the PES24T6G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

  • Page 32: Port Configuration

    IDT PES24T6G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor General Pur- GPIO[10:0] LVTTL STI, pull-up pose I/O High Drive System Pins CCLKDS LVTTL Input pull-up CCLKUS Input pull-up MSMBSMODE Input pull-down P01MERGEN pull-up P23MERGEN pull-up...

  • Page 33: Figure 1.3 All Ports Unmerged Configuration

    IDT PES24T6G2 Device Overview Notes When ports x and y are merged, the switch port, the PCI-to-PCI bridge, and all associated resources associated with port y are disabled and the following modifications are made to the default PES24T6G2 configuration. – All of the output signals associated with port y remain in a negated state (e.g., hot plug outputs, link status signals, port reset output, etc.)

  • Page 34: Figure 1.4 Some Ports Merged Configuration

    IDT PES24T6G2 Device Overview Notes Port 0 Dev. 0 PES24T6G2 PCI to PCI Bridge Virtual PCI Bus Dev. 2 Dev. 5 Dev. 3 PCI to PCI PCI to PCI PCI to PCI Bridge Bridge Bridge Port 2 Port 3 Port 5 Figure 1.4 Some Ports Merged Configuration...

  • Page 35: Clocking, Reset And Initialization

    Chapter 2 Clocking, Reset and Initialization ® Clocking Notes The PES24T6G2 has a single differential reference clock input (PEREFCLKP/PEREFCLKN) that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. The frequency of the reference clock input is set to 100MHz. Note: There are no skew requirement between the reference clock inputs.

  • Page 36: Reset

    IDT Clocking, Reset and Initialization Notes May Be Signal Description Overridden P45MERGEN Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a single x8 port. The SerDes lanes associated with port 5 become lanes 4 through 7 of port 4.
  • Page 37 IDT Clocking, Reset and Initialization Notes When configured to operate in normal mode, the following reset sequence is executed. 1. Wait for the Fundamental Reset condition to clear (e.g., negation of PERSTN). Note that PERSTN must be asserted for at least 100ms (Tpvperl) after the PES24T6G2 power supplies are stable, and 100µs (Tperst-clk) after the reference clock input is stable.

  • Page 38: Figure 2.1 Fundamental Reset With Serial Eeprom Initialization

    IDT Clocking, Reset and Initialization Notes PES24T6G2 responds to a Configuration Request with Configuration-Request-Retry-Status Completion. Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master SMBus operating frequency of 100 KHz.

  • Page 39: Hot Reset

    IDT Clocking, Reset and Initialization Notes RSTHALT bit in SWCTL cleared (i.e., by slave SMBus) Tperst-clk (100us) REFCLK* Tpvperl (100ms) PERSTN 20 ms max. s PLL Lock Ready for Normal Operation SerDes Link Training CDR Reset & Lock RSTHALT RSTHALT bit in SWCTL register is set...

  • Page 40: Upstream Secondary Bus Reset

    IDT Clocking, Reset and Initialization Notes • If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, link retraining is initiated on the corresponding port using the current link parameters.

  • Page 41: Downstream Port Reset Outputs

    IDT Clocking, Reset and Initialization Notes When a Downstream Secondary Bus Reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted. All TLPs received from corresponding downstream port and queued in the PES24T6G2 are discarded.

  • Page 42: Power Good Controlled Reset Output

    IDT Clocking, Reset and Initialization Power Good Controlled Reset Output Notes As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply.

  • Page 43: Link Operation

    Chapter 3 Link Operation ® Introduction Notes Link operation in the PES24T6G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 Gbps and 5.0 Gbps. The PES24T6G2 contains six x4 ports which may be merged in pairs to form x8 ports.

  • Page 44: Link Width Negotiation

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES24T6G2 PES24T6G2 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5]...

  • Page 45: Dynamic Link Width Reconfiguration

    IDT Link Operation Notes The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP) register contains the maximum link width of the port. This field is of RWL type and may be modified when the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the maximum link width of the port to be configured.

  • Page 46: Link Speed Negotiation

    IDT Link Operation Notes exchanged with the link partner during link training. A Downstream port link partner may autonomously change link width. When this occurs, the PES24T6G2 downstream port sets the Link Autonomous Band- width Status (LABWSTS) bit in the PCIELSTS register.

  • Page 47: Software Management Of Link Speed

    IDT Link Operation Notes Note that in this case the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register of the downstream port is not set, since the initial link speed upgrade was not caused by a software directed link retrain or by link reliability issues.
  • Page 48 IDT Link Operation Autonomous Link Reliability Management Notes As mentioned above, an unreliable link exhibits recurrent errors. When the rate of errors is very high, the LTSSM will likely be unable to communicate with the link partner and automatically revert to the lowest possible link speed (i.e., 2.5 Gbps).

  • Page 49: Link Retraining

    IDT Link Operation Notes Once the link speed is downgraded, the link speed will remain at 2.5 Gbps until the link fully retrains (i.e., the PHY LTSSM transitions through the Detect state) or the LRET bit is set in the PCIELCTL register, with a target link speed of 5.0 Gbps.

  • Page 50: Link Down

    IDT Link Operation Notes PES24T6G2 on page 3-4. When the speed of the link is downgraded as a result of link retraining, the PHY LTSSM remains at the downgraded speed until the link partner requests a link speed upgrade or software sets the Link Retrain (LRET) bit in the PCIELCTL register.

  • Page 51: Active State Power Management

    IDT Link Operation Notes • A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states. Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 3.3 PES24T6G2 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management.

  • Page 52: Link Status

    IDT Link Operation Link Status Notes Associated with each port is a Port Link Up (PxLINKUPN) status output and a Port Activity (PxAC- TIVEN) status output. These outputs are provided on I/O expander 4. See section I/O Expanders on page 5-7 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
  • Page 53 IDT Link Operation Notes The PES24T6G2 ports are capable of establishing crosslink with any link partner, including another PES24T6G2 device. Additionally, the PES24T6G2 ports support crosslink-to-self (i.e., transmit lanes to receive lanes of same port) using a proprietary built-in mechanism in the Phy LTSSM. This mode must be explicitly enabled by setting the Self Crosslink Enable (SCLINKEN) bit in the PHYLCFG register.
  • Page 54 IDT Link Operation Notes PES24T6G2 User Manual 3 - 12 April 30, 2013...

  • Page 55: General Purpose I/O

    Chapter 4 General Purpose I/O ® Introduction Notes The PES24T6G2 has 11 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions.GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 56: Gpio Pin Configured As An Input

    IDT General Purpose I/O GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.

  • Page 57: Smbus Interfaces

    Chapter 5 SMBus Interfaces ® Introduction Notes The PES24T6G2 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES24T6G2, allowing every register in the device to be read or written by an external SMBus master.

  • Page 58: Master Smbus Interface

    IDT SMBus Interfaces Notes tration. In some systems, this external SMBus master interface may be implemented using general purpose I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these systems, the PES24T6G2 may be configured to operate in a split configuration as shown in Figure 5.1(b).

  • Page 59: Table 5.2 Pes24T6G2 Compatible Serial Eeproms

    IDT SMBus Interfaces Notes configuration spaces may be used to initialize the device. Any serial EEPROM compatible with those listed in Table 5.2 may be used to store the PES24T6G2 initialization values. Some of these devices are larger than the total size of all of the PCI configuration spaces in the PES24T6G2 that may be initialized and thus may not be fully utilized.

  • Page 60: Figure 5.3 Sequential Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.
  • Page 61 IDT SMBus Interfaces Notes The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa- tion to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an uninitialized serial EEPROM will result in a checksum mismatch. The checksum is computed in the following manner.

  • Page 62: Table 5.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence.

  • Page 63: I/O Expanders

    IDT SMBus Interfaces Notes SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access. I/O Expanders...

  • Page 64: Table 5.5 I/O Expander Default Output Signal Value

    IDT SMBus Interfaces Notes The default value of I/O expander outputs is shown in Table 5.5. Note that this default value may be modified via serial EEPROM or SMBus configuration prior to SMBus initialization by changing the state of the PCI Express Slot Control Register (PCIESCTL) or Hot-Plug Configuration Control (HPCFGCTL).
  • Page 65 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES24T6G2 to I/O expander four (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 66 SEL field in the IOEXPINTF register. The outputs for each I/O expander number are shown in Table 5.6 through 5.10. IDT suggests the following system design recommendations: – I/O expander addresses and default output values may be configured during serial EEPROM initialization.

  • Page 67: Table 5.6 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes I/O Expander 0 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P2APN Port 2 attention push button input 1 (I/O-0.1) P2PDN Port 2 presence detect input 2 (I/O-0.2) P2PFN Port 2 power fault input 3 (I/O-0.3)
  • Page 68 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) P5MRLN Port 5 manually-operated retention latch (MRL) input 12 (I/O-1.4) P5AIN Port 5 attention indicator output 13 (I/O-1.5) P5PIN Port 5 power indicator output 14 (I/O-1.6) P5PEP Port 5 power enable output 15 (I/O-1.7)

  • Page 69: Table 5.8 I/O Expander 2 Signals

    IDT SMBus Interfaces Notes I/O Expander 2 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) Unused 1 (I/O-0.1) Unused 2 (I/O-0.2) Unused 3 (I/O-0.3) Unused 4 (I/O-0.4) Unused 5 (I/O-0.5) Unused 6 (I/O-0.6) Unused 7 (I/O-0.7) Unused 8 (I/O-1.0) Unused 9 (I/O-1.1)

  • Page 70: Slave Smbus Interface

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 11 (I/O-1.3) P1MRLN Port 1 manually-operated retention latch (MRL) input 12 (I/O-1.4) P1AIN Port 1 attention indicator output 13 (I/O-1.5) P1PIN Port 1 power indicator output 14 (I/O-1.6) P1PEP Port 1 power enable output 15 (I/O-1.7)

  • Page 71: Initialization

    IDT SMBus Interfaces Initialization Notes Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-2). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The address is specified by the SSMBADDR[5,3:1] signals as shown in Table 5.11.

  • Page 72: Table 5.13 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Name Description Field FUNC- This field encodes the type of SMBus operation. TION 0 - CSR register read or write operation 1 - Serial EEPROM read or write operation 2 through 7 - Reserved SIZE This field encodes the data size of the SMBus transaction.

  • Page 73: Table 5.14 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes address and upper 6-bit doubleword system address, respectively. For example, use ADDRU = x00 and ADDRL = 0x00 to access system address 0x00000 (port 0’s Vendor/Device ID register). Use ADDRU = x00 and ADDRL = 0x01 to access system address 0x00004 (port 0’s Command/Status register).

  • Page 74: Table 5.16 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Position Name Description EEADDR Serial EEPROM Address. This field specifies the address of the Serial EEPROM on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be zero and thus the 7-bit address must be left justified.

  • Page 75: Figure 5.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec Disabled

    IDT SMBus Interfaces Notes Name Type Description Field OTHERERR Other Error. This bit is set if a misplaced START or STOP condition is detected by the master SMBus interface when accessing the serial EEPROM. This bit has the same function as the OTHERERR bit in the SMBUSSTS register.

  • Page 76: Figure 5.10 Csr Register Write Using Smbus Block Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES24T6G2 Slave CCODE (PES24T6G2 busy with previous command, not ready for a new command) SMBus Address START,END PES24T6G2 Slave CCODE (PES24T6G2 busy with previous command, not ready for a new command) SMBus Address START,END PES24T6G2 Slave...

  • Page 77: Figure 5.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES24T6G2 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES24T6G2 Slave CCODE ADDRU SMBus Address END, Byte PES24T6G2 Slave CCODE (PES24T6G2 not ready with data) SMBus Address START,Word PES24T6G2 Slave CCODE SMBus Address START,Word PES24T6G2 Slave...
  • Page 78 IDT SMBus Interfaces Notes PES24T6G2 User Manual 5 - 22 April 30, 2013...

  • Page 79: Power Management

    Chapter 6 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES24T6G2 is a power management capability structure. The power management capability structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 80: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on Fundamental Reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Man- agement Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 81: Power Budgeting Capability

    IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES24T6G2 receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES24T6G2 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 82 IDT Power Management Notes PES24T6G2 User Manual 6 - 4 April 30, 2013...

  • Page 83: Hot-Plug And Hot-Swap

    Chapter 7 Hot-Plug and Hot-Swap ® Hot-Plug Notes As illustrated in Figures 7.1 through 7.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 7.1 illustrates the use of the PES24T6G2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 84: Figure 7.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES24T6G2 Port x Port y PCI Express PCI Express Device Device Figure 7.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES24T6G2 Master SMBus...
  • Page 85 IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES24T6G2 in an application in which one or more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a downstream slot.

  • Page 86: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the corresponding PxILOCKP I/O expander signal output.

  • Page 87: Legacy System Hot-Plug Support

    IDT Hot-Plug and Hot-Swap Legacy System Hot-Plug Support Notes Some systems require support for operating systems that lack PCIe hot-plug support. The PES24T6G2 supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot- plug.

  • Page 88: Hot-Swap

    IDT Hot-Plug and Hot-Swap Notes General Purpose Event Enable General Purpose Event Mechanism Interrupt Slot Control Disable Register Activate INTx Hot-Plug Interrupt Mechanism Enable Slot Status Register Activate MSI Mechanism Command Completed Enable Command Completed MSI Enable RW1C RW1C Attention Button...

  • Page 89: Configuration Registers

    Chapter 8 Configuration Registers Configuration Space Organization Notes Each software visible register in the PES24T6G2 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES24T6G2 that cannot be accessed by the root. Each soft- ware visible register in the PES24T6G2 has a system address.

  • Page 90: Upstream Port (Port 0)

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting...
  • Page 91 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 8-13 0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13 0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13...
  • Page 92 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 8-33 0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 8-33 0x070...
  • Page 93 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8- 0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) on page 8-49 0x204...

  • Page 94: Downstream Ports

    IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 8-57 0x408 DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 8-60 0x418 DWord GPIOFUNC GPIOFUNC - General Purpose I/O Control Function (0x418) on page...
  • Page 95 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 8-13 0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13 0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 8-13...
  • Page 96 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x054 DWord Px_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page 8-28 0x058 Word Px_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 8-30 0x05A Word Px_PCIESSTS...
  • Page 97 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword Px_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 8- 0x120 Dword Px_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 8- 0x124...

  • Page 98: Register Definitions

    Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. See section Device ID on page 1-5. PCICMD - PCI Command Register (0x004) Field Default Type Description Field...
  • Page 99 IDT Configuration Registers Notes Field Default Type Description Field Name Value Memory Access Enable. When this bit is cleared, the bridge does not respond to memory and prefetchable memory space access from the primary bus specified by MBASE, MLIMIT, PMBASE and PMLIMIT.
  • Page 100 IDT Configuration Registers Notes Field Default Type Description Field Name Value INTS INTx Status. This bit is set when an INTx interrupt is pending from the device. INTx emulation interrupts forwarded by switch ports from devices downstream of the bridge are not reflected in this bit.
  • Page 101 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 0x04 Sub Class Code. This value indicates that the device is a PCI- PCI bridge. 23:16 BASE 0x06 Base Class Code. This value indicates that the device is a bridge.
  • Page 102 IDT Configuration Registers Notes BAR1 - Base Address Register 1 (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus num- ber of the PCI bus segment to which the primary interface of the bridge is connected.
  • Page 103 IDT Configuration Registers Notes IOBASE - I/O Base Register (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. 0x0 -(io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing.
  • Page 104 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Detected Parity Error. This bit is set by the bridge whenever it receives a poisoned TLP on the secondary side regardless of the state of the PERRE bit in the PCI Command register...
  • Page 105 IDT Configuration Registers Notes PMLIMIT - Prefetchable Memory Limit Register (0x026) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge sup- ports 32-bit or 64-bit prefetchable memory addressing. This bit always reflects the value in the PMCAP field in the PMBASE reg- ister.
  • Page 106 IDT Configuration Registers Notes IOLIMITU - I/O Limit Upper Register (0x032) Field Default Type Description Field Name Value 15:0 IOLIMITU Prefetchable IO Limit Upper. This field specifies the upper 16- bits of IOLIMIT. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 107 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot- plug by the downstream ports and to report memory errors by the upstream port.

  • Page 108: Pci Express Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
  • Page 109 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD HWINIT Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. For all bond options the default value is 0x4 which corresponds to 2048 bytes.
  • Page 110 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:26 CSPLS Captured Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for the upstream port.
  • Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value PFEN Phantom Function Enable. The bridge does not support phan- tom function numbers. Therefore, this field is hardwired to zero. AUXPMEN Auxiliary Power PM Enable. The device does not implement this capability.
  • Page 112 IDT Configuration Registers Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. This field indicates the supported link speeds of the port. 1 - (gen1) 2.5 Gbps 2 - (gen2) 5 Gbps...
  • Page 113 IDT Configuration Registers Notes Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indi- cates support for the link bandwidth notification status and inter- rupt mechanisms. The PES24T6G2 downstream ports support Downstream: the capability.
  • Page 114 IDT Configuration Registers Notes Field Default Type Description Field Name Value LRET Link Retrain. Writing a one to this field initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. This field always returns zero when read.
  • Page 115 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:12 Reserved Reserved field. PCIELSTS - PCI Express Link Status (0x052) Field Default Type Description Field Name Value Current Link Speed. This field indicates the current link speed of the port.
  • Page 116 IDT Configuration Registers Notes Field Default Type Description Field Name Value DLLLA Data Link Layer Link Active. This bit indicates the status for the data link control and management state machine. 0x0 - (not_active) Data link layer not active state...
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value ATTIP Attention Indicator Present. This bit is set when an Attention Indicator is implemented for the port. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 118 IDT Configuration Registers Notes PCIESCTL - PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. This bit when set enables generation of a Hot-Plug interrupt or wake-up event on an atten- tion button pressed event.
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value Power Indicator Control. When read, this register returns the current state f the Power Indicator. Writing to this register sets the indicator. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP register.
  • Page 120 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Command Completed. This bit is set when the Hot-Plug Con- troller completes an issued command. If the bit is already set, then it remains set. A single write to the PCI Express Slot Control (PCIESCTL) regis- ter is considered to be a single command even if it affects more than one field in that register.
  • Page 121 IDT Configuration Registers Notes PCIEDCTL2 - PCI Express Device Control 2 (0x068) Field Default Type Description Field Name Value Reserved Reserved field. ARIFEN ARI Forwarding Enable. When set, the downstream port dis- ables its traditional Device Number field being zero enforcement...
  • Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value HASD Hardware Autonomous Speed Disable. When set, this bit pre- vents hardware from changing the link speed for device specific reasons other than to correct unreliable link operation by reduc- ing the link speed.
  • Page 123 IDT Configuration Registers Notes Field Default Type Description Field Name Value Enter Modified Compliance. When this bit is set to 1b, the port Sticky transmits the modified compliance pattern if the LTSSM enters Polling.Compliance state. This register is intended for debug, compliance testing purposes only.

  • Page 124: Power Management Capability Structure

    IDT Configuration Registers Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. Power Management Capability Structure PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name...

  • Page 125: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes PMCSR - PCI Power Management Control and Status (0x0C4) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state and to set a new power state.
  • Page 126 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:8 NXTPTR Next Pointer. This field contains a pointer to the next capability structure. This field is set to 0x0 indicating that it is the last capa- bility. Enable. This bit enables MSI.

  • Page 127: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) Field Default Type Description Field Name Value 15:0 MDATA Message Data. This field contains the lower 16-bits of data that are written when a MSI is signalled. 31:16 Reserved Reserved.

  • Page 128: Advanced Error Reporting (Aer) Enhanced Capability

    IDT Configuration Registers Notes ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configu- ration space register value pointed to by the ECFGADDR regis- ter.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value COMPTO Completion Time-out Status. A switch port does not initiate non-posted requests on its own behalf. Therefore, this field is hardwired to zero. CABORT Completer Abort Status. The PES24T6G2 never responds to a non-posted request with a completer abort.
  • Page 130 IDT Configuration Registers Notes Field Default Type Description Field Name Value SDOENERR Surprise Down Error Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not...
  • Page 131 IDT Configuration Registers Notes Field Default Type Description Field Name Value MAL- Malformed TLP Mask. When this bit is set, the corresponding bit FORMED Sticky in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the...
  • Page 132 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the speci- Sticky ficiation. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding event is...
  • Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in the Sticky AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Single Bit Error Status. When the Single Bit Error AER Reporting Sticky Enable (SBEAEREN) bit is set in the Memory Error Control (MECTL) register, this bit is set whenever a single bit error is detected in any memory associated with the port.
  • Page 135 IDT Configuration Registers Notes Field Default Type Description Field Name Value Single Bit Error Mask. When this bit is set and the Single Bit Error Sticky AER Reporting Enable (SBEAEREN) bit is set in the Memory Error Control (MECTL) register, the corresponding bit in the AERCES register is masked.

  • Page 136: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 3rd doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error.

  • Page 137: Pci Express Virtual Channel Capability

    IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capa- bility structure.
  • Page 138 IDT Configuration Registers Notes PVCCAP2- Port VC Capability 2 (0x208) Field Default Type Description Field Name Value VCARBCAP VC Arbitration Capability. This field indicates the type of VC arbitration that is supported by the port for the low priority VC group.
  • Page 139 IDT Configuration Registers Notes VCR0CAP- VC Resource 0 Capability (0x210) Field Default Type Description Field Name Value PARBC Upstream: Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Arbitration capability.
  • Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value LPAT Load Port Arbitration Table. This bit, when set, updates the Port Arbitration logic from the Port Arbitration Table for the VC resource. In addition, this field is only valid when the Port Arbitra-...
  • Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:18 Reserved Reserved field. VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the corresponding port arbitration period.
  • Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:12 PHASE11 Phase 11. This field contains the port ID for the corresponding port arbitration period. 19:16 PHASE12 Phase 12. This field contains the port ID for the corresponding port arbitration period.

  • Page 143: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:12 PHASE27 Phase 27. This field contains the port ID for the corresponding port arbitration period. 19:16 PHASE28 Phase 28. This field contains the port ID for the corresponding port arbitration period.

  • Page 144: Switch Control And Status Registers

    IDT Configuration Registers Notes PWRBD - Power Budgeting Data (0x288) Field Default Type Description Field Name Value 31:0 DATA Data. If the Data Value Select (DVSEL) field in the Power Bud- geting Data Select register contains a value of zero through 7, then this field returns the contents of the corresponding Power Budgeting Data Value (PWRBDVx) register.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value CCLKDS HWINIT Common Clock Downstream. This bit reflects the value of the CCLKDS signal sampled during Fundamental Reset. CCLKUS HWINIT Common Clock Upstream. This bit reflects the value of the CCLKUS signal sampled during Fundamental Reset.
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value HRST Hot Reset. Writing a one to this bit initiates a hot reset. Addition- ally, the upstream port’s PHY initiates a full link retrain. Writing a zero has no effect. This field always returns a value of zero when read.
  • Page 147 This field controls the extent to which device numbers are checked by downstream ports. This field is present for backwards compatibility with earlier IDT switches that implement a proprietary version of ARI forwarding. This field has no functional effect on the operation of a port when the ARI Forwarding Enable (ARIFEN) bit is set in the port’s PCI...
  • Page 148 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:20 Reserved Reserved field. HPCFGCTL - Hot-Plug Configuration Control (0x408) Field Default Type Description Field Name Value IPXAPN Invert Polarity of PxAPN. When this bit is set, the polarity of the Sticky PxAPN input is inverted in all ports.
  • Page 149 IDT Configuration Registers Notes Field Default Type Description Field Name Value RMRLWEMIL Replace MRL Status with EMIL Status. When this bit is set, the Sticky PxMRLN signal inputs are used as electromechanical lock state inputs. TEMICTL Toggle Electromechanical Interlock Control. When this bit is...
  • Page 150 IDT Configuration Registers Notes GPIOCFG - General Purpose I/O Configuration (0x41C) Field Default Type Description Field Name Value 15:0 GPIOCFG GPIO Configuration. Each bit in this field controls the corre- Sticky sponding GPIO pin. When a bit is configured as a general pur- pose I/O pin and the corresponding bit in this field is set, then the pin is configured as a GPIO output.
  • Page 151 IDT Configuration Registers Notes Field Default Type Description Field Name Value LAERR RW1C Lost Arbitration Error. When the master SMBus interface loses arbitration for the SMBus, it automatically re-arbitrates for the SMBus. If the master SMBus interface loses 16 consecutive arbi- tration attempts, then the transaction is aborted and this bit is set.
  • Page 152 IDT Configuration Registers Notes Field Default Type Description Field Name Value 21:20 MSMBMODE Master SMBus Mode. The master SMBus contains internal Sticky glitch counters on the MSMBCLK and MSMBDAT signals that wait approximately 1uS before sampling or driving these signals.
  • Page 153 IDT Configuration Registers Notes IOEXPINTF - I/O Expander Interface (0x430) ‘ Field Default Type Description Field Name Value 15:0 IOEDATA I/O Expander Data. Each bit in this field corresponds to an I/O expander input/output signal. Reading this field returns the cur- rent value of the corresponding I/O pin state of the I/O expander number selected in the Select (SEL) field in this register (i.e., the...
  • Page 154 IDT Configuration Registers Notes IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) Field Default Type Description Field Name Value Reserved Reserved field. IOE0ADDR I/O Expander 0 Address. This field contains the SMBus address Sticky assigned to I/O expander 0 on the master SMBus interface.
  • Page 155 IDT Configuration Registers Notes Field Default Type Description Field Name Value P2GPEE Port 2 General Purpose Event Enable. When this bit is set, the Sticky hot-plug INTx, MSI and PME event notification mechanisms defined by the PCIe base 2.0 specification are disabled for port 2 and are instead signalled through General Purpose Event (GPEN) signal assertions.
  • Page 156 IDT Configuration Registers Notes Field Default Type Description Field Name Value P4GPES Port 4 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal. This bit is never set if the correspond- ing general purpose event is not enabled in the GPECTL register.
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value ILSCC Upstream: Initial Link Speed Change Control. This field determines whether a port automatically initiates a speed change to Gen2 speed, if Gen2 speed is permissible, after initial entry to L0 from Down- Detect.
  • Page 158 IDT Configuration Registers Notes Field Default Type Description Field Name Value 13:12 RLWS Reconfigure Link Width Status. This field indicates the status of a link width upconfiguration or downconfiguration request. 0x0 - Idle (request not yet serviced) 0x1 - Success (re-configuration of the link succeeded)
  • Page 159 IDT Configuration Registers Notes PHYLSTATE0 - Phy Link State 0 (0x540) Field Default Type Description Field Name Value LTSSMSTAT Phy LTSSM State Machine State. This field contains the current state of the Phy Link Training and Status State Machine (LTSSM).

  • Page 160: Autonomous Link Reliability Management

    IDT Configuration Registers Notes PHYPRBS - Phy PRBS Seed (0x55C) Field Default Type Description Field Name Value 15:0 SEED 0xFFFF Phy PRBS Seed Value. This field contains the PHY PRBS Sticky seed value used for crosslink operation. When the value in this register is modified, the PRBS counter associated with this seed is reset to the seed value and re-starts counting.
  • Page 161 IDT Configuration Registers Notes ALRSTS - Autonomous Link Reliability Status (0x564) Field Default Type Description Field Name Value RW1C Unreliable Link Detected. This bit is set by hardware to indi- Sticky cate that the Autonomous Link Reliability logic has detected an unreliable link.
  • Page 162 IDT Configuration Registers Notes ALRCNT - Autonomous Link Reliability Counter (0x56C) Field Default Type Description Field Name Value ENCNT Error Number Count. This field contains the count for the num- ber of errors detected by the Autonomous Link Reliability Man- agement logic.

  • Page 163: Jtag Boundary Scan

    Chapter 9 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES24T6G2: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 164: Table 9.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 165: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0]...

  • Page 166: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell System Pins (cont.) PERSTN RSTHALT SWMODE[2:0] — EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — SerDes Reference REFRES0 — Resistors REFRES1 — REFRES2 —...

  • Page 167: Figure 9.3 Diagram Of Observe-Only Input Cell

    IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 9.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 9.4. EXTEST To Next Cell...

  • Page 168: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 9.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.

  • Page 169: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 170: Clamp

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x806E This field identifies the silicon as PES24T6G2. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES24T6G2.
  • Page 171 IDT JTAG Boundary Scan Notes the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test- Logic-Reset controller state by continuously holding JTAG_TRST_N low and/or JTAG_TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it.
  • Page 172 IDT JTAG Boundary Scan Notes PES24T6G2 User Manual 9 - 10 April 30, 2013...

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