IDT 89HPES64H16G2 PCI Express Switch Manuals

Manuals and User Guides for IDT 89HPES64H16G2 PCI Express Switch. We have 1 IDT 89HPES64H16G2 PCI Express Switch manual available for free PDF download: User Manual

IDT 89HPES64H16G2 User Manual

IDT 89HPES64H16G2 User Manual (318 pages)

PCI Express

Brand: IDT | Category: Switch | Size: 3.94 MB

Table of Contents

User Manual
1
About this Manual

3
- Content Summary
  3
- Signal Nomenclature
  4
- Numeric Representations
  4
- Data Units
  4
- Register Terminology
  5
- Use of Hypertext
  7
- Reference Documents
  7
- Revision History
  7
- Table of Contents
  11
PES64H16G2 Device Overview

25
- Introduction
  25
- Features
  25
- Logic Diagram
  29
- System Identification
  30
  - Vendor ID
    30
  - Device ID
    30
  - Revision ID
    30
  - Jtag ID
    30
  - Ssid/Ssvid
    30
  - Device Serial Number Enhanced Capability
    30
  - Table 1.3 PES64H16G2 Revision ID
    30
- Pin Description
  31
- Table 1.4 PCI Express Interface Pins
  31
- Table 1.5 Reference Clock Pins
  33
- Table 1.6 Smbus Interface Pins
  33
- Table 1.7 General Purpose I/O Pins
  33
- Table 1.8 System Pins
  37
- Table 1.9 Test Pins
  40
- Table 1.10 Power, Ground, and Serdes Resistor Pins
  40
- Pin Characteristics
  42
- Table 1.11 Pin Characteristics
  42
Architectural Overview

45
- Introduction
  45
- Switch Partitioning
  46
- Dynamic Reconfiguration
  47
Switch Core

49
- Introduction
  49
- Switch Core Architecture
  49
  - Ingress Buffer
    49
  - Table 3.1 IFB Buffer Sizes
    49
  - Egress Buffer
    50
  - Table 3.2 EFB Buffer Sizes
    50
  - Crossbar Interconnect
    51
  - Datapaths
    51
  - Table 3.3 Replay Buffer Storage Limit
    51
- Packet Ordering
  52
- Arbitration
  53
  - Table 3.4 Packet Ordering Rules in the PES64H16G2
    53
  - Port Arbitration
    54
- Cut-Through Routing
  54
- Table 3.5 Conditions for Cut-Through Transfers
  55
- Request Metering
  56
- Internal Errors
  61
Clocking

65
Reset and Initialization

69
Switch Partitions

79
- Introduction
  79
  - Partition Configuration
    79
  - Partition State
    80
  - Partition State Change
    81
- Switch Ports
  82
  - Switch Port Mode
    82
- Port Operating Mode Change
  85
- Partition and Port Configuration
  93
  - Static Reconfiguration
    93
  - Dynamic Reconfiguration
    94
Link Operation

97
- Introduction
  97
- Polarity Inversion
  97
- Lane Reversal
  97
- Link Width Negotiation
  101
  - Link Width Negotiation in the Presence of Bad Lanes
    102
- Dynamic Link Width Reconfiguration
  102
- Link Speed Negotiation
  102
  - Link Speed Negotiation in the PES64H16G2
    103
  - Software Management of Link Speed
    104
- Link Retraining
  105
- Link down
  106
- Slot Power Limit Support
  106
  - Upstream Port
    106
  - Downstream Port
    106
- Link States
  107
- Active State Power Management
  107
  - L0S ASPM
    108
  - L1 Aspm
    108
- L1 ASPM Entry Rejection Timer
  109
- Link Status
  110
- De-Emphasis Negotiation
  110
- Crosslink
  111
- Gen1 Compatibility Mode
  112
- Table 7.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
  113
Serdes

115
Theory of Operation

131
Hot-Plug and Hot-Swap

151
- Introduction
  151
- Hot-Plug Signals
  153
- Table 10.1 Port Hot Plug Signals
  153
- Table 10.2 Negated Value of Unused Hot-Plug Output Signals
  154
- Port Reset Outputs
  155
  - Power Enable Controlled Reset Output
    155
  - Power Good Controlled Reset Output
    156
- Hot-Plug Events
  156
- Legacy System Hot-Plug Support
  157
- Hot-Swap
  158
Smbus Interfaces

159
- Introduction
  159
- Table 11.1 PES64H16G2 Power Management State Transition Diagram
  160
Power Management

161
Register Organization

187
- Introduction
  187
Multicast

193
- Introduction
  193
  - Partial-Byte Access to Word and Dword Registers
    194
- Address Maps
  195
PCI to PCI Bridge and Proprietary Port Specific Registers

211
Switch Configuration and Status Registers

283
- Switch Control and Status Registers
  283
- Internal Switch Timer
  285
- Switch Partition and Port Registers
  286
- Protection
  289
- Serdes Control and Status Registers
  289
- General Purpose I/O Registers
  297
- Hot-Plug and Smbus Interface Registers
  301
JTAG Boundary Scan

309
- Introduction
  309
- Test Access Point
  309
- Signal Definitions
  309
- Figure 18.1 Diagram of the JTAG Logic
  309
- Table 18.1 JTAG Pin Descriptions
  310
- Figure 18.2 State Diagram of the TAP Controller
  310
- Boundary Scan Chain
  311
- Table 18.2 Boundary Scan Chain
  311
- Test Data Register (DR)
  313
- Instruction Register (IR)
  315
  - Figure 18.5 Diagram of Bidirectional Cell
    315
  - Bypass
    316
  - Extest
    316
  - Sample/Preload
    316
  - Table 18.3 Instructions Supported by the JTAG Boundary Scan
    316
  - Clamp
    317
  - Extest_Train
    317
  - Figure 18.6 Device ID Register Format
    317
  - Idcode
    317
  - Table 18.4 System Controller Device Identification Register
    317
  - Validate
    317
  - Extest_Pulse
    318
  - Reserved
    318
  - Usage Considerations
    318

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