IDT 89HPES64H16G2 User Manual page 200

IDT Register Organization
Cfg.
Size
Offset
0x10C Dword
0x110 Dword
0x114 Dword
0x118 Dword
0x11C Dword
0x120 Dword
0x124 Dword
0x128 Dword
0x180 Dword
0x184 Dword
0x188 Dword
0x200 DWord
0x204 DWord
0x208 DWord
0x20C Word
0x20E Word
0x210 DWord
0x214 DWord
0x218 DWord
0x240 DWord
0x244 DWord
0x248 DWord
0x24C DWord
0x280 Dword
0x284 Dword
0x288 Dword
0x28C Dword
0x300 Dword
0x304 Dword
0x308 Dword
PES64H16G2 User Manual
Register
Mnemonic
AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 16-36
AERCES AERCES - AER Correctable Error Status (0x110) on page 16-37
AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 16-38
AERCTL AERCTL - AER Control (0x118) on page 16-40
AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 16-40
AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 16-40
AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 16-40
AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page 16-41
SNUMCAP SNUMCAP - Serial Number Capabilities (0x180) on page 16-41
SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page 16-41
SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 16-41
PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) on
page 16-42
PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 16-42
PVCCAP2 PVCCAP2- Port VC Capability 2 (0x208) on page 16-42
PVCCTL PVCCTL - Port VC Control (0x20C) on page 16-43
PVCSTS PVCSTS - Port VC Status (0x20E) on page 16-43
VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 16-43
VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 16-44
VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 16-44
VCR0TBL0 VCR0TBL0 - VC Resource 0 Port Arbitration Table Entry 0 (0x240) on
page 16-45
VCR0TBL1 VCR0TBL1 - VC Resource 0 Port Arbitration Table Entry 1 (0x244) on
page 16-46
VCR0TBL2 VCR0TBL2 - VC Resource 0 Port Arbitration Table Entry 2 (0x248) on
page 16-46
VCR0TBL3 VCR0TBL3 - VC Resource 0 Port Arbitration Table Entry 3 (0x24C) on
page 16-47
PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 16-47
PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 16-48
PWRBD PWRBD - Power Budgeting Data (0x288) on page 16-48
PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on page
16-48
PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on
page 16-48
PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on
page 16-48
PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on
page 16-48
Table 15.4 PCI-to-PCI Bridge Configuration Space Registers (Part 3 of 4)
Register Definition
15 - 8
US DS
April 5, 2013