IDT 89HPES64H16G2 User Manual page 268

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
4
5
7:6
9:8
10
PES64H16G2 User Manual
Default
Type
Value
CCIE RW 0x0
SWSticky
HPIE RW 0x0
SWSticky
AIC RW 0x3
SWSticky
PIC RW 0x1
SWSticky
PCC RW 0x0
SWSticky
Description
Command Complete Interrupt Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Hot Plug Interrupt Enable.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Attention Indicator Control.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Power Indicator Control.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
Power Controller Control.
This field contains the initial value of the corresponding field in the
PCI Express Slot Control (PCIESCTL) register when the corre-
sponding slot or hot-plug capability is enabled.
A partition reset does not reset slot and hot-plug capability bits
since they are RWL. The intent of this field is to allow the initial
value of the corresponding field in the PCIESCTL register to be
controlled following a partition fundamental reset.
A write to this field causes an immediate effect in the correspond-
ing field in the PCIESCTL register.
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