User Manuals: IDT Tsi578 RapidIO Switch

Manuals and User Guides for IDT Tsi578 RapidIO Switch. We have 1 IDT Tsi578 RapidIO Switch manual available for free PDF download: User Manual

IDT Tsi578 User Manual

IDT Tsi578 User Manual (527 pages)

Serial RapidIO Switch

Brand: IDT | Category: Switch | Size: 2.85 MB

Table of Contents

User Manual
1
Table of Contents
3
About this Document

17
- Scope
  17
- Document Conventions
  17
- Revision History
  18
1 Functional Overview

21
- Overview
  21
- Serial Rapidio Interface
  26
  - Features
    26
  - Transaction Flow Overview
    26
  - Maintenance Requests
    27
  - Control Symbols
    27
- Multicast Engine
  27
  - Multicast Operation
    27
  - Features
    28
- Serial Rapidio Electrical Interface
  28
- Figure 4: Tsi578 MAC Block Diagram
  29
- Internal Switching Fabric (ISF)
  30
- Internal Register Bus (AHB)
  30
- I 2 C Interface
  30
- JTAG Interface
  32
2 Serial Rapidio Interface

35
- Overview
  35
  - Features
    35
  - Transaction Flow Overview
    36
  - Maintenance Requests
    36
  - Control Symbols
    36
- Transaction Flow
  37
- Lookup Tables
  37
  - Filling the Lookup Tables
    38
  - Figure 5: LUT Mode of Operation
    39
  - LUT Modes
    40
  - Flat Mode
    40
  - Figure 6: Flat Mode Routing
    41
  - Figure 7: Flat Mode Routing Example
    42
  - Figure 8: Flat Mode LUT Configuration Example
    43
  - Hierarchical Mode
    45
  - Figure 9: Hierarchical Mode
    46
  - Figure 10: Hierarchical Mode Routing Example
    47
  - Mixed Mode of Operation
    49
  - Lookup Table Parity
    49
  - Lookup Table Error Summary
    50
  - Table 1: Error Summary
    50
  - Lookup Table Entry States
    51
  - Table 2: Lookup Table States
    51
- Maintenance Packets
  53
- Table 3: Examples of Maintenance Packets with Hop Count = 0 and Associated Tsi578 Responses
  53
- Multicast Event Control Symbols
  55
  - MCS Reception
    55
  - Generating an MCS
    56
  - Restrictions
    56
- Reset Control Symbol Processing
  57
- Data Integrity Checking
  57
  - Packet Data Integrity Checking
    57
  - Control Symbol Data Integrity Checking
    57
- Error Management
  57
  - Software Assisted Error Recovery
    58
- Hot Insertion and Hot Extraction
  59
  - Hot Insertion
    60
  - Hot Extraction
    61
  - Hot Extraction System Notification
    62
- Loss of Lane Synchronization
  62
  - Figure 11: LOLS Silent Period
    63
  - Dead Link Timer
    64
  - Lane Sync Timer
    64
3 Serial Rapidio Electrical Interface

65
4 Internal Switching Fabric

85
5 Multicast

103
- Overview
  103
  - Multicast Operation
    103
  - Features
    103
  - Multicast Operation with Multiple Tsi57X Switches
    104
  - Figure 20: Multicast Operation - Option 1
    104
  - Multicast Terminology
    105
  - Figure 21: Multicast Operation - Option 2
    105
  - Table 12: Multicast Terminology
    105
  - Multicast Behavior Overview
    106
  - Multicast Work Queue
    107
  - Broadcast Buffers
    107
  - Figure 22: Multicast Packet Flow in the Tsi578
    108
- Multicast Group Tables
  110
- Arbitration for Multicast Engine Ingress Port
  117
- Figure 25: IDT-Specific Multicast Mask Configuration
  117
- Error Management of Multicast Packets
  118
  - Packet TEA
    118
  - Multicast Packet Stomping
    118
  - Figure 26: Arbitration Algorithm for Multicast Port
    118
  - Multicast Maximum Latency Timer
    119
  - Silent Discard of Packets
    120
  - Port-Writes and Multicast
    120
- Port Reset
  120
6 Event Notification

121
- Overview
  121
- Event Summary
  122
- Table 13: Tsi578 Events
  122
- Error Rate Thresholds
  126
  - Maintaining Packet Flow
    127
- Error Stopped State Recovery
  128
  - Error Stopped States
    128
  - Link Error Clearing and Recovery
    129
  - Figure 27: Control Symbol Format
    130
- Event Capture
  131
- Table 14: Error Rate Error Events
  132
- Port-Write Notifications
  133
  - Destination ID
    134
  - Payload
    134
  - Servicing Port-Writes
    135
  - Table 15: Port Write Packet Data Payload - Error Reporting
    135
  - Port-Writes and Hot Insertion/Hot Extraction Notification
    136
  - Port-Writes and Multicast
    136
- Interrupt Notifications
  136
7 I C Interface

141
- I 2 C Interface
  141
  - Overview
    141
  - Protocol Overview
    143
  - Block Diagram
    144
  - Figure 29: I 2 C Block Diagram
    145
  - Figure 30: I 2 C Reference Diagram
    146
  - Tsi578 as I 2 C Master
    147
    
    Figure 31: Software-Initiated Master Transactions
    148
    
    Example EEPROM Read and Write
    149
    
    Master Clock Generation
    149
    
    Master Bus Arbitration
    150
    
    Master External Device Addressing
    150
    
    Master Peripheral Addressing
    150
    
    Master Data Transactions
    151
  - Tsi578 as I 2 C Slave
    151
    
    Slave Clock Stretching
    153
    
    Figure 32: Transaction Protocols for Tsi578 as Slave
    153
    
    Slave Device Addressing
    154
    
    Slave Peripheral Addressing
    154
    
    External I C Register Map
    155
    
    Table 17: Externally Visible I 2 C Register Map
    155
    
    Slave Write Data Transactions
    156
    
    Slave Read Data Transactions
    157
    
    Slave Internal Register Accesses
    157
    
    Slave Access Examples
    158
    
    Resetting the I 2 C Slave Interface
    161
  - Mailboxes
    161
    
    Figure 33: I 2 C Mailbox Operation
    162
    
    Incoming Mailbox
    163
    
    Outgoing Mailbox
    163
  - Smbus Support
    163
    
    Unsupported Smbus Features
    164
    
    Smbus Protocol Support
    164
    
    Figure 34: Smbus Protocol Support
    165
    
    Smbus Alert Response Protocol Support
    166
  - Boot Load Sequence
    166
    
    Figure 35: Smbus Alert Response Protocol
    166
    
    Figure 36: Boot Load Sequence
    167
    
    EEPROM Reset Sequence
    168
    
    Idle Detect
    168
    
    Wait for Bus Idle
    168
    
    EEPROM Device Detection
    169
    
    Loading Register Data from EEPROM
    169
    
    Chaining
    170
    
    EEPROM Data Format
    170
    
    Table 18: Format for Boot Loadable EEPROM
    171
    
    Table 19: Sample EEPROM Loading Two Registers
    171
    
    I2C Boot Time
    172
    
    Table 20: Sample EEPROM with Chaining
    172
    
    Accelerating Boot Load
    173
  - Error Handling
    174
  - Table 21: I 2 C Error Handling
    174
  - Interrupt Handling
    176
  - Figure 37: I 2 C Interrupt Generation
    176
  - Events Versus Interrupts
    177
  - Figure 38: I 2 C Event and Interrupt Logic
    178
  - Timeouts
    179
  - Table 22: I 2 C Interrupt to Events Mapping
    179
  - Figure 39: I 2 C Timeout Periods
    182
  - Bus Timing
    183
    
    Figure 40: I 2 C Bus Timing Diagrams
    184
    
    I2C_SD Setup and Hold
    185
    
    Start/Restart Condition Setup and Hold
    185
    
    Stop Condition Setup
    185
    
    I2C_SCLK Nominal and Minimum Periods
    186
    
    Idle Detect Period
    186
8 Performance

187
- Overview
  187
  - Throughput
    187
  - Latency
    187
- Performance Monitoring
  188
  - Figure 41: Latency Illustration
    188
  - Table 23: Performance Monitoring Parameters
    189
  - Throughput
    190
  - Traffic Efficiency
    190
  - Bottleneck Detection
    191
  - Congestion Detection
    191
  - Resetting Performance Registers
    191
- Configuring the Tsi578 for Performance Measurements
  192
- Port-To-Port Performance Characteristics
  193
- Congestion Detection and Management
  196
9 JTAG Interface

201
10 Clocks, Resets and Power-Up Options

205
- Clocks
  205
  - Clocking Architecture
    206
  - Figure 46: Tsi578 Clocking Architecture
    206
  - Serdes Clocks
    207
  - Reference Clocks
    207
  - Table 26: Tsi578 Input Reference Clocks
    207
  - Clock Domains
    208
  - Clock Gating
    208
  - Table 27: Tsi578 Clock Domains
    208
- Resets
  209
  - Device Reset
    209
  - Per-Port Reset
    211
  - Generating a Rapidio Reset Request to a Peer Device
    211
  - JTAG Reset
    211
- Power-Up Options
  212
  - Power-Up Option Signals
    212
  - Table 28: Power-Up Options Signals
    213
  - Default Port Speed
    214
  - Port Power-Up and Power-Down
    214
  - Port Width Override
    214
11 Signals

215
- Overview
  215
- Table 29: Signal Types
  215
- Endian Ordering
  216
- Port Numbering
  216
- Table 30: Tsi578 Port Numbering
  216
- Signal Groupings
  218
- Figure 47: Signal Groupings
  218
- Table 31: Tsi578 Signal Descriptions
  219
- Pinlist and Ballmap
  227
12 Serial Rapidio Registers

229
13 I2C Registers

415
Serial Rapidio Protocol Overview

483
- Protocol
  483
- Packets
  483
  - Control Symbols
    484
- Physical Layer
  484
  - PCS Layer
    484
  - PMA Layer
    484
  - Physical Protocol
    484
  - A.2.1 Control Symbols
    484
  - Table 51: Special Characters and Encoding
    485
  - Table 52: Control Symbol Construction
    486
Clocking

489
- Line Rate Support
  489
  - Table 53: Tsi578 Supported Line Rates
    489
  - Register Requirements Using 125 Mhz S_CLK for a 3.125 Gbps Link Rate
    490
- P_CLK Programming
  493
PRBS Scripts

505
EEPROM Scripts

515
- Script
  515
Index

523

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