IDT PowerSpan II Manual

page of 440

/ 440
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

PowerSpan II

™

User Manual

80A1010_MA001_09

November 2009

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

Summary of Contents for IDT PowerSpan II

Page 1 ® PowerSpan II ™ User Manual 80A1010_MA001_09 November 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: Table Of Contents
PowerSpan II and PowerSpan Differences Summary ........
Page 4 Command Port Errors ............. 126 PowerSpan II User Manual...
Page 5 PowerSpan II Arbiter and System Boot ........
Page 6 Processor Bus and PowerSpan II Register Transfers........
Page 7 PowerSpan II External PLL Decoupling for New Designs ....... . .
Page 8 Contents PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 9 PowerSpan II Configuration Slave Mode Timing........
Page 10 PowerSpan II in CompactPCI Peripheral Slot ........
Page 11 Command Encoding for Transaction Type—PowerSpan II as PCI Target .......
Page 12 PowerSpan II PowerPC Little-Endian PB Register Accesses ........
Page 13 Dual PCI PowerSpan II Power Dissipation ........
Page 14 List of Tables PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 15: About This Document
“Document Conventions” on page 15 • “Revision History” on page 16 Scope The PowerSpan II User Manual discusses the features, configuration requirements, and design architecture of the PowerSpan II. Document Conventions This document uses the following conventions. Non-differential Signal Notation Non-differential signals are either active-low or active-high.
Page 16: Revision History
The formatting of this document has been changed and technical edits have occurred throughout the document. 80A1010_MA001_07, Formal, February 2003 The Dual PCI PowerSpan II has reached production status. This manual represents the production information for the Dual PCI PowerSpan II. PowerSpan II User Manual...
Page 17 About this Document 80A1010_MA001_06, Formal, December 2002 The Single PCI PowerSpan II has reached production status. This manual represents the production information for the Single PCI PowerSpan II. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 18 About this Document PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 19: Functional Overview
(MPC8260), PowerPCTM 7xx, and the Wintegra WinPathTM processors. PowerSpan II is available in either a single PCI or dual PCI variant. PowerSpan II defines a new level of PCI bus switch flexibility. The integrated, non-transparent PCI-to-PCI bridge in the Dual PCI PowerSpan II provides a significant opportunity for designers to reduce component count and increase overall system performance.
Page 20: Powerspan Ii Features
1. Functional Overview Figure 1: PowerSpan II Block Diagram IEEE1149.1 Up to 3 32-bit Address/64-bit Data Boundary External 100 MHz Processor Bus Scan Bus Masters JTAG PowerPC Processor Bus Interface Arbiter Switching Fabric PCI-to-Processor Posted Writes Concurrent Delayed Reads Concurrent DMA Reads/Writes...
Page 21: Powerspan Ii Benefits
• Integrated PCI bus, processor bus arbiters decrease individual component count on boards. • Flexible PCI interfaces enable PowerSpan II to meet many different application requirements. • Integrated, non-transparent PCI-to-PCI bridge connects traffic between the two PCI interfaces. This decreases individual component count and simplifies conventional CompactPCI board architecture.
Page 22: Typical Applications
Ethernet Switches VoIP Gateways MPEG 2 Encoders VPN Equipment PowerSpan II is a very flexible device. The following diagram shows a typical PowerPC system architecture using PowerQUICC II and the Dual PCI PowerSpan II. Figure 2: Typical PowerSpan II Application MPC8260...
Page 23: Powerspan Ii And Powerspan Differences Summary
PowerSpan II: two variants for the Single PCI Information” on PowerSpan II and two variants for the Dual PCI PowerSpan II. Both the Single and Dual PCI page 387 PowerSpan II have packages, signals, and pins that are backwards compatible with the original PowerSpan device.
Page 24: Pci Interface
Target Fast Back to Back Capable (TFBBC) “Register Descriptions” on page 235 The default setting of this bit was changed to 0 in PowerSpan II; the device does not support fast back-to-back transactions. PCI Interface PowerSpan II is available as a Single PCI PowerSpan II or Dual PCI PowerSpan II. A 64-bit PCI Interface is available on both variants;...
Page 25: Primary Pci Interface
PCI devices being configured by the CompactPCI system host. 1.2.2 Primary PCI Interface The PowerSpan II provides extra functionality for one of the PCI interfaces. The PCI Interface assigned extra functionality must be specified as Primary PCI Interface through a power-up option. The Primary PCI Interface functions are: •...
Page 26: Pci Host Bridge
This verification ensures any potential interface issues are identified and resolved by IDT before PowerSpan II customers begin to design their own systems.
Page 27: I2C / Eeprom
1.5.1 EEPROM PowerSpan II registers can be programmed by data in an EEPROM at system reset. This enables board designers to set unique identifiers for their cards on the PCI bus at reset, and set various image parameters and addresses. Configuring PowerSpan II with the EEPROM allows PowerSpan II to boot-up as a Plug and Play compatible device.
Page 28: Figure 4: Concurrent Read Process With Powerspan Ii
This occurs even though a read is in progress for Master 1. PowerSpan II can simultaneously support two reads to the Processor Bus and two reads to the PCI bus. 1.6.1.1...
Page 29: Powerspan Ii's Concurrent Read Applications
When Master 2 is retried in Step 2, no information is latched about the read request. When Master 2 returns for a subsequent read request in Step 4, it is treated by the bridge as the first read request. 1.6.2 PowerSpan II’s Concurrent Read Applications 1.6.2.1 PCI Host Bridge In a PCI host bridge application, all of the PCI masters —...
Page 30 FCC would have a dedicated channel to the PCI bus so they do not have to share resources. PowerSpan II supports this ideal situation through its concurrent reads in a flexible switching architecture. The PCI bridge latches information about the local read as it receives the read request even with reads pending.
Page 31: Pci Interface
“I2O Shell Interface” on page 62 Overview This chapter describes the functionality of the Dual PCI PowerSpan II. The Single PCI PowerSpan II is identified when its functionality or settings differ from the Dual PCI PowerSpan II. The Single PCI PowerSpan II and the Dual PCI PowerSpan II have different characteristics. The features of each device are shown in the following list.
Page 32: Pci Data Width
2. PCI Interface There are two settings available for the Dual PCI PowerSpan II: Primary PCI Interface and Secondary PCI Interface. The Primary PCI Interface adds extra functionality to the PCI Interface that is designated as the Primary PCI Interface. The Secondary PCI Interface has no extra functionality.
Page 33: Table 3: Signals Involved In Pci Data Width Determination
Control and Status Register” on page 324. This feature must only be used in systems where PowerSpan II controls both P1_REQ64# and P1_RST#. In this scenario, PowerSpan II is the Central Resource in the system and can ensure that timing parameters are satisfied. 2.1.2.2...
Page 34: Pci Interface Descriptions
2.1.3 PCI Interface Descriptions The PowerSpan II PCI interfaces are described in terms of its PCI master and PCI target functions. This description is largely independent of PCI-1 versus PCI-2, or the assignment of the Primary PCI Interface functions. Exceptions to these rules are noted as required.
Page 35 This is caused by the fact that PCI-1 to PB Interface transactions and PCI-2 to PB Interface transactions arbitrate in a round robin fashion. When a PowerSpan II decision is required on whether to service a transaction from PCI-1 or PCI-2, writes are available at both even though at one point a write is only available from PCI-2.
Page 36 PCI transaction ordering rules: • PowerSpan II only completes the writes that are destined for the same bus as the initiated read when it is processing a read request. It does not complete writes in both directions before processing a read request.
Page 37: Pci Target Interface
2. PCI Interface PCI Target Interface PowerSpan II participates in a transaction as a PCI target when a PCI master initiates one of the following actions: • attempts to access the alternate PCI Interface • attempts to access processor bus memory •...
Page 38: Table 4: Command Encoding For Transaction Type-Powerspan Ii As Pci Target
2. PCI Interface Table 4 illustrates the command encoding for PowerSpan II as PCI target. Table 4: Command Encoding for Transaction Type—PowerSpan II as PCI Target Px_C/BE#[3:0] Transaction Type PowerSpan II Capable 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read...
Page 39 A 5-bit value, defined in the processor bus Defaults to Write with Flush protocol, is generated on the PB_TT lines during a write on the processor bus. PRKEEP Enables PowerSpan II to keep prefetch read data Disabled over subsequent transactions (see “Reads” on page 41).
Page 40 RD_AMT[2:0]. This can be programmed up to a maximum of 128 bytes. Master-based Decode The PCI Target supports Master-based decode when the PowerSpan II PCI arbiter is enabled (see “Arbitration” on page 137). With Master-based decode enabled, a PCI target image only claims a transaction decoded for its specified physical address space if it originates from a specific PCI master.
Page 41: Data Phase
PowerSpan II does not support delayed write transactions as described in the PCI 2.2 Specification. 2.2.2.2 Reads PowerSpan II supports up to four concurrent reads from external PCI masters. All four reads are treated equally and have the same prefetch capacity, but have individually programmable values. Integrated Device Technology PowerSpan II User Manual www.idt.com...
Page 42: Figure 6: Concurrent Read Waveform
Read line buffers are allocated on a first come, first serve basis. When an external master makes the initial memory request, the PowerSpan II PCI Target captures the PCI address in an available delayed read request latch. This initiates a read on the destination bus specified by the Destination Bus (DEST) bit in the “PCI-1 Target Image x Control Register”...
Page 43: Table 6: Powerspan Ii Pci Target Read Watermarks
2. PCI Interface In order to program PowerSpan II to complete 4 byte reads on the PCI bus, both the MEM_IO bit and the MODE bit must be set to 1 in the PCI x Target Image x Control register.
Page 44: Termination Phase
“PCI-1 Control and Status Register.” on page 251 is set when PowerSpan II encounters a parity error as a PCI target on any transaction. PowerSpan II records an error condition when a parity error occurs (see “Error Handling” on page 157).
Page 45 Px_TRDY# is high — by the PCI Target because it cannot currently process the transaction. Retry means the transaction is terminated after the address phase without any data transfer. PowerSpan II retries read requests while it fetches data from the destination bus. Any attempt by a PCI master to complete the memory read transaction is retried by the PCI target until at least an 8-byte quantity is available in the line buffer.
Page 46: Pci Master Interface
2. PCI Interface PCI Master Interface In order for PowerSpan II to be a PCI master in a transaction the Bus Master (BM) bit, in the “PCI-1 Control and Status Register.” on page 251, must be set. With this bit set, PowerSpan II is PCI Master in a transaction in the following instances: •...
Page 47: Arbitration Phase: Arbitration For The Pci Bus
Arbitration Phase: Arbitration for the PCI Bus PowerSpan II issues a bus request on the PCI bus when it requires access to the PCI bus. When the PowerSpan II PCI arbiter is active, this request is internal. When it is not enabled the request appears externally (see “PCI Interface Arbitration”...
Page 48: Table 7: Command Encoding For Transaction Type (Powerspan Ii As Pci Master)
Register.” on page 251) A new request for access to the bus is generated by the PowerSpan II PCI Master when it requires access to the PCI bus to service a request from the Processor Bus Interface or the other PCI interface (Py).
Page 49 “Processor Bus Slave Image x Control Register” on page 287). When address translation is enabled — by setting the TA_EN bit in PCI Target or PB Slave Image Control Register — PowerSpan II produces the PCI address using the following inputs: •...
Page 50: Data Phase
“Processor Bus Miscellaneous Control and Status Register” on page 304. When the Dual PCI PowerSpan II is used, incoming PCI writes are executed as similar writes on the alternate PCI interface. For example, a 64-byte burst write to memory space from the PCI-1bus is executed as a 64-byte burst write to the memory space on the PCI-2 bus, provided the target on PCI-2 does not disconnect.
Page 51: Table 9: Powerspan Ii Pci Master Read Commands
“PCI-1 Control and Status Register.” on page 251 is set if the PERESP bit is enabled and either PowerSpan II is the master of the transaction where it asserts PERR#, or the addressed target asserts PERR#. If the transfer originated from the Processor Interface, then PowerSpan II sets the MDP_D bit and the Px_PB_ERR_EN bit in the “Interrupt Enable...
Page 52: Terminations
Although there may be a fatal error for the initiating application, the transaction completes gracefully, ensuring normal PCI operation for other PCI resources. PowerSpan II sets R_TA in Px_CSR and records an error condition in the event of a Target-abort (see “Error Handling”...
Page 53: Compactpci Hot Swap Silicon Support
The CompactPCI Hot Swap Specification defines a switch located in the ejector handle that indicates to PowerSpan II if the ejector handle is open or closed. A low value on ES input indicates that the ejector latch is open. A high value on ES indicates that the ejector latch is closed and is in operation mode.
Page 54: Compactpci Hot Swap Card Insertion And Extraction
2. PCI Interface During the negation of HEALTHY#, PowerSpan II disables its output and bidirectional pins ( except for LED#) to avoid applying power to non-powered components on the card. The signals connected between PowerSpan II and these non-powered components result in floating pins on PowerSpan II.
Page 55: Figure 7: Powerspan Ii In A Compactpci Adapter Card
2. PCI Interface Figure 7: PowerSpan II in a CompactPCI Adapter Card Ensure that PB_CLK and P2_CLK are within specification before the release of back-end power-up reset. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 56: Hot Swap Insertion Process
PowerSpan II output pins disabled, input pins inhibited — Card’s PCI signals pre-charge 2. Medium pins contact PCI backplane signals: — PowerSpan II’s Primary PCI Interface, in this case PCI-1, connects to the PCI pins on the backplane — PowerSpan II P1_CLK is within specification 3.
Page 57 — Setting INS bit in the HS_CSR register — Asserting ENUM# 7. PowerSpan II is now able to accept Configuration cycles on PCI-1 from the CompactPCI Host Since Px_LOCKOUT bit in the “PCI-1 Miscellaneous Control and Status Register” on page...
Page 58: Hot Swap Extraction Process
— Reads the P1_HS_CSR of each agent to determine which card is being extracted — Clears the PowerSpan II EXT bit. This causes the negation of ENUM# and arms the INS bit — Places the card in a software dormant state —...
Page 59: Figure 9: Hot Swap Extraction
Physical Connection After the status LED# is illuminated by the host, the operator can close the ejector switch, rather than extracting the card. If the closure or the extraction occurs, a PowerSpan II register reload from EEPROM does not occur.
Page 60: Vital Product Data
Only and the remaining 128 bytes are VPD-Read/Write. When VPD_CS = 0b000, VPD addresses are translated upward by 64 bytes before being presented to the EEPROM. PowerSpan II can be programmed with an alternate chip select for VPD access if more than the 192 accessible bytes is required. Programming of the I C chip select is done in the PowerSpan II “Miscellaneous Control and Status Register”...
Page 61: Writing Vpd Data
267. The F bit must be set to 0 to indicate a VPD read access. PowerSpan II sets the F bit to 1 when it completes reading the 4 bytes from the EEPROM. The F bit must be polled to determine when the read is complete. Byte 0 (bits 7 through 0) of the “PCI-1...
Page 62: I2O Shell Interface
64-bits wide for PCI-1, but limited to 32-bit wide for PCI-2. PowerSpan II does not support posting of more than one write transaction to the Inbound or Outbound Queue. Attempts to write to the Inbound or Outbound Queue are retried until the currently active write completes on the Processor Bus Interface.
Page 63: Iop Functionality
2. PCI Interface 2.6.2 IOP Functionality A number of configuration steps are required before PowerSpan II and the embedded processor bus are enabled to provide IOP functionality. The following example assumes PCI-1 is the Primary PCI Interface. The steps required to implement IOP functionality are listed below.
Page 64: Messaging Interface
O system through a memory-based system, such as PCI, which has no inherent message passing capability. An IOP which is connected to a memory-based system is said to be locally attached. The PowerSpan II implements four I O defined memory mapped registers on PCI to enable the physical and logical connection of the IOP to the system.
Page 65 The Outbound Queue Register is the messaging interface used by the local IOP to post messages to the Host. The I O Outbound Queue Register Interface is located at offset 0x044 of the PowerSpan II PCI O target image in PCI memory space. The Outbound Queue has a Free List FIFO and a Post List FIFO, both of which reside in the IOP local memory.
Page 66 Figure 3.4. The solid lines indicate pointers which are maintained and incremented by the PowerSpan II. The dashed lines indicate pointers which are incremented by the IOP. The IOP writes one to increment to PowerSpan II increment register associated with the pointer.
Page 67: Figure 10: Powerspan Ii I2O Message Passing
2. PCI Interface Figure 10: PowerSpan II I O Message Passing Bottom Pointer Top Pointer Inbound Queue Inbound (0x040) Free List FIFO Bottom Pointer Top Pointer Local Inbound Processor (IOP) post List FIFO Inbound Queue Outbound Queue Top Pointer Outbound Queue...
Page 68: Inbound Messages
The Inbound Free and Post List FIFOs are implemented as circular queues using Bottom and Top pointers. The PowerSpan II implements the Bottom and Top pointers for the Inbound Free List FIFO and the Inbound Post List FIFO. The FIFOs reside in the local memory. The Inbound posted messages also reside in local processor memory.
Page 69: Outbound Messages
FIFO. The IOP, having obtained a Host MFA, is then free to write a message through the PowerSpan II to the Host MF at the Host memory address specified by the MFA. Once the message is transferred, the IOP writes the MFA to the Outbound Post List FIFO at the address pointed to by the Outbound Post List Top pointer maintained by PowerSpan II.
Page 70: Pull Capability
O target image on PCI The XMFA is processed by the PowerSpan II in the same way as a normal MFA posted to the local IOP by the Host or external IOP. The IOP can determine if the XMFA is posted using the Pull Capability and to pull the message from the system memory.
Page 71 FIFO resets the FIFO index to the base address and this time through write the P bit to 0. This allows the Host to track the progress of the local IOP in returning XMFAs. Figure 11 illustrates the following steps in PowerSpan II I 0 pull capability: 1. Host reads XMFA from Host Free List 2.
Page 72: Figure 11: Powerspan Ii I2O Pull Capability
2. PCI Interface Figure 11: PowerSpan II I O Pull Capability Bottom Pointer Top Pointer Inbound Queue Inbound Step 3 (0x040) Free List FIFO Step 6 XMFA Step 5 Step 4 Bottom Pointer Top Pointer Local Inbound Processor (IOP) Post List...
Page 73: Outbound Option
Register by writing to the IOP Outbound Index Increment Register. The PowerSpan II IOP Outbound Index Register is initialized by the IOP with a value received along with the Host Outbound Post List FIFO Size through an “IOP Message Outbound Extensions” message from the Host.
Page 74 The Host will post empty MFAs back to the IOP by writing to the PowerSpan II’s Outbound Queue Register (0x044), with the C bit set to zero. PowerSpan II services the written MFA the same as a normal Outbound MFA being returned to the IOP.
Page 75: Figure 12: Powerspan Ii I2O Outbound Capability
2. PCI Interface Figure 12: PowerSpan II I O Outbound Capability XMFA Step 3 XMFA XMFA Step 4 Step 5 IOP Outbound Index Host Host Outbound Index Host Outbound Processor Post List FIFO Host Platform Outbound Queue Top Pointer XMFA...
Page 76: I2O Standard Registers
0 Inbound Message Frames The I O Shell Interface is located in the first 4 Kbytes of the PowerSpan II I O target image. The I Inbound Message Frames occupies offsets above the 4 Kbyte point of the PowerSpan II I O target image.
Page 77 PCI to offset 0x30 from Px_BSI2O is destined for OPL_IS. When the I 0 messaging unit in PowerSpan II is not enabled, the OPL_IS register is not visible to read or write access. The register essentially disappears from all PowerSpan II memory maps.
Page 78 PCI to offset 034h from Px_BSI2O is destined for OPL_IM. When the I 0 messaging unit in PowerSpan II is not enabled, the OPL_IM register is not visible to read or write access. The register essentially disappears from all PowerSpan II memory maps.
Page 79 When the I 0 Interface in PowerSpan II is not enabled, the IN_Q register is not visible to read or write access. The register essentially disappears from all PowerSpan II memory maps. Register Name: IN_Q...
Page 80 When the I 0 Interface in PowerSpan II is not enabled, the OUT_Q register is not visible to read or write access. The register essentially disappears from all PowerSpan II memory maps. Register Name: OUT_Q...
Page 81 4 Kbytes of the PCI I O target image map. When the I 0 Interface in PowerSpan II is not enabled, the HOST_OI register is not visible to read or write access. The register essentially disappears from all PowerSpan II memory maps. Register Name: HOST_OI...
Page 82 2. PCI Interface PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 83: Processor Bus Interface
Processor Bus Interface This chapter describes the functionality of the Processor Bus Interface. Both the Single PCI PowerSpan II and Dual PCI PowerSpan II have a Processor Bus Interface. The following topics are discussed: • “Overview” on page 83 •...
Page 84: Pb Bus Interface Descriptions
Coherency Attribute (M) set to zero. PowerSpan II performs PCI read prefetches. These reads can be cached in an internal queueing memory within PowerSpan II — if PRKEEP is set to 1. When a write is performed to a prefetched address, a subsequent read yields stale data.
Page 85: Address Phase
Transaction decoding on the PB Slave operates in both normal decode mode and Master-based decode mode. When PowerSpan II is in normal decode mode, each PB slave monitors the Processor Bus Address (PB_A[]). When the address falls into one of the programmed windows, and the Transfer Type (PB_TT[]) is supported, PowerSpan II claims the address tenure.
Page 86: Table 11: Programming Model For Pb Slave Image Control Register
PB memory management supports a variety of memory/cache access attributes: write through (W), caching-inhibited (I), and memory coherency (M). Although PowerSpan II does not decode these attributes — external pins PB_GBL_ and PB_CI_ are output only— specific guidelines must be followed to ensure correct system operation. These...
Page 87: Table 13: Powerspan Ii Pb Slave Transfer Types
3. Processor Bus Interface Register and PCI I/O space accesses requires I to be set to 1 because PowerSpan II does not accept burst transactions to these resources. Master-based Decode Mode The PB Slave Interface supports Master-based decode mode when the internal PowerSpan II processor bus arbiter is enabled (see “Processor Bus Arbitration”...
Page 88 Write with flush atomic Because PowerSpan II does not have a cache, all read and write transfer types are treated the same. For example, a Read with Intent to Modify command (PB_TT= 01110) is handled the same way as a Read Atomic command (PB_TT= 11010).
Page 89 When ARTRY_EN has a value of 1, the PB Slave can assert PB_ARTRY_. The default setting is 0 (ARTRY_EN is disabled). The PB Interface has higher performance if the ARTRY_EN bit is enabled. PowerSpan II’s PB Master or another external master can gain access to the bus when PowerSpan II cannot assert PB_TA.
Page 90: Table 14: Translation Address Mapping
01001 31:20 0:11 01000 31:19 0:12 00111 512k 31:18 0:13 00110 256k 31:17 0:14 00101 128k 31:16 0:15 00100 31:15 0:16 00011 31:14 0:17 00010 31:13 0:18 00001 31:12 0:19 00000 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 91: Table 15: Powerspan Ii Pb Address Parity Assignments
PowerSpan II, and PowerSpan II has either or both address and data parity enabled, then PowerSpan II reports parity errors on the transaction. To enable or disable address parity in PowerSpan II, set the Address Parity Enable (AP_EN) bit in the “Processor Bus Miscellaneous Control and Status Register” on page 304.
Page 92: Data Phase
Table 17 lists the size and alignment transactions less than or equal to 8 bytes. PowerSpan II register accesses are limited to 4 bytes or less. The PowerSpan II port size is 64-bit. PowerSpan II User Manual...
Page 93: Table 17: Powerspan Ii Processor Bus Single Beat Data Transfers
3. Processor Bus Interface Table 17: PowerSpan II Processor Bus Single Beat Data Transfers Size TSIZ[0:3] A[29:31] Data Bus Byte Lanes Byte 0001 0001 0001 0001 0001 0001 0001 0001 Half word 0010 0010 0010 0010 0010 0010 0010 Tri-byte...
Page 94 “Processor Bus Miscellaneous Control and Status Register” on page 304. Any misaligned transaction between PowerSpan II and the PowerPC 7400 that is a single word (32-bit) or less must be within a single word aligned boundary. Any transfer greater than a single word must start or end on a word boundary.
Page 95 — The master repeats the transaction with the same parameters used for the initial request Any attempt by a processor bus master to complete the read transaction is retried by the PowerSpan II PB Slave until the following byte quantities are available in the line buffer: •...
Page 96: Table 18: Read Amount Settings
3. Processor Bus Interface In order to program PowerSpan II to complete 4 byte reads on the PB bus, both the MEM_IO bit and the MODE bit must be set to 1 in the Processor Bus Slave Image x Control register.
Page 97: Table 19: Powerspan Ii Pb Data Parity Assignments
Parity generation and checking is provided for each byte of the data bus and for each data beat of the data tenure. Data parity bit assignments are as defined in Table 19. Table 19: PowerSpan II PB Data Parity Assignments Data Bus...
Page 98: Terminations
PowerSpan II, and PowerSpan II has either or both address and data parity enabled, then PowerSpan II reports parity errors on the transaction. To enable or disable address parity in PowerSpan II, set the Address Parity Enable (AP_EN) bit in the “Processor Bus Slave Image x Control Register” on page 287.
Page 99 PCI Configuration or IACK commands (see “Configuration and IACK Cycle Generation” on page 246) PowerSpan II also asserts PB_TEA_ if a read from PCI generates a Master-Abort or Target-Abort. The assertion PB_TEA_ is enabled or disabled with the TEA Enable (TEA_EN) bit in the “Processor Bus Miscellaneous Control and Status Register”...
Page 100: Pb Master Interface
The PB Master negates PB_ABB_ for at least one clock after Address Acknowledge (PB_AACK_) has been asserted by the slave. This is true even if the arbiter parked the bus on PowerSpan II. For example, Figure 13 on page 105 the bus is parked at the PowerSpan II (PB_BG[1]_ is asserted throughout), PB_ABB_ is negated the first positive clock edge after sampling PB_AACK_.
Page 101 This guarantees the snooping master that retried the cycle an opportunity to request and be granted the bus before the PowerSpan II PB Master can restart its transaction. Once the bus is re-acquired, the PB Master restarts the transaction.
Page 102: Table 20: Default Powerspan Ii Pb Master Transfer Type
(see “PCI-1 Target Image x Control Register” on page 268. When address translation is enabled — TA_EN bit is set in the PCI target image — PowerSpan II produces the processor bus address using three inputs: • the incoming address from the source bus •...
Page 103: Data Phase
The PB Master negates PB_DBB_ for at least one clock after the final data termination signal is asserted by the slave. The PowerSpan II PB Master derives equivalent Data Bus Busy information from PB control signals. This allows the PowerSpan II processor bus arbiter to operate in processor bus environments that do not implement DBB.
Page 104: Table 22: Powerspan Ii Pb Transfer Sizes
The PB Master can generate a super-set of the data transfer sizes supported by the embedded PowerPC family. The user can disable certain data transfer sizes that are unique to the PowerQUICC II. All data transfer sizes supported by the PowerSpan II PB master are illustrated in Table 22 below.
Page 105: Figure 13: Pb Master Interface Burst Read
PB_TT[0:4] PB_AACK PB_ARTRY_ PB_DBG_IN_ PB_DBB PB_D[0:63] PB_DP[0:7] PB_DVAL_ PB_TA_ PB_TEA_ The following figures, Figure 15 Figure 16, illustrate single cycle read and single cycle write transfers on the PB Master Interface. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 106: Figure 15: Pb Master Interface Single Cycle Read
Embedded processor bus transfer sizes and alignments are supported by the PowerSpan II PB Master for transaction accesses. The PB master creates the necessary sequence of transactions from a set of processor bus data size and alignment options. The size and alignment...
Page 107: Table 23: 64-Bit Pb Data Bus Byte Lane Definitions
D[0:7] DH[0:7] H_DATA[63:56] PB_D[8:15] D[8:15] DH[8:15] H_DATA[55:48] PB_D[16:23] D[16:23] DH[16:23] H_DATA[47:40] PB_D[24:31] D[24:31] DH[24:31] H_DATA[39:32] PB_D[32:39] D[32:39] DL[0:7] H_DATA[31:24] PB_D[40:47] D[40:47] DL[8:15] H_DATA[23:16] PB_D[48:55] D[48:55] DL[16:23] H_DATA[15:8] PB_D[56:63] D[56:63] DL[24:31] H_DATA[7:0] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 108: Table 24: Powerspan Ii Processor Bus Single Beat Data Transfers
8-bytes. The shaded table cells PowerPC 7400 show transactions that support the processor. Table 24: PowerSpan II Processor Bus Single Beat Data Transfers Size TSIZ[0:3] A[29:31] Data Bus Byte Lanes...
Page 109 “Processor Bus Miscellaneous Control and Status Register” on page 304. Any misaligned transaction between PowerSpan II and the PowerPC 7400 that is a single word (32-bit) or less must be within a single word aligned boundary. Any transfer greater than a single word must start or end on a word boundary.
Page 110: Table 25: Powerspan Ii Pb Data Parity Assignments
3.4.2.4 Cache Line Size The PowerPC processors supported by PowerSpan II implement a 32-byte cache line size (8 words). Cache wrap bursts are not generated because the PB master starts a burst transaction at a 32-byte aligned address. For a transaction that is not 32-byte aligned, the PB master utilizes one or more single beat or extended transaction size, to align to the cache line boundary, before generating the required burst transaction or transactions.
Page 111: Terminations
“Processor Bus Miscellaneous Control and Status Register” on page 304). “Error Handling” on page 157 “Interrupt Handling” on page 145 for a full description of error logging support and associated interrupt mapping options. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 112 3. Processor Bus Interface PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 113: Dma
PowerSpan II has four identical Direct Memory Access (DMA) channels for independent data transfer between the three ports of the Dual PCI PowerSpan II: Processor Bus Interface (PB), PCI Interface 1 (PCI-1) and PCI Interface 2 (PCI-2). The programming and operation of the four DMAs are the same.
Page 114: Dma Register Description
The DMA registers are the same for each DMA channel. DMA registers are described in Table 26. The registers for DMA1 begin at offset 0x300 and their organization in PowerSpan II register space is described in “Register Descriptions” on page 235.
Page 115: Transfer Control Register
DMA Addresses and Retries If a PowerSpan II DMA transaction is retried enough times the its retry counter may expire. When the retry timer expires, the DMA transaction does not try to restart the transaction at the original address; it jumps the address.
Page 116: General Dma Control And Status
Write 1 to clear P2_ERR A status bit indicating an error has occurred on Clear PCI-2. Disregard this bit with the Single PCI PowerSpan II. Write 1 to clear PB_ERR A status bit indicating an error has occurred on the processor Clear bus.
Page 117: Processor Bus Transfer Attributes
Enables an interrupt if an error occurs on PCI-1. Disabled P2_ERR_EN Enables an interrupt if an error occurs on PCI-2. Do not Disabled program this bit if using the Single PCI PowerSpan II PB_ERR_EN Enables an interrupt if an error occurs on the processor bus. Disabled STOP_EN...
Page 118: Direct Mode Dma Operation
In Direct mode, the contents for all of a DMA channel registers are directly programmed into PowerSpan II before every DMA operation (see Table 26). This results in higher software overhead than in Linked-List mode since PowerSpan II register accesses are required for every DMA block transfer. 4.3.1 Initializing a Direct Mode Operation The GO bit in the “DMA x General Control and Status Register”...
Page 119: Figure 17: Direct Mode Dma Transfers
Figure 17: Direct Mode DMA Transfers Program: Source and destination addresses Transfer size and addresses Ensure status bits are clear Set GO bit Await termination of DMA Normal Handle error Termination? More transfers required? Done Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 120: Linked-List Mode Dma Operation
Linked-List Mode DMA Operation In Linked-List (scatter-gather) mode, PowerSpan II steps through a linked series of command packets in external memory. The DMA is configured with the starting address of this list and independently reads command packets and executes the transfers specified.
Page 121: Table 29: Programming Model For The Command Packet Contents
If the command packets are resident in processor bus memory, the byte ordering is big-endian. command packets can reside on any one of the three PowerSpan II interfaces. The contents of a command packet are described, with the associated DMA register, in...
Page 122: Initializing A Linked-List Mode Transfer
A Linked-List mode DMA transfer is configured using the following steps: 1. Set-up the command packet linked-list in memory accessible to any one of the PowerSpan II’s three ports. The command packet port selection is independent of the port selected as the source or destination port.
Page 123: Figure 19: Sequence Of Operations In A Linked-List Transfer
If the Linked-List mode is started with a non-zero byte count in the DMA Transfer Control Register, a Direct mode DMA transfer is initiated by PowerSpan II to clear the remaining byte count value. Once that Direct mode transfer is complete, the DMA then processes the linked-list pointed to in the DMA Command Packet Pointer Register.
Page 124: Dma Interrupts
Linked-List mode), and the GO bit (to re-activate the DMA). DMA Interrupts The PowerSpan II DMA supports a number of interrupt sources for each channel. Individual enable and status bits exist for each source. The status and enable bits are contained in the “DMA x General...
Page 125: Pci Error Bits
Maximum retry limit is reached 4.6.2 Processor Bus Error Bit The error bit for the processor bus is set if the PowerSpan II PB Master encounters one of the following conditions while servicing a DMA channel: • Assertion of PB_TEA_ •...
Page 126: Command Port Errors
When an error occurs on the command port the appropriate DMAx_GCSR error bit is set. The DMA channel registers are not updated with command packet data. Each PowerSpan II external port has error log registers that provides additional diagnostic information to assist in error recovery. These error log registers indicate when multiple errors occur due to the pipelined nature of DMA channel requests.
Page 127: I2C/Eeprom
C bus compatible interface which supports up to eight I C slave devices. This interface is primarily used by PowerSpan II for the initialization of registers and for reading and writing PCI Vital Product Data (VPD). However, PowerSpan II also provides a mechanism for processor bus and PCI masters to access the I C devices.
Page 128: Power-Up Configuration
When a EEPROM is used in a system, the EEPROM device responds and a number of PowerSpan II register bits are loaded from the external device and the ELOAD bit is set. During this loading process, all accesses to PowerSpan II’s external interfaces are retried.
Page 129 P1_SID[SVID[15:8]] PCI-1 Subsystem vendor ID bits 15-8 0x0A P1_SID[SVID[7:0]] PCI-1 Subsystem vendor ID bits 7-0 0x0B PowerSpan II Reserved P1_MISC1[INT_PIN[0]] PCI-1 Interrupt pin bit 0 P2_MISC1[INT_PIN[0]] PCI-2 Interrupt pin bit 0 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 130 PowerSpan II Reserved 0x10 MISC_CSR[P1_LOCKOUT] PCI-1 Lockout MISC_CSR[P2_LOCKOUT] PCI-2 Lockout PowerSpan II Reserved MISC_CSR[PCI_ARB_CFG] PCI Arbiter Configuration Complete MISC_CSR[PCI_M7] PCI Arbiter Master 7 MISC_CSR[PCI_M6] PCI Arbiter Master 6 MISC_CSR[PCI_M5] PCI Arbiter Master 5 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 131 PCI-2 Target image 3 prefetch indicator 0x14 P2_SID[SID[15:8]] PCI-2 Subsystem ID bits 15-8 0x15 P2_SID[SID[7:0]] PCI-2 Subsystem ID bits 7-0 0x16 P2_SID[SVID[15:8]] PCI-2 Subsystem vendor ID bits 15-8 0x17 P2_SID[SVID[7:0]] PCI-2 Subsystem vendor ID bits 7-0 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 132 0x27 P1_CLASS[RID] PCI-1 Revision ID 0x28 PowerSpan II Reserved PB_SI0_CTL[TA_EN] PB Slave image 0 translation enable PB_SI0_CTL[MD_EN] PB Slave image 0 Master decode enable PB_SI0_CTL[BS] PB Slave image 0 block size PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 133 PB Slave register image base address bits 23-16 0x33 PB_REG_ADDR[15:12] PB Slave register image base address bits 15-12 PowerSpan II Reserved PB_REG_ADDR[END] PB Slave register image endian conversion 0x34 P2_ID[DID[15:8]] PCI-2 Device ID bits 15-8 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 134 EEPROM is read to determine the loading sequence desired. All bytes for the selected load option are read from the EEPROM, but only a subset of PowerSpan II registers are updated. This subset is defined by the external reset pin that initiated the reset sequence. Only those register bits affected by the active reset pin(s) are updated with EEPROM contents.
Page 135: Bus Master I 2 C Transactions
5. I2C/EEPROM Bus Master I C Transactions C master reads and writes can be performed from any one of the PowerSpan II’s three interfaces — PB, PCI-1 or PCI-2. These I C transactions are generated by accessing the “I2C/EEPROM Interface Control and Status Register”...
Page 136 If VPD is located in the first EEPROM, the first byte is located at offset 0x40. On every VPD transfer, PowerSpan II adds the offset 0x40 to the address in the P1_VPDC or P2_VPDC register. If VPD is not located in the first EEPROM, then the address in the P1_VPDC or P2_VPDC register is used directly as the 8 bit EEPROM address.
Page 137: Arbitration
PCI Interface Arbitration Each PowerSpan II PCI Interface supports a PCI central arbiter. Each arbiter has dedicated support for the PowerSpan II PCI Master — with internal request and grant signaling and up to four external PCI masters. PowerSpan II provides external pins to support three additional external PCI masters —...
Page 138: Arbitration Levels
6.2.1 Arbitration Levels The PowerSpan II PCI arbiter implements a fairness algorithm in order to prevent deadlocks. There are two priority levels signed to the PCI master agents. Fairness is defined by the PCI 2.2 Specification as an algorithm that grants all potential PCI masters access to the bus, independent of other requests.
Page 139 A master that does not respond to the Px_GNT# signal in 16 clocks is considered a non-functioning master by the PowerSpan II PCIx Arbiter when the Status enable (STATUS_EN) bit is set to 1 in the “PCI-1 Bus Arbiter Control Register” on page 284.
Page 140: Figure 21: Arbitration Algorithm
Level 0 * A, B, C, X Master Y Each PowerSpan II PCI arbiter is programmable with the corresponding arbiter control register (see “PCI-1 Bus Arbiter Control Register” on page 284) and enabled through power-up option PCI x Arbiter enable (PWRUP_Px_ARB_EN) (see “Resets, Clocks and Power-up Options”...
Page 141: Bus Parking
Bus Parking on a Non-functioning Master It is possible for PowerSpan II to park the bus on a master that is considered non-functioning or to park the bus on the last master that has a status that has changed to non-functioning by the STATUS bit is set to 1 in the “PCI-1 Bus Arbiter Control Register”...
Page 142: Address Bus Arbitration
An example application for this feature is some L2 caches hold the BR_ signal after the TS_ signal starts. The PowerSpan II arbiter could see this as a valid request and give the bus to the L2 cache when the bus was not requested. This bit delays when the PB arbiter samples the signal so a false bus request is not granted.
Page 143: Address Only Cycles
Some processors, specifically the PowerPC 7400, must have the data bus grant qualified by the arbiter before it is issued to the master. PowerSpan II, by default, does not qualify the data bus grant by the PowerSpan II PB Arbiter and requires that the requesting master qualify bus grants before beginning an data tenure.
Page 144: Table 32: Mx_En Default State
P2_LOCKOUT bits in the MISC_CSR register. Setting the Px_LOCKOUT bits means any configuration cycles for PowerSpan II on the PCI bus are retried until the Px_LOCKOUT bits are cleared from the processor bus or the EEPROM. When PCI_BOOT is set to 1 (boot is from PCI) the...
Page 145: Interrupt Handling
• “Doorbells” on page 155 Overview PowerSpan II handles interrupts both from normal device operation and from exceptions. These interrupts are programmed through certain register settings and are signaled through both input and output signal pins. The following sections describes PowerSpan II interrupt handling.
Page 146: Interrupts From Transaction Exceptions
7.2.2 Interrupts from Transaction Exceptions Bus transaction exceptions can occur on any one of the PowerSpan II interfaces — PCI-1, PCI-2 or Processor Bus (PB) — because of bus errors, address parity errors, or data parity errors. When an error occurs, PowerSpan II tracks the direction of the transaction through the interrupt enabling and status function.
Page 147: Interrupt Registers
7. Interrupt Handling Interrupt Registers PowerSpan II interrupt status and enabling, as well as message passing through mailboxes and doorbells are controlled by the interrupt registers. Table 33 provides a description of PowerSpan II registers controlling these functions. Table 33: Interrupt Register Description...
Page 148: Interrupt Status
Set when a doorbell register is written to in the corresponding IER0 bit. Write 1 to Clear MBOXx Set when there is a write to a mailbox. Write 1 to Clear PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 149: Table 35: Register Description For Interrupt Status Register 1
The PowerSpan II PB Master Interface has detected more than the maximum allowable retries. Write 1 to Clear PB_x_ERR The PowerSpan II PB Interface asserted (as slave) or received (as master) PB_TEA_. The PB slave detects illegal conditions, while the PB master Write 1 receives PB_TEA_. to Clear PB_A_PAR An address parity error was detected on the PB.
Page 150: Interrupt Enable
For errors detected by a target/slave, PowerSpan II has separate reporting mechanisms for each destination port. For example, if the PowerSpan II PB slave detects a data parity error on a transaction destined for an agent connected to the PCI-1 external interface, the P1_PB_A_PAR bit in the ISR1 register is set.
Page 151: Table 37: Register Description For Interrupt Enable Register 1
For errors detected by a target/slave, PowerSpan II has separate reporting mechanisms for each destination port. For example, if the PowerSpan II PB slave detects a data parity error on a transaction destined for an agent connected to the PCI-1 external interface, the P1_PB_A_PAR bit in the ISR1 register is set.
Page 152: Interrupt Mapping
7. Interrupt Handling 7.3.3 Interrupt Mapping The following registers contain mapping bits for PowerSpan II interrupt sources: • IMR_MBOX (mailbox sources) • IMR_DB (doorbell sources) • IMR_DMA (DMA channel sources) • IMR_HW (external pin sources) • IMR_P1 (PCI-1 sources) •...
Page 153: Interrupt Pins
• Px_INTA = user defined, in the ID register. Px_INTA# is used as general purpose pin. PowerSpan II provides an EEPROM load feature to automatically control the interrupt capabilities of PCI-1 and PCI-2 (see “I2C/EEPROM” on page 127).
Page 154: Dma Interrupts
7. Interrupt Handling DMA Interrupts The PowerSpan II DMA supports a number of interrupt sources for each channel. Individual enable and status bits exist for each source. The status and enable bits are contained in the “DMA x General Control and Status Register” on page...
Page 155: Doorbells
“Interrupt Enable Register 0” on page 332. The Doorbell interrupt is cleared by writing a 1 to the corresponding Doorbell x (DBx) bit in the “Interrupt Status Register 0” on page 327. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 156 7. Interrupt Handling PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 157: Error Handling
“DMA Errors” on page 166 Overview PowerSpan II has error detection, error reporting and error recovery mechanisms for each of the major interfaces — Processor Bus (PB), PCI-1 and PCI-2. The master and target/slave of each interface provides error detection for transactions where they participate.
Page 158: Pb Interface Errors
For errors detected by a target/slave, PowerSpan II provides separate reporting tools for each destination port. For example, if the PowerSpan II PB slave detects a data parity error on a transaction destined for an agent connected to the PCI-1 external interface, the PB_P1_D_PAR bit in the ISR1 is set.
Page 159: Table 40: Pb Interface Errors
Unaligned access in PPC IO, IACK) little-endian mode, Transaction Size > 4 bytes or burst Propagation of PCI-1 Read PB_TEA if error from TEA_EN=1 destination master PCI-2 Read PB_TEA if TEA_EN=1 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 160 Transfer Size, PB_TSIZ, indicates a transfer greater than 4 bytes When a PowerSpan II PCI master is performing a read and encounters a Target-Abort, or generates a Master-Abort, an error indication is latched. When the Address Retry Enable (ARTRY_EN) bit, in the “Processor Bus Miscellaneous Control and Status Register”...
Page 161 5. Fix the configuration issue that caused the error. 6. Retry the transaction that caused the error. The flow of transactions through the PowerSpan II interfaces is independent of error status bits in ISR1 and Error Status bit in the “Processor Bus Error Control and Status Register”...
Page 162: Pci Interface Errors
Table 41 on page 163 itemizes the error cases detected and reported by the Px master and the Px target. Error logging in Px_ERRCS and Px_AERR is triggered for each of these error cases PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 163: Table 41: Pci Interface Errors
External Py agent Read/Write R_TA in the Px_CSR register, Px_Py_ERR in the ISR1 register Px-to-Py DMA Py-to-Px DMA DMA Px Linked-List R_TA in the Px_CSR register, Px_Px_ERR in the ISR1 register Px-to-Px DMA Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 164 Target-Abort (S_TA) bit in the “PCI-1 Control and Status Register.” on page 251. In this case the PowerSpan II PB Master or Py master and the Px target reports the error. The shaded row from the Px master section of Table 41...
Page 165 5. Clear the error bits in Px_CSR. 6. Fix the configuration issue that caused the error. 7. Retry the transaction that caused the error. The flow of transactions through PowerSpan II is independent of error status bits in “Interrupt Status Register 1” on page 329, error status bits in “PCI-1 Control and Status Register.”...
Page 166: Dma Errors
PCI-1 Bus Error (P1_ERR) in the DMAx_GCSR register • PCI-2 Bus Error (P2_ERR) in the DMAx_GCSR register These status bits can be used to cause the assertion of a PowerSpan II interrupt pin according to “Interrupt Handling” on page 145.
Page 167: Resets, Clocks And Power-Up Options
“Power-Up Options” on page 171 Reset PowerSpan II has several inputs to its reset logic. It also has the capability of propagating the reset to the other side of the bus. PowerSpan II has reset capabilities for PCI Host, Adapter and Hot Swap applications 9.1.1...
Page 168: Table 43: Reset Direction Control Pins
Typically, the bus reset pin on the bus closest to the system host must be configured as an input. 9.1.1.2 Reset Response The assertion of an external reset pin elicits a specific response from PowerSpan II. Table 44 defines how various PowerSpan II resources are affected by active reset pins.
Page 169 PowerSpan II bus interface is in a reset state. However, the reset does not propagate to other PowerSpan II busses when the reset pin is configured as an input. In order for PowerSpan II to propagate the reset another bus, the reset pin must be configured as an input (see “Reset Generation”...
Page 170: Clocks
The clock input for each port enables PowerSpan II’s master/target state machines to be synchronized to the external bus. Each interface has a dedicated PLL designed to eliminate clock tree insertion delay. PowerSpan II requires the input clock to be at the specified frequency before the negation of PO_RST_ (see...
Page 171: Power-Up Options
9. Resets, Clocks and Power-up Options Power-Up Options To ensure proper operation, a number of PowerSpan II features must be configured by completion of the power-up reset sequence. PowerSpan II has the following modes to configure these power-up options: •...
Page 172 PB_D[7]=1 BYPASS_EN=1 (PWRUP_BYPASS_EN) Bypass a. The information in the System Pin column is used when PowerSpan II is in Multiplexed System Pin mode (see page 173) b. The information in the PB_D Pin column is used when PowerSpan II is in Configuration Slave mode (page 175).
Page 173: Multiplexed System Pin Mode
PWRUP_PB_ARB_EN, PWRUP_P1_ARB_EN, and PWRUP_P2_ARB_EN have multiple purposes: determines the PLL frequency range, and the PowerSpan II power-up option. During the low to high transition of PO_RST_, the following pins are latched by PowerSpan II in order to choose the following internal clock PLL frequency range: •...
Page 174: Figure 22: Powerspan Ii Power-Up Waveform
9.3.1.2 Signal Timing for the Remaining Power-up Options Using to INT[5:1] During the low to high transition of PO_RST_, the INT[5:1] pins are internally latched by PowerSpan II in order to choose the required power-up options (see Figure 22). There is a 10 ns minimum input setup time and 10 ns maximum input hold time requirement for...
Page 175: Configuration Slave Mode
9.3.2 Configuration Slave Mode When there is a 60x bus device with the capability to be a configuration master in a PowerSpan II system (for example the PowerQUICC II) the Configuration Slave mode overrides the default power-up option — the Multiplexed System Pins mode. The slave mode’s power-up options overwrite...
Page 176 9. Resets, Clocks and Power-up Options PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 177: Endian Mapping
Data in a system must be consistent; that is, the system must be entirely big-endian or little-endian. This chapter describes the endian mapping system used in PowerSpan II. The following topics are discussed: •...
Page 178: Table 47: 64-Bit Pb Data Bus Byte Lane Definitions
D[56:63] DL[24:31] PowerSpan II supports both big-endian and PowerPC little-endian byte ordering. Endian selection with PowerPC is performed with the processor register MSR[LE] and defaults to big-endian. PowerPC little-endian mode allows a PowerPC and Pentium processor to share a data structure in memory.
Page 179: Processor Bus And Powerspan Ii Register Transfers
When the processor bus is operating in big-endian mode, the END bit must be set to big-endian mode. In this case, the PowerSpan II PB slave maps the processor bus byte lanes to PowerSpan II register addresses according to...
Page 180: Table 48: Powerspan Ii Big-Endian Pb Register Accesses
10. Endian Mapping Table 48: PowerSpan II Big-Endian PB Register Accesses PowerSpan II Register Address Starting PowerPC Byte Lanes A[1:0] Address Transfer PB_A Size [29:31] A[2] Byte Two bytes Tri- byte Word PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 181: Table 49: Processor Bus Address Munging
When the processor bus is operating in PowerPC little-endian mode, END bit must be set to PowerPC little-endian mode. In this case, the PB Slave munges the processor bus address, and maps byte lanes to register addresses to preserve the significance of the scalar. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 182: Table 50: Powerspan Ii Powerpc Little-Endian Pb Register Accesses
50. Only munged cases are illustrated. The PB slave asserts PB_TEA_ in response to an unaligned access to a register if the END bit is set for PowerPC little-endian mode. Table 50: PowerSpan II PowerPC Little-Endian PB Register Accesses PowerSpan II Register Address Starting...
Page 183: Processor Bus And Pci Transfers
In this mode, all elements of a multi-byte structure or scalar appear at the same address in both PCI and processor bus spaces, but their relative significance is not preserved. If the processor bus is programmed to be big-endian, PowerSpan II big-endian mode must be used for processor bus/PCI transactions.
Page 184: Table 51: Powerspan Ii Big-Endian Mode Byte Lane Mapping
10. Endian Mapping Table 51: PowerSpan II Big-endian Mode Byte Lane Mapping PowerPC Byte Lanes PCI Byte Lanes Start Transfer Size Address Byte Two bytes Tri-byte Word Five bytes Six bytes PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 185: Little-Endian Mode
PowerPC spaces, but translates the byte addressing. In order to access PCI device registers from the processor bus in little-endian mode, there are certain addressing rules which must be followed. In PowerSpan II when little-endian mode is selected, no address swapping takes place (refer to Table 52 on page 186).
Page 186: Table 52: Powerspan Ii Little-Endian Mode Byte Lane Mapping
10. Endian Mapping Table 52: PowerSpan II Little-endian Mode Byte Lane Mapping PowerPC Byte Lanes PCI Byte Lanes Start Transfer Size Address Byte Two bytes Tri-byte Word Five bytes Six bytes PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 187: Powerpc Little-Endian Mode
In PowerPC little-endian mode, the PB Master is restricted to transferring naturally aligned quantities. External PCI masters or the PowerSpan II’s DMA channels can request transactions that are not naturally aligned. The PB Master breaks up these requests into single byte transactions on the processor bus, with a performance penalty.
Page 188: True Little-Endian Mode
MSB on PCI is the high address. True little-endian mode cannot be used with the 4 byte read implementation in the PowerSpan II design. The MEM_IO bit must be set to 0 when the END field is set to 11. Refer to “Reads”...
Page 189: Table 53: Powerspan Ii True Little-Endian Byte Lane Mappings
10. Endian Mapping Table 53: PowerSpan II True Little-Endian Byte Lane Mappings PowerSpan II PCI Address Starting Address PowerPC Byte Lanes A[1:0] (Munged) Transfer PB_A Size [29:31] A[2] Byte Two bytes Tri bytes Word Five Bytes Integrated Device Technology PowerSpan II User Manual www.idt.com...
Page 190 10. Endian Mapping Table 53: PowerSpan II True Little-Endian Byte Lane Mappings PowerSpan II PCI Address Starting Address (Munged) PowerPC Byte Lanes A[1:0] Transfer PB_A Size [29:31] A[2] Six Bytes Seven Bytes Double PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 191: Signals And Pinout
Signals and Pinout This chapter describes the Processor Bus (PB) Interface, Single PCI PowerSpan II and Dual PCI PowerSpan II signals. Signals the differ between the Single PCI PowerSpan II and Dual PCI PowerSpan II are identified in the signal tables. The following topics are discussed: •...
Page 192: Processor Bus Signals
11. Signals and Pinout 11.1.2 Processor Bus Signals This section describes PowerSpan II PB Interface signals used to interface to the 60x bus processors. Signals in this group are 3.3V LVTTL compatible. The signals are not 5V tolerant. Table 55 summarizes the signals in this grouping.
Page 193 As output it indicates that PowerSpan II requests the ownership of the processor address bus. As input an external master should assert this signal...
Page 194 PB_RSTCONF_ Input Reset Configuration: Asserted by PowerQUICC II master to (Schmitt trigger) indicate to PowerSpan II to load power-up options. This pin must be pulled high if the multiplexed system pin mechanism is used to load the power-up options. PowerSpan II User Manual...
Page 195 PB Phase Locked Loop (nominally 2.5V). PB_DVDD Supply PB Digital VDD: Voltage supply pin to the digital circuits in the PB Phase Locked Loop (nominally 2.5V). Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 196: Signals
PowerSpan II. However, adding resistors to the address and data signals minimizes the current drawn by the PowerSpan II's tristated buffers when the bus is in an idle condition. The system designer must decide whether to add these resistors to the address and data bus.
Page 197 As input it is used by the external arbiter to grant the bus to PowerSpan II. As output it is used by the internal arbiter to grant the bus to an external master. This pin must be weakly pulled high.
Page 198 Refer to the PCI Local Bus Specification for reset states and recommended terminations of these PCI signals. b. To use the PowerSpan II Dual PCI in a 32-bit environment, add a pull-up resistor to P1_AD[32:63]. PowerSpan II User Manual...
Page 199: Signals
PCI-2 internal arbiter is used. As input it is used by the external arbiter to grant the bus to PowerSpan II. As output it is used by the PCI-2 internal arbiter to grant the bus to an external master.
Page 200 PCI-2 Bus Request: This is an output when an external arbiter is used and an input when the PCI-2 Interface internal arbiter is used. As input it is used by an external master to request the bus. As output it is used by PowerSpan II to request the bus.
Page 201: Miscellaneous Signals
11. Signals and Pinout 11.1.5 Miscellaneous Signals Table 58 below lists PowerSpan II signals which are not necessarily dedicated to the PB, PCI-1 or PCI-2 Interfaces. They have a variety of electrical capabilities. Table 58: Miscellaneous Signals Recommended Pin Name...
Page 202 Vdd CORE Supply Core Vdd: Nominally 2.5V Vdd I/O Supply IO Vdd: Nominally 3.3V Supply Ground a. Refer to the CompactPCI Hot Swap Specification for information on these signals. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 203: Test Signals
11. Signals and Pinout 11.1.6 Test Signals Table 59 lists PowerSpan II signals used to support silicon or board level testing. Table 59: Test Signals Recommended Pin Name Pin Type Reset State Termination Description PI_TEST1 Input Internal pull-down Pull-down resistor...
Page 204 Customers must assert TRST _concurrently with PO_RST_ as part of the power-up reset sequence. Input Internal pull-down Pull-down resistor Test Enable: Enables resistor manufacturing test. IDT recommends that system designers pull this signal low. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 205: Dual Pci Powerspan Ii Pinout
11. Signals and Pinout 11.2 Dual PCI PowerSpan II Pinout 11.2.1 Dual PCI PowerSpan II 480 HSBGA Figure 24 illustrates the top, side, and bottom views of the PowerSpan II package. Table 60: Package Characteristics Feature Description Package Type 480 HSBGA Package Body Size 37.5mm...
Page 206: Figure 24: 480 Hsbga
3. Conforms to JEDEC MO-151 Variation BAT-1. 11.2.1.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MO-151 Variation BAT-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 207: 480 Hsbga Pin Information
11. Signals and Pinout 11.2.2 480 HSBGA Pin Information The following table shows the PowerSpan II 480 HSBGA, 1.27 mm package, pin information. This package is backwards compatible with the original Powerspan’s 480 HPBGA device. A1. VSS_IO G25. VDD25 AC25. VDD25 A2.
Page 208 AF10. PB_D[57] B26. P1_ACK64_ M29. VSS_IO AF11. INT[0]_ B27. P1_CLK N1. PB_AP[3] AF12. PB_D[25] B28. VSS_IO N2. PB_TSIZ[0] AF13. PB_D[1] B29. VSS_IO N3. I2C_SCLK AF14. PB_FAST C1. PB_A[11] N4. PB_TBST_ AF15. PB_D[24] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 209 AG12. PB_D[17] C28. P1_AD[2] T1. PB_D[15] AG13. PB_RST_ C29. P1_AD[1] T2. VSS_IO AG14. PB_D[40] D1. PB_A[8] T3. PB_D[30] AG15. PB_D[16] D2. PB_A[9] T4. PB_D[39] AG16. PB_DP[6] D3. PB_A[10] T5. VDD25 AG17. PB_DP[3] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 210 AH14. PB_D[32] E1. PB_DBG3_ W2. PB_D[62] AH15. PB_D[8] E2. VSS_IO W3. PB_D[54] AH16. VSS_IO E3. PB_A[7] W4. PB_D[46] AH17. PB_DP[2] E4. ES W5. VDD33 AH18. PB_D[63] E5. VSS W25. VDD33 AH19. P2_AD[30] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 211 AJ16. PB_DP[5] F3. PB_A[6] AB3. PB_D[45] AJ17. P2_RST_DIR F4. PB_RST_DIR AB4. VSS AJ18. VSS_IO F5. VDD25 AB5. VDD25 AJ19. P2_AD[29] F25. VDD25 AB25. VDD25 AJ20. P2_AD[25] F26. PCI_REQ[6]_ AB26. P2_REQ[4]_ AJ21. P2_AD[23] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 212 AJ24. P2_CBE[2]_ G1. VSS_IO AC1. VSS_IO AJ25. P2_IRDY_ G2. PB_A[2] AC2. PB_BG3_ AJ26. P2_DEVSEL_ G3. PB_A[3] AC3. INT[5]_ AJ27. P2_PERR_ G4. VSS AC4. PB_D[13] AJ28. VSS_IO G5. VDD25 AC5. VDD25 AJ29. VSS_IO PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 213: Dual Pci Powerspan Ii 504 Hsbga
11. Signals and Pinout 11.2.3 Dual PCI PowerSpan II 504 HSBGA Figure 25 illustrates the top, side, and bottom views of the PowerSpan II package. Table 61: Package Characteristics Feature Description Package Type 504 HSBGA Package Body Size 27mm JEDEC Specification...
Page 214: Figure 25: 504 Hsbga
3. Conforms to JEDEC MO-151 Variation AAL-1. 11.2.3.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MO-151 Variation AAL-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 215: 504 Hsbga Pin Information
11. Signals and Pinout 11.2.4 504 HSBGA Pin Information The following table shows the PowerSpan II 504 HSBG pin information. A3. JT_TDO H21. VDD25 W21. VDD25 A4. PB_A[19] H22. VDD25 W22. VDD25 A5. JT_TMS H23. P1_CBE[0]_ W23. P2_IDSEL A6. PB_A[21] H24.
Page 216 AB11. VDD33 C10. PB_A[28] M12. VSS_IO AB12. PB_D[49] C11. PB_A[31] M13. VSS_IO AB13. VSS C12. P1_AD[37] M14. VSS_IO AB14. VSS C13. P1_AD[39] M15. VSS_IO AB15. P2_CBE[3]_ C14. P1_AD[47] M16. VSS_IO AB16. VDD33 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 217 AC16. P2_AD[26] D15. P1_AD[51] P3. PB_D[39] AC17. P2_AD[21] D16. P1_AD[57] P4. PB_AP[0] AC18. P2_IRDY_ D17. P1_AD[60] P5. VSS AC19. P2_DEVSEL_ D18. ENUM_ P6. VSS AC20. P2_TRDY_ D19. P1_REQ[1]_ P11. VSS_IO AC21. P2_PERR_ Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 218 AD21. P2_AD[19] E20. P1_TEST2 R24. P1_AD[31] AD22. P2_CLK E21. P1_TEST1 R25. P1_AD[27] AD23. P2_AVSS E22. VSS_IO R26. PCI_GNT[5]_ AD24. P2_VDDA E23. P1_AD[0] T1. PB_D[7] AD25. VSS_IO E24. P1_AD[2] T2. PB_D[22] AD26. P2_CBE[1]_ PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 219 AF4. PB_DBB_ F25. P1_AD[11] U25. P2_GNT[3]_ AF5. PB_D[27] F26. P1_AD[10] U26. P1_RST_ AF6. PB_D[34] G1. HEALTHY_ V1. PB_D[23] AF7. PB_D[2] G2. PB_TT[3] V2. PB_D[46] AF8. PB_D[41] G3. PB_A[4] V3. PB_D[29] AF9. PB_D[9] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 220 AF19. P2_AD[25] H2. PB_TT[0] W2. PB_D[14] AF20. P2_AD[28] H3. PB_A[1] W3. PB_BG3_ AF21. P2_AD[22] H4. PB_A[5] W4. PB_D[44] AF22. P2_AD[17] H5. VDD25 W5. VDD25 AF23. P2_FRAME_ H6. VDD25 W6. VDD25 AF24. P2_STOP_ PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 221: Single Pci Powerspan Ii Pin Information
Single PCI PowerSpan II Pin Information The PowerSpan II Single PCI device is offered in two packages. The 484 PBGA package is offered with a 23 mm body size and 1.00 mm ball pitch.The 420 HSBGA package is offered with a 35 mm body size and 1.27 mm ball pitch.
Page 222: Figure 26: 420 Hsbga
3. Conforms to JEDEC MO-034 Variation BAR-1. 11.3.1.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MS-034 Variation BAR-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 223: 420 Hsbga Pin Information
11. Signals and Pinout 11.3.2 420 HSBGA Pin Information The following table shows the PowerSpan II 420 HSBGA pin information. This package is backwards compatible with the original PowerSpan’s 420 HPBGA device. A1. VSS_IO G1. PB_TT[3] AA1. VSS_IO A2. VSS_IO G2.
Page 224 AC18. PB_DP[3] C3. VSS_IO M5. VDD25 AC19. PB_D[63] C4. PB_A[17] M22. VDD25 AC20. PB_DP[5] C5. PB_A[15] M23. P1_AD[15] AC21. VSS C6. PB_A[16] M24. P1_AD[14] AC22. PB_D[8] C7. PB_A[22] M25. P1_AD[5] AC23. VSS PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 225 AD23. VSS_IO D8. PB_A[23] R22. VDD25 AD24. VSS_IO D9. PB_A[24] R23. P1_TEST1 AD25. NC D10. PB_A[28] R24. P1_AD[21] AD26. VSS_IO D11. PB_A[31] R25. P1_AD[22] AE1. VSS_IO D12. P1_AD[35] R26. P1_AD[16] AE2. VSS_IO Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 226 AF2. PB_BG2_ E13. VSS_IO V23. P1_AD[27] AF3. INT[1]_ E14. VSS_IO V24. P1_AD[26] AF4. PB_D[61] E15. VDD25 V25. VSS_IO AF5. PB_CLK E16. VDD25 V26. VSS_IO AF6. VSS_IO E17. VDD25 W1. PB_D[62] AF7. PB_DVAL_ PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 227: Single Pci Powerspan Ii 484 Hsbga
F26. VSS_IO Y26. VSS_IO AF26. VSS_IO 11.3.3 Single PCI PowerSpan II 484 HSBGA Figure 27 illustrates the top, side, and bottom views of the PowerSpan II package. Table 63: Package Characteristics Feature Description Package Type 484 HSBGA Package Body Size...
Page 228: Figure 27: 484 Pbga
11. Signals and Pinout Figure 27: 484 PBGA 11.3.3.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MS-034 Variation AAJ-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 229 11. Signals and Pinout 11.3.3.2 484 PBGA Pin Information The following table shows the PowerSpan II 484 PBGA pin information. A1. PB_A[6] H9. VSS_IO R17. VDD33 A2. PB_A[13] H10. VSS_IO R18. VDD25 A3. TE H11. VSS_IO R19. P1_AD[22] A4. JT_TMS H12.
Page 230 V5. PB_TEA_ C12. P1_AD[41] K20. P1_AD[7] V6. PB_D[35] C13. P1_AD[44] K21. P1_AD[12] V7. VDD25 C14. P1_SERR_ K22. P1_AD[3] V8. VDD25 C15. P1_AD[50] L1. I2C_SCLK V9. VDD25 C16. P1_AD[51] L2. PB_AP[1] V10. VDD25 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 231 W14. PB_D[56] D21. P1_DVDD M7. VSS W15. PB_DP[2] D22. PB_CI_ M8. VSS_IO W16. PB_D[63] E1. INT[4]_ M9. VSS_IO W17. PB_D[8] E2. PB_A[1] M10. VSS_IO W18. PCI_GNT[7]_ E3. PB_A[5] M11. VSS_IO W19. VDD25 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 232 AA1. INT[3]_ F8. VDD33 N16. VSS AA2. VSS_IO F9. VDD33 N17. VDD33 AA3. PB_AVSS F10. VDD33 N18. VDD25 AA4. PB_CLK F11. VDD33 N19. P1_CBE[2]_ AA5. PB_D[38] F12. VDD33 N20. PCI_GNT[6]_ AA6. PB_D[14] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 233 AB10. PB_D[26] G17. VDD33 R3. PB_D[29] AB11. PB_D[57] G18. P1_GNT[3]_ R4. PB_TEST1 AB12. PB_D[33] G19. P1_64EN_ R5. VDD25 AB13. PB_D[25] G20. P1_AD[6] R6. VDD33 AB14. PB_D[9] G21. P1_AD[55] R7. VSS AB15. PB_FAST Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 234 H3. HEALTHY_ R11. VSS_IO AB19. PB_D[4] H4. PB_TT[3] R12. VSS_IO AB20. PB_D[0] H5. VDD25 R13. VSS_IO AB21. P1_RST_ H6. VDD33 R14. VSS_IO AB22. P1_AD[31] H7. VSS R15. VSS_IO H8. VSS_IO R16. VSS PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 235: Register Descriptions
Table 64 is a detailed memory map for PCSR space and shows the PowerSpan II register map for the Dual PCI PowerSpan II. PowerSpan II is available as both the Single PCI PowerSpan II and Dual PCI PowerSpan II. The shaded registers under PCI-1 Configuration and PCI-2 Configuration registers exist only if the associated PCI Interface is configured as the Primary Interface.
Page 236 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x008 P1_CLASS “PCI-1 Class Register” on page 254 0x00C P1_MISC0 “PCI-1 Miscellaneous 0 Register” on page 255 0x010 P1_BSI2O “PCI-1 I2O Target Image Base Address Register” on page 257...
Page 237 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x124 P1_TI2_TADDR “PCI-1 Target Image x Translation Address Register” on page 274 0x128-0x12C PowerSpan II Reserved 0x130 P1_TI3_CTL “PCI-1 Target Image x Control Register” on page 268 0x134 P1_TI3_TADDR “PCI-1 Target Image x Translation Address Register”...
Page 238 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x230 PB_SI3_CTL “Processor Bus Slave Image x Control Register” on page 287 0x234 PB_SI3_TADDR “Processor Bus Slave Image x Translation Address Register” on page 292 0x238 PB_SI3_BADDR “Processor Bus Slave Image x Base Address Register” on page 294...
Page 239 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x2A4 PB_P2_IACK “Processor Bus to PCI-2 Interrupt Acknowledge Cycle Generation Register” on page 301 0x2A8-0x2AC PowerSpan II Reserved 0x2B0 PB_ERRCS “Processor Bus Error Control and Status Register” on page 302...
Page 240 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x34C DMA1_CPP “DMA x Command Packet Pointer Register” on page 313 0x350 DMA1_GCSR “DMA x General Control and Status Register” on page 314 0x354 DMA1_ATTR “DMA x Attributes Register” on page 317...
Page 241 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x408 I2C_CSR “I2C/EEPROM Interface Control and Status Register” on page 322 0x40C RST_CSR “Reset Control and Status Register” on page 324 0x410 ISR0 “Interrupt Status Register 0” on page 327...
Page 242 0x550-0x7FC PowerSpan II Reserved PCI-2 Configuration Registers (Dual PCI PowerSpan II) The PCI-2 Configuration Registers are functionally identical to the PCI-1 Configuration Registers from offsets 0x000-0FC. Documentation of the PCI-2 Configuration Space is the same as the PCI-1 Interface, shifting the register offsets up by 0x800 and swapping PCI-1 and PCI-2 everywhere.
Page 243 12. Register Descriptions Table 64: PowerSpan II Register Map Offset Register Mnemonic 0x804 P2_CSR PCI-2 Control and Status Register 0x808 P2_CLASS PCI-2 Class Register 0x80C P2_MISC0 PCI-2 Miscellaneous 0 Register 0x810 P2_BSI2O PCI-2 I O Target Image Base Address Register...
Page 244: Access From Pci
Access from PCI The PCI-1 Register Image Base Address Register specifies the 4-Kbyte aligned base address for the PowerSpan II Control and Status Registers (PCSRs) in PCI Memory Space. The base address for PCSR space is enabled by: 1. Setting the BSREG_BAR_EN bit in the P1_MISC_CS 2.
Page 245: Access From The Processor Bus
Access from Multiple Interfaces PowerSpan II allows reads to its registers from all of its bus interfaces at the same time. However, writes may occur from only one bus interface at a time. This prevents data corruption if two or more interfaces try to write to the same register simultaneously.
Page 246: Configuration And Iack Cycle Generation
(Type 1 or 0) and IACK transactions on either PCI bus. 12.3.1 From PCI-to-PCI The following PowerSpan II registers are used by a PCI master to generate configuration (Type 1 or 0) and IACK transactions on the alternate PCI Interface: •...
Page 247: From The Processor Bus To Pci
12. Register Descriptions 12.3.2 From the Processor Bus to PCI The following PowerSpan II registers are used to generate Configuration (Type 1 or 0) and IACK transactions going from the Processor Bus Interface to either of the PCI Interfaces: •...
Page 248: Bit Ordering And Endian Ordering
12.5 Register Descriptions In the following detailed descriptions of each register, the shaded register bits are different for the Dual PCI PowerSpan II and Single PCI PowerSpan II Table 65 describes the abbreviations used in the register descriptions. Table 65: Abbreviations used in Register Descriptions...
Page 249 Do not write. Read back 0 PowerSpan II Reserved Do not write. Read back undefined Reserved Do not write. Read back undefined Single PCI PowerSpan II Single PCI PowerSpan II (PCI-1 and Processor Bus) Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 250 P1_RST 0x8260 Device ID processor bus EEPROM IDT allocated Device Identifier DID[15:0] R/Write from P1_RST 0x8261 Single PCI PowerSpan II processor bus VID[15:0] R/Write from P1_RST 0x10E3 Vendor ID processor bus EEPROM PCI SIG allocated Vendor Identifier Note: IDT acquired Tundra Semiconductor.
Page 251 P1_RST Received Target Abort The device sets this bit when a transaction it initiated was terminated with a Target-Abort. 0 = device did not detect Target-Abort 1 = device detected Target-Abort Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 252 0 = Master Module did not detect/generate data parity error 1 = Master Module detected/generated data parity error TFBBC P1_RST Target Fast Back to Back Capable Warning: PowerSpan II cannot accept fast back-to-back transactions - neither as the same agent nor as a different agent. DEV66 P1_RST...
Page 253 Enables the device to accept Memory cycles as a PCI target. EEPROM Memory Space 0 = Disable 1 = Enable P1_RST IO Space PowerSpan II does not respond to I/O cycles as a PCI target. 0 = Disable Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 254 BASE[7:0] R/WPB P1_RST 0x06 Base Class Code EEPROM When PowerSpan II is an I O controller, this field must be programmed with 0x0E either from the Processor Bus or by EEPROM. 0x06 = Bridge Device (default) 0x0E = I2O controller...
Page 255 PCI-1 Master in units of PCI bus clocks. The latency timer provides a resolution of one PCI bus clock. This timer always has a minimum value of eight PCI bus clocks. The values 000b-111b correspond to eight clock cycles. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 256: Table 66: Read Amount Versus Read Command
= 8 x 32-bit words CLINE[7:0] The CLINE Size specifies the system cacheline size in units of 32-bit words. The CLINE is used by the PowerSpan II PCI Master in determining which PCI Read cycle it generates on PCI (MR, MRL, MRM).
Page 257 A Base Address of 0x00000 is not a supported base address and the register image does not respond to PCI transactions as a target device when 0x00000 is written to this field — the image is disabled. PowerSpan II supports a Base Address of 0x00000 if the BAR_EQ_0 bit is set in the “Miscellaneous Control and Status Register”...
Page 258 A Base Address of 0x00000 is not a supported base address and the register image does not respond to PCI transactions as a target device when 0x00000 is written to this field — the image is disabled. PowerSpan II supports a Base Address of 0x00000 if the BAR_EQ_0 bit is set in the “Miscellaneous Control and Status Register”...
Page 259 A Base Address of 0x00000 is not a supported base address and the register image does not respond to PCI transactions as a target device when 0x00000 is written to this field — the image is disabled. PowerSpan II supports a Base Address of 0x00000 if the BAR_EQ_0 bit is set in the “Miscellaneous Control and Status Register”...
Page 260 Values for subsystem ID are vendor specific SVID[15:0] R/WPB P1_RST Subsystem Vendor ID EEPROM Subsystem Vendor IDs are obtained from the PCI SIG and used to identify the vendor of the add-in board or subsystem. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 261 Register Offset: 0x034 Bits Function Bits 31-24 PCI Reserved 23-16 PCI Reserved 8-15 15-08 PCI Reserved 16-23 07-00 CAP_PTR 24-31 Reset Reset Name Type State Function CAP_PTR [7:0] P1_RST 0xE4 Capabilities Pointer Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 262 Interrupt Pin EEPROM This interrupt pin is used to enable PCI interrupts. If this bit is not set, PowerSpan II does not use PCI interrupts. Setting this bit enables a single function PCI device to use INTA#. 0 = The device does not use any PCI interrupts...
Page 263 P1_RST Interrupt Line This read/write interrupt line field is used to identify which of the system interrupt request lines on the interrupt controller the device’s interrupt request pin is routed to. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 264 Primary PCI Interface of PowerSpan II. In the Single PCI PowerSpan II the lone PCI Interface is enabled as Primary, but in the Dual PCI PowerSpan II only one of the two ports can be enabled as Primary.
Page 265 0xE8. When the VPD_EN bit in the MISC_CSR register is cleared or an external EEPROM is not detected, this field reads back 0. CAP_ID [7:0] P1_RST 0x06 Capability ID Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 266 12.5.12 PCI-1 Vital Product Data Capability Register PowerSpan II only supports VPD access from the Primary PCI Interface. The Secondary PCI Interface reads zero for VPD accesses. VPD writes have no effect. VPD can also be disabled when the NXT_PTR bit in the “PCI-1 Compact PCI Hot Swap Control and...
Page 267 “PCI-1 Compact PCI Hot Swap Control and Status Register” on page 264 register is 0. PowerSpan II only supports VPD access from the Primary PCI Interface. The Secondary PCI Interface always reads zero for VPD accesses and VPD writes have no effect. Register Name: P1_VPDD...
Page 268 12.5.14 PCI-1 Target Image x Control Register This register contains the control information for the PowerSpan II PCI 1 Target Image x. The Image is enabled for decode when both IMG_EN and BAR_EN are set. The bits in this register are not dynamic. Do not alter these settings while transactions are being processed through PowerSpan II.
Page 269 Writes to P1_BSTx have no effect when this bit is cleared. This effectively disables the PowerSpan II P1_BSTx Image and PowerSpan II does not request PCI Memory space for the image. If the user is clearing this bit, they must also clear P1_BSTx.
Page 270 MEM_IO P1_RST MEM_IO mode PowerSpan II supports 4-byte reads. When this bit is set, I/O commands to the corresponding image generates Memory Read commands on the destination PCI bus (Py) with the same byte enables latched from the source bus transaction. If...
Page 271: Table 67: Block Size
BS[3:0] Block Size Address Lines Compared/Translated 0000 AD31-AD16 0001 128K AD31-AD17 0010 256K AD31-AD18 0011 512K AD31-AD19 0100 AD31-AD20 0101 AD31-AD21 0110 AD31-AD22 0111 AD31-AD23 1000 AD31-AD24 1001 AD31-AD25 1010 AD31-AD26 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 272: Table 68: Setting For Mode And Mem_Io Bits
Table 68: Setting for MODE and MEM_IO Bits MODE Setting MEM_IO setting Transaction size Memory cycle (minimum 8 byte memory read) I/O Cycle Memory cycle (minimum 4 byte memory read) a. X means either 0 or 1. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 273: Table 69: Read Amount
RD_AMT[2:0]: The read amount setting determines different values to prefetch from the destination bus. Table 69: Read Amount RD_AMT[2:0] Data Fetched 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 101-111 Reserved Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 274: Table 70: Arbitration Pin Mapping
The TADDR[15:0] field can be changed while transactions are being processed by PowerSpan II. This is the only parameter that can be changed during a transaction. All other programmable parameters must stay constant during a transaction.
Page 275 12. Register Descriptions Table 70: Arbitration Pin Mapping Register Bit External Arbitration Pins P1_REQ#[3]/P1_GNT#[3] P1_REQ#[4]/P1_GNT#[4] PCI_REQ#[5]/PCI_GNT#[5] PCI_REQ#[6]/PCI_GNT#[6] PCI_REQ#[7]/PCI_GNT#[7] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 276 PCI-1 to PCI-2 Configuration Cycle Information Register This register is used to set up the address phase of a PCI configuration cycle on PCI-2. This register is not implemented in the Single PCI PowerSpan II and must be treated as reserved. Register Name: P1_CONF_INFO...
Page 277: Table 71: Pci-2 Ad[31:11] Lines Asserted During Configuration Type 0 Cycles
0000 0000 0000 0000 0010 0 10011 0000 0000 0000 0000 0100 0 10100 0000 0000 0000 0000 1000 0 10101-11111 0000 0000 0000 0000 0000 0 The remaining address lines are: • P2_AD[10:8] = FUNC_NUM[2:0] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 278 12. Register Descriptions • P2_AD[7:2] = REG_NUM[5:0] • P2_AD[1:0] = 00 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 279 A write to the PCI Configuration Data register from the PCI-2 Interface or the Processor Bus has no effect. A read from PCI-2 Interface or the Processor Bus returns undefined data. This register is not implemented in the Single PCI PowerSpan II and must be treated as reserved. Register Name: P1_CONF_DATA...
Page 280 Writing to this register from the Processor Bus or either PCI bus has no effect. Reads from the PCI-2 Interface and Processor Bus return all zeros. This register is not implemented in the Single PCI PowerSpan II and must be treated as reserved. Register Name: P1_IACK...
Page 281 ES is set. Clearing the ES by writing 1 to the bit allows the error log registers to capture future errors. 0 = no error currently logged 1 = error currently logged CMDERR [3:0] P1_RST PCI Command Error Log Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 282 Bus Error Control and Status Register” on page 281 is set, qualifying and freezing the contents of this register. This register logs additional errors only after the ES bit in the P1_ERRCS register is cleared. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 283 When the P1_BSREG register is not visible in PCI-1 Configuration space, the PowerSpan II PCI-1 register image is disabled and PowerSpan II does not request PCI Memory space for the image. 0=disable...
Page 284 BM_PARK are not applicable. Programming these combinations result in unpredictable PowerSpan II behavior. The PowerSpan II PCI-1 internal arbiter is enabled by a power-up option. When disabled, an external arbiter is used. The signals P1_REQ[1]_/P1_GNT[1]_ are used by the PowerSpan II PCI-1 Master to arbitrate for access to the bus.
Page 285: Table 72: Parked Pci Master
1 = high priority STATUS_EN P1_RST Enable monitoring of master by arbiter Enables internal monitor of the PowerSpan II PCI arbiter. The monitor checks that no PCI Master waits longer than 16 PCI clock cycles before starting a transaction. 0 = disabled...
Page 286 12. Register Descriptions Table 72: Parked PCI Master BM_PARK [2:0] Parked PCI Master External Pins P1_REQ#[3]/P1_GNT#[3] P1_REQ#[4]/P1_GNT#[4] PCI_REQ#[5]/PCI_GNT#[5] PCI_REQ#[6]/PCI_GNT#[6] PCI_REQ#[7]/PCI_GNT#[7] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 287 287. The bits in this register are not dynamic. Do not alter these settings while transactions are being processed through PowerSpan II. Refer to “Processor Bus Slave Image x Translation Address Register” on page 292 for more information on dynamic address translation.
Page 288 MEM_IO PB_RST MEM_IO mode PowerSpan II supports 4-byte reads. When this bit is set, the Memory Read command to the corresponding image generates the Memory Read command on the destination PCI bus with a minimum 32 bit aligned 4-byte read.
Page 289 0 = purge read data at end of transfer 1 = keep read data Caution: The ARTRY_EN bit must be set to 1 in order for the PowerSpan II Prefetch Keep feature to keep prefetched data. The ARTRY_EN bit is in the “Processor Bus Miscellaneous Control and Status Register”...
Page 290: Table 73: Block Size
4 bytes or less. A transaction attempting to move more than 4 bytes will cause a TEA_ response. The TEA_ can be suppressed by setting the PB_MISC_CSR[TEA_EN] bit. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 291: Table 74: Setting For Mode And Mem_Io Bits
PCI bus to fetch more data. The read data is invalidated when a read with a non-matching address occurs. The ARTRY_EN bit must be set to 1 in order for the PowerSpan II Prefetch Keep feature to keep prefetched data. The ARTRY_EN bit is in the “Processor...
Page 292 TADDR[31:12] replace the Processor Bus PB_A[0:19]. For example, if TADDR[31:12] = 0x12345 and PB_SIx_CTL[BS]=0 (4 K image) and the address on the Processor Bus is PB_A[0:31] = 0x78563412, then the PCI address becomes 0x12345412 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 293: Table 76: Translation Address Mapping
12. Register Descriptions The TADDR[19:0] field can be changed while transactions are being processed by PowerSpan II. This is the only parameter that can be changed during a transaction. All other programmable parameters must stay constant during a transaction. Table 76: Translation Address Mapping...
Page 294 Register Name: PB_SIx_BADDR 258, 0x268, 0x278 Bits Function Bits 31-24 23-16 8-15 15-08 16-23 07-00 PowerSpan II Reserved 24-31 Reset Reset Name Type State Function BA[19:0] PB_RST 0 EEPROM Processor Bus Base Address PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 295 12. Register Descriptions 12.5.26 Processor Bus Register Image Base Address Register This register defines the Processor Bus address offset for PowerSpan II internal registers. The register can be loaded by an external EEPROM. A base address of 0 is valid.
Page 296 Name Type State Function DEST PB_RST Destination Bus 0 = PCI 1 1 = PCI-2 DEST PB_RST Single PCI PowerSpan II: Reserved PCI-1 Bus is the only destination. BUS_NUM[7:0] PB_RST Bus Number DEV_NUM[4:0] PB_RST Device Number FUNC_NUM[2:0] PB_RST Function Number...
Page 297: Table 77: Pci Ad[31:11] Lines Asserted During Configuration Type 0 Cycles
0000 0000 0000 0000 0010 0 10011 0000 0000 0000 0000 0100 0 10100 0000 0000 0000 0000 1000 0 10101-11111 0000 0000 0000 0000 0000 0 The remaining address lines are: • AD[10:8] = FUNC_NUM[2:0] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 298 12. Register Descriptions • AD[7:2] = REG_NUM[5:0] • AD[1:0] = 00 PowerSpan II does not generate configuration cycles to devices connected to AD[15:11]. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 299 PCI accesses, not register accesses. Register Name: PB_CONF_DATA Register Offset: 0x294 Bits Function Bits 31-24 CDATA 23-16 CDATA 8-15 15-08 CDATA 16-23 07-00 CDATA 24-31 Reset Reset Name Type State Function CDATA[31:0] PB_RST Configuration Data Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 300 “Processor Bus Register Image Base Address Register” on page 295 selects the endian conversion scheme used for accesses to PCI through this register. The definition of endian conversion scheme is for PCI accesses, not register accesses. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 301 PCI through this register. The definition of endian conversion scheme is for PCI accesses, not register accesses. This register is not implemented in the Single PCI PowerSpan II and must be treated as reserved. Integrated Device Technology PowerSpan II User Manual www.idt.com...
Page 302 0 = no error currently logged 1 = error currently logged TT_ERR[4:0] PB_RST Processor Bus Transaction Type Error Log SIZ_ERR[3:0] PB_RST Processor Bus SIZ field Error Log PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 303 “Processor Bus Error Control and Status Register” on page 302 is set, qualifying and freezing the contents of this register. This register logs additional errors only after the ES bit is cleared. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 304 0011 = 192 retries, etc. EXTCYC PB_RST Determines if the PowerSpan II PB master is enabled to generate extended cycles (16 byte or 24 byte) This ability improves performance of PowerQUICC II systems. The EXTCYC bit must be set to 0 in order to ensure compatibility with WinPath and other PowerPC devices.
Page 305 When ARTRY_EN is set, the Processor Bus Slave retries a processor (60x) bus master under the following conditions: • Register write while an external master connected to another PowerSpan II interface is doing a register write • Register read during I C load •...
Page 306 ARTRY_EN is cleared by default. The user will see improved Processor Bus Interface utilization by setting ARTRY_EN. The ARTRY_EN bit must be set to 1 in order for the PowerSpan II Prefetch Keep feature to keep prefetched data. Prefetch Keep is enabled by setting the PRKEEP bit in the “Processor Bus Slave Image x Control Register”...
Page 307 An example application for this feature is some L2 caches hold the BR_ signal after the TS_ signal starts. The PowerSpan II arbiter could see this as a valid request and give the bus to the L2 cache when the bus was not requested.
Page 308: Table 78: Mx_En Default State
Identifies the master to be parked (see Table 79 on page 308). 00 = PowerSpan II 01 = External Master 1 10 = External Master 2 11 = External Master 3 Mx_EN: When set, the arbiter recognizes address bus requests for this master. When cleared, the arbiter ignores address bus requests from this master.
Page 309 Reset Name Type State Function SADDR[31:0] G_RST Starting byte address on the source bus for the port defined by SRC_PORT field in the “DMA x Transfer Control Register” on page 311. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 310 DST_PORT field in the “DMA x Transfer Control Register” on page 311. The lower three bits of the destination address is identical to the lower three bits of the source address (DMAx_SRC_ADDR) PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 311 G_RST Source Port for DMA transfer [1:0] 00 = PCI-1 01 = PCI-2 10 = PB 11 = reserved Single PCI PowerSpan II: 00 = PCI-1 10 = PB 01, 11 = reserved DST_PORT G_RST Destination Port for DMA transfer...
Page 312 Linked-List mode, the DMA starts with a Direct mode transfer. After the direct mode transfer has completed, the DMA channel begins processing the linked-list. The field is updated during the DMA transaction. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 313 DMA x Command Packet Pointer Register This register specifies the 32-byte aligned address of the next command packet in the Linked-List for channel DMAx. It is programmed by PowerSpan II from the Linked-list when loading the command packet. The DMAx_CPP register is updated at the start of a Linked-list transfer and remains constant throughout the transfer.
Page 314 Write 1 to Set G_RST DMA Halt Request 0 = no effect 1 = Halt DMA at completion of current command packet DACT G_RST DMA Active 0 = not active 1 = active PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 315 256 bytes of source bus traffic occur before the idle period. If source and destination ports are the same, 64 bytes of source bus traffic occur before the idle period. This helps prevent PowerSpan II from interfering with Processor Bus instruction fetches. 000 = 0...
Page 316 1 = enable interrupt P2_ERR_EN G_RST Normal PCI Error Interrupt Enable 0 = no interrupt 1 = enable interrupt Single PCI PowerSpan II: Reserved PB_ERR_EN G_RST Processor Bus Error Interrupt Enable 0 = no interrupt 1 = enable interrupt STOP_EN...
Page 317 G_RST Command Packet Port [1:0] 00 = PCI-1 01 = PCI-2, 10 = PB 11 = reserved Single PCI PowerSpan II: 00 = PCI-1 10 = PB 01, 11 = reserved PB_GBL_ G_RST Processor Bus Global 0 = Assert PB_GBL_...
Page 318 Reset Reset Name Type State Function TUNDRA_DEV_ID[7:0] G_RST 0x00 IDT Internal Device ID 0x01 Single PCI PowerSpan II TUNDRA_VER_ID[7:0] G_RST 0x02 IDT Internal Version ID PowerSpan II = 02 (Original PowerSpan = 01) VPD_EN G_RST PCI Vital Product Data. EEPROM...
Page 319 Clear EEPROM When set, all configuration and memory register space accesses from PCI are retried. The Px_LOCKOUT bit must be cleared for all memory space accesses to the PowerSpan II’s PCI target images. 0=not set 1=set P2_LOCKOUT R/Write 1 to...
Page 320: Table 80: Arbitration Pin Mappings
Single PCI PowerSpan II: Reserved Px_LOCKOUT: When set, all configuration and memory register space accesses from PCI are retried. The Px_LOCKOUT bit must be cleared for all memory space accesses to the PowerSpan II’s PCI target images. PowerSpan II does not terminate the cycle when the Px_LOCKOUT bit is not cleared during a memory space access to the PCI target images.
Page 321 12. Register Descriptions 12.5.42 Clock Control Register PowerSpan II does not use the TUNE bits for adjusting the PLL parameters. This register does not effect PLL performance. This register does not effect the functionality or performance of PowerSpan II. This register makes the device backwards compatible with the PowerSpan II device.
Page 322 12. Register Descriptions 12.5.43 C/EEPROM Interface Control and Status Register This register supports the PowerSpan II I C/EEPROM interface. An I C bus cycle is initiated by writing to this register. Software must wait for the ACT bit to be zero before starting a new I C cycle.
Page 323 C interface is busy loading registers at the end of reset • I C interface is busy accessing PCI Vital Product Data 0=not active 1=active R/Write 1 to G_RST Error Clear 0=no error 1=error condition Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 324 12. Register Descriptions 12.5.44 Reset Control and Status Register This register contains the read-only bits that specify all PowerSpan II power-up options and status of a number of pins that are normally fixed for each application. Register Name: RST_CSR Register Offset: 0x40C...
Page 325 1=33 MHz to 66 MHz P1_R64_EN G_RST PWRUP P1_REQ64# output enable. 0=PowerSpan II does not assert P1_REQ64# at reset 1=PowerSpan II does assert P1_REQ64# at reset to indicate the presence of a 64-bit P1_AD[] bus P1_D64 G_RST PWRUP PCI-1 Databus Width Indicates the width of the databus to which the PCI-1 Interface is connected.
Page 326 PWRUP Phase Locked Loop Bypass Enable Indicates the setting of this power-up option. If this bit is set, the user has elected to bypass all PowerSpan II PLL’s. This bit supports slow speed emulation of a PowerSpan II based system.
Page 327 PCI-1 INTA# pin. P2_HW R/Write 1 to G_RST PCI-2 hardware interrupt. Set when a level interrupt is Clear detected on the PCI-2 INTA# pin. Single PCI PowerSpan II: Reserved Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 328 DB7-DB0 R/Write 1 to G_RST Set when a doorbell register is written to in the IER register. Clear MBOX[7:0] R/Write 1 to G_RST Set when a mailbox is written to. Clear PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 329 G_RST Processor Bus Max Retry Error. Maximum number of retries RETRY Clear detected. The cycle was initiated/destined to the PCI-2 bus. Single PCI PowerSpan II: Reserved PB_PB_RETRY R/Write 1 to G_RST Processor Bus Max Retry Error. Maximum number of retries Clear detected during Processor Bus to Processor Bus DMA.
Page 330 PB_P2_D_PAR R/Write 1 to G_RST Processor Bus Data Parity Error detected. The cycle was Clear initiated/destined to the PCI-2 bus. Single PCI PowerSpan II: Reserved PB_PB_D_PAR R/Write 1 to G_RST Processor Bus Data Parity Error detected during Processor Clear Bus to Processor Bus DMA.
Page 331 PCI-1 Master received too many retries. The cycle was Clear initiated from the Processor Bus. P1_P1_RETRY R/Write 1 to G_RST PCI-1 Master received too many retries during PCI-1 to PCI-1 Clear DMA. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 332 INT[0]_ hardware interrupt enable INT1_HW_EN G_RST INT[1]_ hardware interrupt enable INT2_HW_EN G_RST INT[2]_ hardware interrupt enable INT3_HW_EN G_RST INT[3]_ hardware interrupt enable INT4_HW_EN G_RST INT[4]_ hardware interrupt enable INT5_HW_EN G_RST INT[5]_ hardware interrupt enable PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 333 This causes the corresponding doorbell bit in the ISR0 register to be set. In order to clear the doorbell interrupt, the ISR0 status bit must be cleared. MBOXx_EN G_RST Mailbox interrupt enable Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 334 Processor Bus Error enable. The cycle was initiated/destined to the PCI-2 bus. 2P: Reserved PB_PB_ERR_E G_RST Processor Bus Error enable. Processor Bus to Processor Bus DMA. PB_A_PAR_EN G_RST Processor Bus Address Parity Error enable PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 335 RETRY_EN 2P: Reserved P1_P2_ERR_EN G_RST PCI-1 error enable. The cycle was initiated/destined to the PCI-2 bus. 2P: Reserved P1_PB_ERR_E G_RST PCI-1 error enable. The cycle was initiated/destined to the Processor Bus. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 336 PCI-1 max retry enable. The cycle was initiated/destined to RETRY_EN the PCI-2 bus. 2P: Reserved P1_PB_RETRY_ G_RST PCI-1 max retry enable. The cycle was initiated/destined to the Processor Bus. P1_P1_RETRY_ G_RST PCI-1 max retry enable. PCI-1 to PCI-1 DMA. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 337: Table 81: Mapping Definition
Map Mailbox #0 to an interrupt pin. Table 81 describes the mapping of interrupt sources to the external interrupt pins. The shaded entries indicate unsupported combinations for the Single PCI PowerSpan II. Table 81: Mapping Definition Map Field Interrupt Pin...
Page 338 12. Register Descriptions Table 81: Mapping Definition Map Field Interrupt Pin INT[3]_ INT[4]_ INT[5_ PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 339 Map doorbell #3 to an interrupt pin DB2_MAP[2:0] G_RST Map doorbell #2 to an interrupt pin DB1_MAP[2:0] G_RST Map doorbell #1 to an interrupt pin DB0_MAP[2:0] G_RST Map doorbell #0 to an interrupt pin Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 340 Map DMA #3 to an interrupt pin DMA2_MAP[2:0] G_RST Map DMA #2 to an interrupt pin DMA1_MAP[2:0] G_RST Map DMA #1 to an interrupt pin DMA0_MAP[2:0] G_RST Map DMA #0 to an interrupt pin PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 341 Map INT[3]_ hardware interrupt to an interrupt INT2_HW_MAP[2:0] G_RST Map INT[2]_ hardware interrupt to an interrupt INT1_HW_MAP[2:0] G_RST Map INT[1]_ hardware interrupt to an interrupt INT0_HW_MAP[2:0] G_RST Map INT[0]_ hardware interrupt to an interrupt Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 342 MAP[2:0] 2P: Reserved P1_PB_RETRY_ G_RST Map PCI-1 max retry error to an interrupt pin MAP[2:0] P1_P1_RETRY_ G_RST Map PCI-1 max retry error to an interrupt pin. PCI-1 to MAP[2:0] PCI-1 DMA. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 343 PCI-2 Interface. Table 81 on page 337 defines the mapping definitions. This register is not implemented in the Single PCI PowerSpan II and must be treated as reserved. Register Name: IMR_P2 Register Offset: 434 Bits...
Page 344 G_RST Map Processor Bus data parity error to an interrupt pin 2P: Reserved PB_PB_D_PAR_MAP[2:0] G_RST Map Processor Bus data parity error to an interrupt pin. Processor Bus to Processor Bus DMA. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 345 Map Processor Bus max retry errors to an interrupt pin MAP[2:0] PB_P2_RETRY_ G_RST Map Processor Bus max retry errors to an interrupt pin MAP[2:0] Single PCI PowerSpan II Reserved PB_PB_RETRY_ G_RST Map Processor Bus max retry errors to an interrupt pin. MAP[2:0] Processor Bus to Processor Bus DMA.
Page 346 I2O_HOST_MAP [2:0] G_RST Map I2O Host interrupt to an interrupt pin This field must be configured to route the interrupt source to the interrupt pin on PowerSpan II’s Primary PCI Interface. I2O_IOP_MAP[2:0] G_RST Map I2O IOP interrupt to an interrupt pin...
Page 347 EEPROM 0 = Input 1 = Output INT3_HW_DIR G_RST INT[3]_ Interrupt Direction EEPROM 0 = Input 1 = Output INT2_HW_DIR G_RST INT[2]_ Interrupt Direction EEPROM 0 = Input 1 = Output Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 348 12. Register Descriptions Reset Reset Name Type State Function INT1_HW_DIR G_RST INT[1]_ Interrupt Direction EEPROM 0 = Input 1 = Output INT0_HW_DIR G_RST INT[0]_ Interrupt Direction EEPROM 0 = Input 1 = Output PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 349 Register Name: MBOXx 0x464, 0x468, 0x46C Bits Function Bits 31-24 MBOXx 23-16 MBOXx 8-15 15-08 MBOXx 16-23 07-00 MBOXx 24-31 Reset Reset Name Type State Function MBOXx G_RST Mailbox x [31:0] Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 350 G_RST Semaphore 3 TAG3[6:0] G_RST Tag 3 SEM2 G_RST Semaphore 2 TAG2[6:0] G_RST Tag 2 SEM1 G_RST Semaphore 1 TAG1[6:0] G_RST Tag 1 SEM0 G_RST Semaphore 0 TAG0[6:0] G_RST Tag 0 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 351 G_RST Semaphore 7 TAG7[6:0] G_RST Tag 7 SEM6 G_RST Semaphore 6 TAG6[6:0] G_RST Tag 6 SEM5 G_RST Semaphore 5 TAG5[6:0] G_RST Tag 5 SEM4 G_RST Semaphore 4 TAG4[6:0] G_RST Tag 4 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 352 12. Register Descriptions 12.5.62 PCI I2O Target Image Control Register This register contains the control information for the PowerSpan II PCI I O Target Image. The lower 4 Kbytes of the image provide the I O Shell Interface - Inbound and Outbound Queues and the Host Interrupt Status and Mask Registers.
Page 353: Table 82: Block Size
Writes to Px_BSI2O have no effect when this bit is cleared. This bit must be enabled for PCI BIOS configuration in order to map PowerSpan II PCI I2O Target Image into memory space. 0 = Disable...
Page 354 BS: Specifies the size of the image, address lines compared and address lines translated. Table 82: Block Size BS[3:0] Block Size Address Lines Compared/Translated 0000 AD31-AD16 0001 128K AD31-AD17 0010 256K AD31-AD18 0011 512K AD31-AD19 0100 AD31-AD20 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 355: Table 83: Read Amount
RD_AMT[2:0]: The read amount setting determines different values to prefetch from the destination bus (see Table 83 on page 355). Table 83: Read Amount RD_AMT[2:0] Data Fetched 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 101-111 Reserved Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 356 When the TA_EN bit in the “PCI I2O Target Image Control Register” on page 352 is set, TADDR[15:0] replaces the PCI bus upper address bits, up to the size of the image. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 357 84). EMTR PRI_RST Empty FIFO Read Response The Empty FIFO Read Response bit determines the PowerSpan II response to an IOP read of the “I2O Inbound Post List Bottom Pointer Register” on page 365 or the “I2O Outbound Free List Bottom Pointer Register”...
Page 358 O_EN PRI_RST Extended MFA Enabled The IOP programs this bit to enable the PowerSpan II O Extended Capabilities support for the Outbound Option. The Host Outbound Index Offset Register needs to be programmed with the offset in the PCI I2O target Image where the Host Outbound Index Register can be located for the Outbound Option Support.
Page 359: Table 84: Host Outbound Post List Size
12. Register Descriptions HOPL_SIZE: This field specifies the size of the Host Outbound Post List circular FIFO in the Host memory. The IOP must program this field when PowerSpan II extended Outbound Option support is enabled. Table 84: Host Outbound Post List Size...
Page 360: Table 85: I2O Fifo Sizes
I2O Queue Base Address Register This register specifies the location and size of the Inbound and Outbound Queues in processor memory space. The IOP must program this register before enabling the PowerSpan II I2O Shell Interface. Register Name: I2O_QUEUE_BS Register Offset: 0x50C...
Page 361 12. Register Descriptions Table 85: I2O FIFO Sizes Maximum Number of Memory Required per PowerSpan II I2O Pointer FIFO_SIZE [2:0] MFAs per FIFO FIFO (Kbytes) bits incremented I2O_PTR [15:2] I2O_PTR [17:2] a. I2O_PTR is one of the following: IFL_BOT, IFL_TOP, IPL_BOT, IPL_TOP, OFL_BOT, OFL_TOP, OPL_BOT, OPL_TOP...
Page 362 BOT: This pointer gives the address offset for the Inbound Free List Bottom Pointer from PB_I2O_BS. This pointer is initialized by the IOP and maintained by PowerSpan II. This pointer is incremented by four for each PCI read from the Inbound Queue.
Page 363 Bottom pointer and then set the INCR bit in the “Inbound Free List Top Pointer Increment Register” on page 364 register to make the inbound free list full. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 364 PowerSpan II Reserved INCR 24-31 Reset Reset Name Type State Function INCR Write 1 to set PRI_RST Inbound Free List Top Pointer Increment Write 1 to increment the pointer by four. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 365 “I2O Inbound Post List Bottom Pointer Increment Register” on page 366. The initial values of the Inbound Post List Bottom and Top pointers must be the same. After these pointers are initialized, the inbound post list is empty. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 366 PowerSpan II Reserved INCR 24-31 Reset Reset Name Type State Function INCR Write 1 to set PRI_RST Inbound Post List Bottom Pointer Increment Write 1 to increment the pointer by four. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 367 TOP: This pointer gives the address offset for the Inbound Post List Top Pointer from PB_I2O_BS. This pointer is initialized by the IOP and maintained by PowerSpan II. This pointer is incremented by four for each PCI write to the Inbound Queue.
Page 368 INCR bit in the OFL_BOT_INC register. The initial values of the Outbound Free List Bottom and Top pointers must be the same. After these pointers are initialized, the outbound free list is empty. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 369 PowerSpan II Reserved INCR 24-31 Reset Reset Name Type State Function INCR Write 1 to set PRI_RST Outbound Free List Bottom Pointer Increment Write 1 to increment the pointer by four. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 370 TOP: This pointer gives the address offset for the Outbound Free List Top Pointer from PB_I2O_BS. This pointer is initialized by the IOP and maintained by PowerSpan II. This pointer is incremented by four for each PCI write to the Outbound Queue.
Page 371 BOT: This pointer gives the address offset for the Outbound Post List Bottom Pointer from PB_I2O_BS. This pointer is initialized by the IOP and maintained by PowerSpan II. This pointer is incremented by four for each PCI read from the Outbound Queue.
Page 372 This pointer is initialized by the IOP and can be incremented by four by writing 1 to the INCR bit in the OPL_TOP_INC register. The initial values of the Outbound Post List Bottom and Top pointers must be the same. After these pointers are initialized, the outbound post list is empty. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 373 PowerSpan II Reserved INCR 24-31 Reset Reset Name Type State Function INCR Write 1 to set PRI_RST Outbound Post List Top Pointer Increment Write 1 to increment the pointer by four. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 374 PowerSpan II I2O Target Image. The I2O Host Outbound Index register must be in the first 4 Kbytes of the PowerSpan II I2O Target Image and be aligned to a 4-byte boundary. This register must not be programmed with the following values: 0x030, 0x034, 0x040, 0x044.
Page 375 O Outbound Option support. This is an alias to the I2O Host Outbound Index Register in the PowerSpan II I2O Target Image. The Host maintains this register. This register indicates the address in Host memory from which the Host is to retrieve the next Outbound XMFA.
Page 376 12.5.80 I2O IOP Outbound Index Register This register is required for PowerSpan II I2O Outbound Option support. This register indicates the address in Host memory to which the IOP is to post the next Outbound XMFA. The IOP maintains this register.
Page 377 16-23 07-00 PowerSpan II Reserved INCR 24-31 Reset Reset Name Type State Function INCR Write 1 to set PRI_RST IOP Outbound Index Increment Write 1 to increment the pointer by four. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 378 The PCI-2 Configuration Registers are functionally identical to the PCI-1 Configuration Registers from offsets 0x000-0FC. Documentation of the PCI-2 Configuration Space is the same as the PCI-1 Interface, shifting the register offsets up by 0x800 and swapping PCI-1 and PCI-2 everywhere. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09...
Page 379 The PCI-2 Target Image Control and Status Registers are functionally identical to the PCI-1 Target Image Control and Status Registers from offsets 0x100-1FC. Documentation of the PCI-2 Target Images is the same as the PCI-1 Images, shifting the register offsets up by 0x800 and swapping PCI-1 and PCI-2 everywhere. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 380 12. Register Descriptions PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 381: Electrical And Signal Characteristics
Electrical and Signal Characteristics This chapter describes the electrical characteristics of the PowerSpan II device. It also details the pin-outs of both the Single PCI PowerSpan II and Dual PCI PowerSpan II. The following topics are discussed: • “Electrical Characteristics” on page 381 •...
Page 382 = min, I = 10mA Input Capacitance Output Low Current =1.5V (65 ohm output) a. Non-PCI DC Electrical Characteristics (Ta= -40 °C to 85 °C b. CompactPCI Hot Swap LED pin PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 383: Power Dissipation
13. Electrical and Signal Characteristics 13.2 Power Dissipation Table 87 shows the Single PCI PowerSpan II power dissipation.. Table 87: Single PCI PowerSpan II Power Dissipation Processor Bus Clock PCI-1 Clock Vdd I/O Vdd Core Maximum 50 MHz 33 MHz 0.17...
Page 384: Operating Conditions
13. Electrical and Signal Characteristics 13.3 Operating Conditions 13.3.1 Recommended Operating Conditions The following table, Table 89, specifies the recommended operating conditions of the PowerSpan II. Table 89: Operating and Storage Conditions Symbol Parameter Units Vdd I/O I/O DC Supply 3.15...
Page 385: Table 90: Absolute Maximum Ratings
Functional operation at the maximums is not guaranteed. Stress beyond those listed can affect device reliability or cause permanent damage to PowerSpan II. b. Vdd Core/ Px_VDDA must not exceed Vdd I/O by more than 0.4 V. This includes during power-on reset.
Page 386 13. Electrical and Signal Characteristics PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 387: Table 91: Package Characteristics
Package Information This appendix discusses PowerSpan II’s packaging (mechanical) features. The following topics are discussed: • “Package Characteristics” on page 387 • “Thermal Characteristics” on page 391 14.1 Package Characteristics PowerSpan II’s package characteristics are summarized in the following sections.
Page 388: Figure 28: 420 Hsbga
3. Conforms to JEDEC MO-034 Variation BAR-1. 14.1.1.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MS-034 Variation BAR-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 389: Table 92: Package Characteristics
14. Package Information 14.1.2 Dual PCI PowerSpan II 480 HSBGA Figure 29 illustrates the top, side, and bottom views of the PowerSpan II package. Table 92: Package Characteristics Feature Description Package Type 480 HSBGA Package Body Size 37.5mm JEDEC Specification...
Page 390: Figure 29: 480 Hsbga
3. Conforms to JEDEC MO-151 Variation BAT-1. 14.1.2.1 Package Notes 1. All dimensions in mm 2. All dimensions and tolerance conform to ANSI Y14.5M - 1994 3. Conforms to JEDEC MO-151 Variation BAT-1 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 391: Thermal Characteristics
14. Package Information 14.2 Thermal Characteristics The thermal performance of PowerSpan II package is represented by the following parameters: 1.  , Thermal resistance from junction to ambient  = (T ) / P Where, is the junction temperature is the ambient temperature P is the power dissipation ...
Page 392: Table 93: Thermal Parameters
420 package. These values are based on the parameters described in Table 93 Table 94: 420 HSBGA Package Performance Theta ja (C/W) 0 m/s 1 m/s 2 m/s (C/W) Theta jc (C/W) 16.5 14.6 13.2 5.48 6.80 PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 393: Table 95: Thermal Parameters
480 package. These values are based on the parameters described in Table Table 96: 480 PBGA Package Performance Theta ja (C/W) 0 m/s 1 m/s 2 m/s (C/W) Theta jc (C/W) 15.1 13.2 11.8 4.87 6.00 Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 394 14. Package Information PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 395: Ac Timing
15.1 Overview This chapter describes the timing information for the PowerSpan II device. The timing for the both the Single and the Dual PCI PowerSpan II’s Processor Bus Interface is 100 MHz, while the PCI Interface(s) can operate either at 33 MHz or 66 MHz.
Page 396: Table 97: Reset, And Clock Timing Parameters
15. AC Timing 15.2 Single PCI PowerSpan II Timing Parameters The timing parameters specified in this document are guaranteed by design. Test conditions for timing parameters in Table 97 Table 101 are: • Commercial (C): 0ºC to 70ºC, 3.15 - 3.45V, 2.38 - 2.63V •...
Page 397 This parameter is a function of the slowest frequency of PB_CLK, and P1_CLK. The minimum occurs at 100 MHz, the maximum at 25 MHz. After this time, PowerSpan II is synchronized to external buses and able to participate in transactions once externally applied resets are released.
Page 398: Table 98: Pci 33 Mhz Timing Parameters
Px_M66EN is connected to logic zero. Table 98 summarizes the timing behavior of a PowerSpan II PCI interface configured in this way. This table is valid for operation in 3.3V or 5.0V signaling environments. Table 98: PCI 33 MHz Timing Parameters...
Page 399: Table 99: Pci 66 Mhz Timing Parameters
Px_M66EN is connected to logic one. Table 99 summarizes the timing behavior of a PowerSpan II PCI interface configured in this way. This table is valid for operation in a 3V signaling environment. Table 99: PCI 66 MHz Timing Parameters...
Page 400: Table 100: Pb Timing Parameters
15. AC Timing The PowerSpan II PB Interface can be configured for 100 MHz operating frequencies. Table 100 summarizes the timing behavior of a PowerSpan II PB interface configured for 100 MHz. Table 100: PB Timing Parameters CE/IE Timing Parameter...
Page 401: Table 101: Miscellaneous Timing Parameters
PowerSpan II synchronizes these inputs before using them. This parameter must be met for deterministic response time. PowerSpan II filters these inputs to ensure spurious low going pulses are not recognized as active interrupts. An interrupt pin is considered valid if three PB_CLK samples yield the same result.
Page 402: Table 102: Reset, And Clock Timing Parameters
15. AC Timing 15.3 Dual PCI PowerSpan II Timing Parameters The timing parameters specified in this document are guaranteed by design. Test conditions for timing parameters in Table 102 Table 106 are: • Commercial (C): 0ºC to 70ºC, 3.15 - 3.45V, 2.38 - 2.63V •...
Page 403 This parameter is a function of the slowest frequency of PB_CLK, P1_CLK, and P2_CLK. The minimum occurs at 100 MHz, the maximum at 25 MHz. After this time, PowerSpan II is synchronized to external buses and able to participate in transactions once externally applied resets are released.
Page 404: Table 103: Pci 33 Mhz Timing Parameters
Px_M66EN is connected to logic zero. Table 103 summarizes the timing behavior of a PowerSpan II PCI interface configured in this way. This table is valid for operation in 3.3V or 5.0V signaling environments. Table 103: PCI 33 MHz Timing Parameters...
Page 405: Table 104: Pci 66 Mhz Timing Parameters
Px_M66EN is connected to logic one. Table 104 summarizes the timing behavior of a PowerSpan II PCI interface configured in this way. This table is valid for operation in a 3V signaling environment. Table 104: PCI 66 MHz Timing Parameters...
Page 406: Table 105: Pb Timing Parameters
15. AC Timing The PowerSpan II PB Interface can be configured for 100 MHz operating frequencies. Table 105 summarizes the timing behavior of a PowerSpan II PB interface configured for 100 MHz. Table 105: PB Timing Parameters CE/IE Timing Parameter...
Page 407: Table 106: Miscellaneous Timing Parameters
PowerSpan II synchronizes these inputs before using them. This parameter must be met for deterministic response time. PowerSpan II filters these inputs to ensure spurious low going pulses are not recognized as active interrupts. An interrupt pin is considered valid if three PB_CLK samples yield the same result.
Page 408: Figure 30: Power-Up Reset: Compactpci Adapter Scenario
15. AC Timing 15.4 Timing Diagrams The timing diagrams in this section apply to both the Single PCI PowerSpan II and the Dual PCI PowerSpan II. Figure 30: Power-up Reset: CompactPCI Adapter Scenario Reset Ready for initialization t100 t100 t101...
Page 409: Figure 31: Power-Up Options: Multiplexed System Pin Approach
1. The power-up options latched by the Configuration Slave mode take precedence over those latched by the Multiplexed System Pins mode. 2. The configuration master runs configuration cycles as part of each HRESET_ sequence. Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 410: Figure 33: Clocking
P1_CLK t130 t130 t131 t131 t132 t132 P2_CLK Figure 34: PCI Timing t203 t204 PCI Clock (P1_CLK, P2_CLK) PCI Input t200 t202 t201 PCI Output PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 411: Figure 35: Pci Miscellaneous Timing; Compact Pci Adapter Scenario
Figure 32 on page 409. 2. In a CompactPCI Host application, PowerSpan II controls P1_RST# and P1_REQ64# and can ensure compliance with t205 and t206. In CompactPCI Adapter application, the system must guarantee P1_RST# negated after PowerSpan II power-up options loaded.
Page 412: Figure 37: Processor Bus Timing
PB_TT[0:4], PB_TBST_, PB_GBL_, PB_CI_, PB_D[0:63], PB_DP[0:7]. 2. The transaction control group of signals includes: PB_TS_, PB_ABB_, PB_DBB_, PB_TA_, PB_DVAL_, PB_TEA-, PB_AACK_. 3. The transaction arbitration group outputs includes: PB_BR[1]_, PB_BG[1:3]_, PB_DBG[1:3]_. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 413: Figure 38: Interrupt Timing
P1_INTA#, P2_INTA#, INT[5:0] (output) t404 t404 t402 t403 P1_INTA#, P2_INTA#, INT[5:0] (input) Figure 39: I C Timing t410 t411 t412 t416 t419 I2C_SCLK t415 t414 t413 t417 t418 I2C_SDA STOP/START Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 414 15. AC Timing PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 415: Table 107: Standard Ordering Information
Ordering Information This appendix discusses PowerSpan II’s ordering information. 16.1 Ordering Information When ordering the PowerSpan II please refer to the device by its full part number, as displayed in Table 107. Table 107: Standard Ordering Information Voltage (IO/ Part Number...
Page 416 16. Ordering Information PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 417: Figure 40: Bootstrap Diodes For Power-Up Sequencing
This chapter deals with design issues in a PowerSpan II system. Recommended Bootstrap Diode IDT recommends the use of a bootstrap diode between the power rails. The bootstrap diodes that are used in the system must be configured so that a nominal Core Supply Voltage (Vdd Core) is sourced from the I/O Supply Voltage (Vdd I/O) until the power supply is active.
Page 418: Figure 41: Pll Power Filter
A. Hardware Implementation PLL External Decoupling The PLLs in the PowerSpan II device should be externally decoupled in order to have the cleanest possible supply environment. IDT recommends two decoupling scenarios for PowerSpan II. The first recommendation is a backwards compatible design that enables migrating PowerSpan II users to employ the decoupling scheme used in the original PowerSpan II.
Page 419: Figure 42: Pll Decoupling
A. Hardware Implementation A.3.2 PowerSpan II External PLL Decoupling for New Designs To provide the cleanest possible supply environment for the PLL, the supplies should be decoupled externally. Isolation should be provided between the external core supply voltage on the board and the supply that goes to the PLL.
Page 420 A. Hardware Implementation PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 421: B. Typical Applications
This section highlights the use of PowerSpan II in PowerPC and CompactPCI applications. B.2.1 Direct Connect Support The PowerSpan II PB Interface provides direct connect support for a number of PowerPC embedded processors. The block diagram in Figure 43 illustrates a system where the PowerSpan II and the PowerQUICC II and PowerPC 7xx are directly connected.
Page 422: Figure 43: Powerspan Ii In Multi-Processor 60X System
B. Typical Applications The PowerSpan II PB Interface fully supports the multi processing cache coherent aspects of the processor bus. The PowerSpan II PB Interface can only interact with 64-bit port size agents. The presence of the PowerPC 7xx limits the extent of extended cycle support in the system depicted in Figure The SIZ[0] pin is hardwired on PowerSpan II and the PowerQUICC II.
Page 423: B.2.2 Compactpci Adapter Card
Additionally, the PowerPC 7xx and PowerSpan II can program PowerQUICC II registers and master the PowerQUICC II local bus. The PowerSpan II processor bus arbiter controls system boot. Boot can be selected from PCI by configuring the arbiter at power-up to ignore all external requests on Bus Request (PB_BR[3:1]_). This allows an external PCI master to configure the PowerQUICC II memory controller and load system boot code before enabling recognition of requests on PB_BR[3:1]_.
Page 424: Figure 44: Powerspan Ii In Compactpci Peripheral Slot
33MHZ Secondary PCI Agents All PowerSpan II resources are reset when PO_RST_ is asserted by the card’s power on reset logic. PB_RST_ and P2_RST# are configured as outputs and are asserted during the power on reset sequence (PO_RST_) or during a CompactPCI reset (P1_RST#). The connection between PowerSpan II PB_RST_ and PowerQUICC II HRESET _is required for PowerSpan II to load its power-up options during Configuration activity generated by the Configuration master.
Page 425: B.2.3 Compactpci Host Card
When the PowerQUICC II system boots from local FLASH there are two possible scenarios which can occur. In the first case, after reset, PowerSpan II retries all accesses to its Primary PCI target. The PowerQUICC II configures the PowerSpan II Primary and Secondary Base Address Registers and then configures all agents on the Secondary bus.
Page 426: Figure 45: Powerspan Ii In Compactpci System Slot
B. Typical Applications Figure 45: PowerSpan II in CompactPCI System Slot PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 427: B.3 Winpath And Powerspan Ii Applications
Detailed descriptions of typical applications, design information, signal connection, and register settings involving the Wintegra WinPath processor and PowerSpan II are available in the Interfacing the Wintegra WinPath with the IDT PowerSpan II Application Note. Integrated Device Technology PowerSpan II User Manual www.idt.com...
Page 428 B. Typical Applications PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 429 A process for transferring data from main memory to a device without passing it through the Host processor. DRAM Dynamic Random Access Memory. variant with dual PCI interfaces. Dual PCI PowerSpan II PowerSpan II FLASH Writable non-volatile memory, often used to store code in embedded systems. Host Node A node composed of one or more application processors and their associated resources.
Page 430 A range of Memory space is prefetchable if there are no side effects on reads. Peripheral Slot Slots on a CompactPCI bus segment that may contain simple boards, intelligent slaves, or PCI bus masters. PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 431 Used to support the movement of serial data to/from the serial ports of the PowerQUICC II. Secondary PCI Interface In the Dual PCI PowerSpan II, this interface is the interface that is not designated as the Primary PCI Interface. variant with a single PCI interface.
Page 432 Glossary PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 433: Index
PB master PB Slave PCI master DEST BM_PARK[2:0] DEVSEL# Bus Errors Direct Mode DMA interrupts initializing PB master terminating PB slave transfer acknowledgment PCI master Discard Timer PCI target Bus Parking Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 434 PB slave mapping PCI master normal operations PCI target pins Even Parity register description PB master sources EXTCYC status Extended Cycles transfer exceptions IRDY# Flush Block FRAME# Kill Block Frequency PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 435 PB Interface data phase address phase error logging and interrupts address retry window parity monitoring and generation bus errors termination phase Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 436 PCI 1 Miscellaneous Control and Status Register LAST MAX_RETRY NCP[31:5] PCI 1 Target Image x Base Address Register DMA x Destination Address Register BAR_EN BS[3:0] DEST END[1:0] GBL_ IMG_EN MODE PRKEEP RD_AMT[2:0] RTT[4:0] TA_EN WTT[4:0] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 437 REQ# PowerPC (PB) Reset Px_AD[31:0] from PCI bus Px_C⁄BE[3:0] timing parameters Px_DEVSEL Resets Px_FRAME direction control Px_IRDY generation Px_M66EN pins Px_PAR RST# Px_PERR RTT[4:0] Px_TRDY test SIZ[1:0] Special Cycle STOP STOP_EN Integrated Device Technology PowerSpan II User Manual www.idt.com 80A1010_MA001_09...
Page 438 TRDY# Typical Applications Vital Product Data defined EEPROM Primary PCI reading writing VPD_EN Window of Opportunity defined Write with Flush Write with flush Write with flush atomic Write with kill WTT[4:0] PowerSpan II User Manual Integrated Device Technology 80A1010_MA001_09 www.idt.com...
Page 439 Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
Page 440 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology) CA91L8260B-100CE CA91L8200B-100CE CA91L8200B-100CEY CA91L8260B-100CEV...

IDT PowerSpan II Manual

1 Functional Overview

2 PCI Interface

3 Processor Bus Interface

4 Dma

5 I2C/Eeprom

6 Arbitration

7 Interrupt Handling

8 Error Handling

9 Resets, Clocks and Power-Up Options

10 Endian Mapping

11 Signals and Pinout

12 Register Descriptions

13 Electrical and Signal Characteristics

14 Package Information

Quick Links

Related Manuals for IDT PowerSpan II

Summary of Contents for IDT PowerSpan II