IDT 89HPES16T4G2 PCI Express Switch Manuals

Manuals and User Guides for IDT 89HPES16T4G2 PCI Express Switch. We have 1 IDT 89HPES16T4G2 PCI Express Switch manual available for free PDF download: Preliminary User's Manual

IDT 89HPES16T4G2 Preliminary User's Manual (149 pages)

Brand: IDT | Category: Switch | Size: 1.26 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
7
PES16T4G2 Device Overview
19
Introduction
19
Features
19
System Diagram
20
Table 1.1 Table
20
Logic Diagram
21
System Identification
22
Vendor ID
22
Device ID
22
Revision ID
22
Jtag ID
22
Pin Description
22
PES16T4G2 Device ID
22
Table 1.3 PCI Express Interface Pins
22
Table 1.4 Smbus Interface Pins
23
Table 1.5 General Purpose I/O Pins
24
Table 1.6 System Pins
25
Table 1.7 Test Pins
26
Table 1.8 Power, Ground, and Serdes Resistor Pins
26
Pin Characteristics
27
Table 1.9 Pin Characteristics
27
Port Configuration
28
Figure 1.3 PES16T4G2 Port & Device Numbering
29
Clocking, Reset and Initialization
31
Clocking
31
Table 2.1 Reference Clock Mode Encoding
31
Reset
32
Table 2.2 Boot Configuration Vector Signals
32
Fundamental Reset
33
Figure 2.1 Fundamental Reset with Serial EEPROM Initialization
34
Hot Reset
35
Figure 2.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
35
Upstream Secondary Bus Reset
36
Downstream Secondary Bus Reset
36
Downstream Port Reset Outputs
37
Power Enable Controlled Reset Output
37
Figure 2.3 Power Enable Controlled Reset Output Mode Operation
37
Power Good Controlled Reset Output
38
Figure 2.4 Power Good Controlled Reset Output Mode Operation
38
Link Operation
39
Introduction
39
Polarity Inversion
39
Lane Reversal
39
Figure 3.1 Port Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth=0X4)
39
Link Width Negotiation
40
Dynamic Link Width Re-Configuration
40
Background
40
Figure 3.2 Port Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth=0X2)
40
Dynamic Link Width Re-Configuration Support in the PES16T4G2
41
Link Speed Negotiation
41
Background
41
Link Speed Negotiation in the PES16T4G2
42
Software Management of Link Speed
43
Link Retraining
44
Slot Power Limit Support
44
Upstream Port
44
Downstream Port
45
Link States
45
Figure 3.3 PES16T4G2 ASPM Link Sate Transitions
45
Active State Power Management
46
Link Status
46
De-Emphasis Negotiation
46
Low-Swing Transmitter Voltage Mode
47
General Purpose I/O
49
Introduction
49
GPIO Configuration
49
Table 4.1 General Purpose I/O Pin Alternate Function
49
Table 4.2 GPIO Pin Configuration
49
GPIO Pin Configured as an Input
50
GPIO Pin Configured as an Output
50
GPIO Pin Configured as an Alternate Function
50
Smbus Interfaces
51
Introduction
51
Figure 5.1 Smbus Interface Configuration Examples
51
Master Smbus Interface
52
Initialization
52
Serial EEPROM
52
Table 5.1 Serial EEPROM Smbus Address
52
Table 5.2 PES16T4G2 Compatible Serial Eeproms
53
Figure 5.2 Single Double Word Initialization Sequence Format
53
Figure 5.3 Sequential Double Word Initialization Sequence Format
54
Figure 5.4 Configuration Done Sequence Format
54
Table 5.3 Serial EEPROM Initialization Errors
55
I/O Expanders
56
Table 5.4 I/O Expander Function Allocation
56
Table 5.5 I/O Expander Default Output Signal Value
57
Table 5.6 I/O Expander 0 Signals
59
Table 5.7 I/O Expander 2 Signals
60
Table 5.8 I/O Expander 4 Signals
60
Slave Smbus Interface
61
Initialization
61
Table 5.9 Slave Smbus Address When a Static Address Is Selected
61
Smbus Transactions
62
Table 5.10 Slave Smbus Command Code Fields
62
Figure 5.5 Slave Smbus Command Code Format
62
Table 5.11 CSR Register Read or Write Operation Byte Sequence
63
Figure 5.6 CSR Register Read or Write CMD Field Format
63
Table 5.12 CSR Register Read or Write CMD Field Description
64
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence
64
Table 5.14 Serial EEPROM Read or Write CMD Field Description
65
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
65
Figure 5.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
66
Figure 5.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
66
Figure 5.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
66
Figure 5.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
67
Figure 5.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
67
Figure 5.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
67
Power Management
69
Introduction
69
Figure 6.1 PES16T4G2 Power Management State Transition Diagram
69
PME Messages
70
PCI-Express Power Management Fence Protocol
70
Table 6.1 PES16T4G2 Power Management State Transition Diagram
70
Power Budgeting Capability
71
Hot-Plug and Hot-Swap
73
Hot-Plug
73
Figure 7.1 Hot-Plug on Switch Downstream Slots Application
73
Figure 7.2 Hot-Plug with Switch on Add-In Card Application
74
Figure 7.3 Hot-Plug with Carrier Card Application
74
Table 7.1 Downstream Port Hot Plug Signals
75
Hot-Plug I/O Expander
76
Hot-Plug Interrupts and Wake-Up
76
Legacy System Hot-Plug Support
76
Figure 7.4 PES16T4G2 Hot-Plug Event Signalling
77
Hot-Swap
78
Configuration Registers
79
Configuration Space Organization
79
Table 8.1 Base Addresses for Port Configuration Space Registers
79
Figure 8.1 Port Configuration Space Organization
80
Upstream Port (Port 0)
81
Table 8.2 Upstream Port 0 Configuration Space Registers
81
Downstream Ports
84
Table 8.3 Downstream Ports 2, 4, 6 Configuration Space Registers
84
Register Definitions
88
Type 1 Configuration Header Registers
88
PCI Express Capability Structure
97
Power Management Capability Structure
112
Message Signaled Interrupt Capability Structure
114
Subsystem ID and Subsystem Vendor ID
115
Extended Configuration Space Access Registers
116
Advanced Error Reporting (AER) Enhanced Capability
117
Device Serial Number Enhanced Capability
123
PCI Express Virtual Channel Capability
124
Power Budgeting Enhanced Capability
130
Switch Status and Control Registers
131
Physical Layer Control and Status Registers
138
Power Management Control and Status Registers
139
JTAG Boundary Scan
141
Introduction
141
Test Access Point
141
Signal Definitions
141
Figure 9.1 Diagram of the JTAG Logic
141
Table 9.1 JTAG Pin Descriptions
142
Figure 9.2 State Diagram of Pes16T4G2'S TAP Controller
142
Boundary Scan Chain
143
Table 9.2 Boundary Scan Chain
143
Test Data Register (DR)
144
Boundary Scan Registers
144
Figure 9.3 Diagram of Observe-Only Input Cell
144
Figure 9.4 Diagram of Output Cell
145
Figure 9.5 Diagram of Bidirectional Cell
145
Instruction Register (IR)
146
Extest
146
Table 9.3 Instructions Supported by Pes16T4G2'S JTAG Boundary Scan
146
Sample/Preload
147
Bypass
147
Clamp
147
Idcode
147
Table 9.4 System Controller Device Identification Register
147
Figure 9.6 Device ID Register Format
147
Validate
148
Reserved
148
Usage Considerations
148

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IDT 89HPES16T4G2 Preliminary User's Manual (149 pages)

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