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89HPES34H16
IDT 89HPES34H16 Manuals
Manuals and User Guides for IDT 89HPES34H16. We have
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IDT 89HPES34H16 manual available for free PDF download: User Manual
IDT 89HPES34H16 User Manual (182 pages)
PCI Express
Brand:
IDT
| Category:
Switch
| Size: 1.12 MB
Table of Contents
User Manual
1
About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
7
List of Tables
11
PES34H16 Device Overview
19
Introduction
19
List of Features
19
Figure 1.1 PES34H16 Architectural Block Diagram
20
Logic Diagram
21
Table 1.6 System Pins
21
Figure 1.2 PES34H16 Logic Diagram
21
System Identification
22
Vendor ID
22
Device ID
22
Revision ID
22
Jtag ID
22
Ssid/Ssvid
22
Device Serial Number Enhanced Capability
22
Pin Description
23
Table 1.3 PCI Express Interface Pins
23
Table 1.4 Smbus Interface Pins
25
Table 1.5 General Purpose I/O Pins
25
Table 1.7 Test Pins
29
Pin Characteristics
30
Table 1.8 Power and Ground Pins
30
Table 1.9 Pin Characteristics
30
Port Configuration
33
Figure 1.3 All Ports Unmerged Configuration
33
Disabled Ports
34
Figure 1.4 Three Ports Merged Configuration
34
Upstream Port Failover
35
Introduction
35
Figure 2.1 Upstream Port Failover Architecture
35
Failover
36
Figure 2.2 Upstream Failover Mode Data Configurations
36
Dynamic Upstream Port Failover
37
Static Upstream Port Failover
37
Clocking, Reset, and Initialization
41
Introduction
41
Table 3.1 Reference Clock Mode Encoding
41
Figure 3.1 Common Clock on Upstream and Downstream
41
Figure 3.2 Non-Common Clock on Upstream; Common Clock on Downstream
42
Figure 3.3 Common Clock on Upstream; Non-Common Clock on Downstream
42
Table 3.2 Boot Configuration Vector Signals
43
Figure 3.4 Non-Common Clock on Upstream and Downstream
43
Reset
44
Fundamental Reset
45
Hot Reset
46
Figure 3.5 Fundamental Reset in Transparent Mode with Serial EEPROM Initialization
46
Upstream Secondary Bus Reset
47
Downstream Secondary Bus Reset
48
Downstream Port Reset Outputs
48
Power Enable Controlled Reset Output
49
Power Good Controlled Reset Output
49
Figure 3.6 Power Enable Controlled Reset Output Mode Operation
49
Figure 3.7 Power Good Controlled Reset Output Mode Operation
49
Link Operation
51
Introduction
51
Polarity Inversion
51
Link Width Negotiation
51
Lane Reversal
51
Figure 4.1 Unmerged Port Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth[5:0]=0X4)
52
Figure 4.2 Unmerged Port Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth[5:0]=0X2)
52
Figure 4.3 Merged Port Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth[5:0]=0X2)
53
Figure 4.4 Merged Port Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth[5:0]=0X4)
53
Link Retraining
54
Figure 4.5 Merged Port Lane Reversal for Maximum Link Width of X8 (Maxlnkwdth[5:0]=0X8)
54
Link down
55
Slot Power Limit Support
55
Upstream Port
55
Downstream Port
55
Link States
55
Active State Power Management
56
Link Status
56
Figure 4.6 PES34H16 ASPM Link Sate Transitions
56
General Purpose I/O
57
Introduction
57
Table 5.1 General Purpose I/O Pin Alternate Function
57
GPIO Configuration
58
GPIO Pin Configured as an Input
58
GPIO Pin Configured as an Output
58
GPIO Pin Configured as an Alternate Function
58
Table 5.2 GPIO Pin Configuration
58
Smbus Interfaces
59
Introduction
59
Figure 6.1 Smbus Interface Configuration Examples
59
Master Smbus Interface
60
Initialization
60
Serial EEPROM
60
Table 6.1 Serial EEPROM Smbus Address
60
Table 6.2 PES34H16 Compatible Serial Eeproms
61
Figure 6.2 Sequential Double Word Initialization Sequence Format
62
Figure 6.3 Configuration Done Sequence Format
62
Figure 6.4 Serial EEPROM Initialization Errors
63
I/O Expanders
64
Figure 6.5 I/O Expander Function Allocation
64
Figure 6.6 I/O Expander Default Output Signal Value
65
Table 6.3 I/O Expander 0 Signals
68
Table 6.4 I/O Expander 1 Signals
69
Table 6.5 I/O Expander 2 Signals
69
Table 6.6 I/O Expander 3 Signals
70
Table 6.7 I/O Expander 4 Signals
71
Table 6.8 I/O Expander 5 Signals
71
Table 6.9 I/O Expander 6 Signals
72
Table 6.10 I/O Expander 7 Signals
73
Table 6.11 I/O Expander 8 Signals
73
Table 6.12 I/O Expander 9 Signals
74
Slave Smbus Interface
75
Initialization
75
Table 6.13 I/O Expander 10 Signals
75
Table 6.14 Slave Smbus Address When a Static Address Is Selected
75
Smbus Transactions
76
Table 6.15 Slave Smbus Command Code Fields
76
Figure 6.7 Slave Smbus Command Code Format
76
Table 6.16 CSR Register Read or Write Operation Byte Sequence
77
Table 6.17 CSR Register Read or Write CMD Field Description
78
Figure 6.8 CSR Register Read or Write CMD Field Format
78
Table 6.18 Serial EEPROM Read or Write Operation Byte Sequence
79
Table 6.19 Serial EEPROM Read or Write CMD Field Description
79
Figure 6.9 Serial EEPROM Read or Write CMD Field Format
79
Figure 6.10 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
80
Figure 6.11 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC Disabled
81
Figure 6.12 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
81
Figure 6.13 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
81
Figure 6.14 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
81
Figure 6.15 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
82
Power Management
83
Introduction
83
Figure 7.1 PES34H16 Power Management State Transition Diagram
83
PME Messages
84
Power Express Power Management Fence Protocol
84
Table 7.1 PES34H16 Power Management State Transition Diagram
84
Power Budgeting Capability
85
Hot-Plug and Hot-Swap
87
Introduction
87
Figure 8.1 Hot-Plug on Switch Downstream Slots Application
87
Figure 8.2 Hot-Plug with Switch on Add-In Card Application
88
Figure 8.3 Hot-Plug with Carrier Card Application
88
Table 8.1 Downstream Port Hot-Plug Signals
89
Hot-Plug I/O Expander
90
Hot-Plug Interrupts and Wake-Up
90
Legacy System Hot-Plug Support
90
Figure 8.4 PES34H16 Hot-Plug Event Signalling
91
Hot-Swap
92
Configuration Registers
93
Configuration Space Organization
93
Table 9.1 Base Addresses for Port Configuration Space Registers
93
Figure 9.1 Port Configuration Space Organization
94
Table 9.2 Upstream Port 0 Configuration Space Registers
95
Upstream Port (Port 0)
95
Downstream Ports (Ports 1 through 15)
100
Table 9.3 Downstream Ports 1 through 15 Configuration Space Registers
100
Register Definitions
103
Type 1 Configuration Header Registers
103
PCI Express Capability Structure
114
Power Management Capability Structure
127
Message Signaled Interrupt Capability Structure
128
Subsystem ID and Subsystem Vendor ID
130
Extended Configuration Space Access Registers
130
Advanced Error Reporting (AER) Enhanced Capability
131
Device Serial Number Enhanced Capability
138
PCI Express Virtual Channel Capability
139
Power Budgeting Enhanced Capability
149
Switch Control and Status Registers
151
Internal Switch Error Control and Status Registers
168
JTAG Boundary Scan
173
Introduction
173
Test Access Point
173
Signal Definitions
173
Table 10.1 JTAG Pin Descriptions
174
Boundary Scan Chain
175
Table 10.2 Boundary Scan Chain
175
Test Data Register (DR)
177
Boundary Scan Registers
177
Instruction Register (IR)
179
Extest
180
Sample/Preload
180
Bypass
180
Table 10.3 Instructions Supported by Pes34H16'S JTAG Boundary Scan
180
Clamp
181
Idcode
181
Validate
181
Reserved
181
Table 10.4 System Controller Device Identification Register
181
Usage Considerations
182
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