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IDT CPS-16 User Manual

Central packet switch
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IDT
CPS-16/12/8
Central Packet Switch

User Manual

Revision 1.5
July 10, 2012

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Summary of Contents for IDT CPS-16

  • Page 1: User Manual

    CPS-16/12/8   Central Packet Switch User Manual Revision 1.5 July 10, 2012...
  • Page 2 IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree.

  • Page 3: Table Of Contents

    Reference Clock ........................7-1 Reference Clock Specification ..................7-1 PLL..........................7-1 Programming the Device ......................8-1 Device Access ......................8-1 Route Tables ........................8-3 Device Programming ....................8-9 Example of Programming ..................8-12 Optional API Calls......................8-13 CPS-16/12/8 User Manual July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 4 Register Type Field Definitions ..................10-1 10.3 Address Map......................10-2 10.4 Rapid IO Registers.....................10-8 10.5 RIO extended feature registeR ................10-19 10.6 IDT Specific sRIO Extended Feature Set ..............10-24 10.7 Routing Table Registers...................10-25 10.8 Trace Registers......................10-26 10.9 Global Configuration Registers ................10-31 10.10 Multicast Registers....................10-38 10.11 Switching Port Registers..................10-40...
  • Page 5 JTAG Write Access......................6-3 Figure 6.2 JTAG Read Access ......................6-3 Figure 7.1 Reference Clock Representative Circuit................7-1 Figure 7.2 Internal PLL Clock Generator ...................7-2 Figure 8.1 Route Table Lookup Diagram...................8-3 CPS-16/12/8 User Manual July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 6 Table 10.17 STD_RTE_DEFAULT_PORT 0x000078................ 10-16 Table 10.18 MCAST_MASK_PORT 0x000080 ................. 10-17 Table 10.19 MCAST_ASSOC_SEL_CSR 0x000084 ................ 10-17 Table 10.20 MCAST_ASSOC_OP_CSR 0x000088 ................10-18 Table 10.21 PORT_MAINT_BLOCK_HEAD 0x000100..............10-18 CPS-16/12/8 User Manual July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 7 IDT List of Tables Table 10.22 PORT_LINK_TO_CTRL_CSR 0x000120 ..............10-18 Table 10.23 PORT_GEN_CTRL_CSR 0x00013C................10-19 Table 10.24 RIO Extended Register Map..................10-19 Table 10.25 PORT_0_LINK_MAINT_REQ_CSR 0x000140 ............. 10-20 Table 10.26 PORT_0_LINK_MAINT_RESP_CSR 0x000144 ............10-20 Table 10.27 PORT_0_LOCAL_ACKID_CSR 0x000148..............10-21 Table 10.28 PORT_0_ERR_STAT_CSR 0x000158 ................
  • Page 8 IDT List of Tables Table 10.77 SPECIAL_ERR_0 0xFD0008 ..................10-48 Table 10.78 ERR_FLAG 0xFD0028 ....................10-50 Table 10.79 ERR_COUNTER 0xFD002C ..................10-50 Table 10.80 ERR_RESET 0xFD0030....................10-51 Table 10.81 QUAD_CTRL Control Register Map ................10-52 Table 10.82 QUAD_0_CTRL 0xFF0000.................... 10-52 Table 10.83...
  • Page 9 This user reference manual includes hardware and software information for the CPS family products. It applies to CPS-16, CPS-12, and CPS-8. The only deference is port number, device ID and register map file. The pinout is covered in each individual datasheet. All the description through out the user manual is default as CPS-16.
  • Page 10 IDT About This Manual vention. A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.   The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD. The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

  • Page 11: Device Overview

    The device supports priority levels 0 - 3 as defined in the revision 1.3 Rapid IO specifications. The CPS device is programmable by RIO ports, I C JTAG interface. CPS-16/12/8 User Manual 1 - 1 July 10, 2012 Revision 1.5...

  • Page 12: Key Features

    In addition to this User’s Reference Manual, which explains the functionality of the CPS and how to use the device. There is the device’s datasheet which covers all electrical specifications, package pinouts, and ther- mal characteristics available on IDT’s secure access site. Contact your local IDT sales representative to obtain your copy.

  • Page 13: Block Diagram

    Lane 5 Lane 11 Quad 1 SRIO Logical SERDES Lane 6 Maintenance & SRIO Error SERDES Lane 7 Management Register JTAG File Figure 1.1 Block Diagram CPS-16/12/8 User Manual 1 - 3 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 14: Application Example: The Wireless Basestation

    It’s also suitable in processing card since more and more processing is moved from RNC to Node B in the emerging applica- tions. CPS-16/12/8 User Manual 1 - 4 July 10, 2012 Revision 1.5...

  • Page 15: Functional Overview

    IDT Device Overview 1.6 FUNCTIONAL OVERVIEW The user may program IDT’s CPS to direct incoming packet data with a given destination ID to a packet processor. Input packets are switched as defined by the transport layer of RIO specification. The CPS receives the packets from up to 16 unique ports, the received packets may be processed in three ways: a.

  • Page 16: Srio Ports

    Quad Mode (1x Capacity) Configuration Enhanced Enhanced 4 by 1x Enhanced Enhanced Enhanced Enhanced 4 by 1x Enhanced Enhanced Enhanced Enhanced 4 by 1x Enhanced Enhanced CPS-16/12/8 User Manual 2 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 17: Table 2.2 Port Configuration Examples

    For the CPS device, control of each of these parameters are separately configurable, such that the charac- teristics for lanes 0 and 1 can be different from those for land 2 and 3 CPS-16/12/8 User Manual 2 - 2 July 10, 2012 Revision 1.5...

  • Page 18: Trace Function

    Each port supports the ability to compare a configurable set of parameters in a given received packet against a set of configurable predefined values and, if a match occurs, routes the packet to a configurable output port. This function is defined as the “Trace” function. CPS-16/12/8 User Manual 2 - 3 July 10, 2012 Revision 1.5...

  • Page 19: Figure 2.1 Trace Matching Criteria

    A packet which matches any of the four values are forwarded to the trace enabled output port as well as any other ports referenced by the packet’s destination ID. The Trace Criteria architecture is illustrated in the diagram below. CPS-16/12/8 User Manual 2 - 4 July 10, 2012 Revision 1.5...

  • Page 20: Figure 2.2 Illustration Of The Trace Function Within A Given Port

    The trace port needs to be disable first before changing to a new trace port. 2.2.3 Trace Routing Features CPS routing function in support of the trace function is provided in two modes. CPS-16/12/8 User Manual 2 - 5 July 10, 2012 Revision 1.5...
  • Page 21 (non-trace) path through the device, then the packet must be NACKed and NOT transmitted via the normal route output port. CPS-16/12/8 User Manual 2 - 6 July 10, 2012 Revision 1.5...

  • Page 22: Packet Filtering

    In the case where packet does not match the filter and TRACE_OUTPUT_PORT_MODE is set to a 1, the packet will not be routed to the destined port. IDT recommends to set the TRACE_OUTPUT_PORT_MODE to 0 when only packet filtering is enabled.
  • Page 23 3) If the port has outstanding ack IDs and the written value is not one of them an error will be recorded and the port will take no action. CPS-16/12/8 User Manual 2 - 8 July 10, 2012 Revision 1.5...

  • Page 24: Switch Description

    Inside each QUAD, TDM connects each port to PVC. Figure 3.1 CPS Switch Core Block Diagram CPS-16/12/8 User Manual 3 - 1 July 10, 2012 Revision 1.5...

  • Page 25: Figure 3.2 Input Buffer Diagram

    The extended packet tracking function allows input buffer keep track up to 8 packet per priority. (See register 0xF40004 bit 18). It is typically for small packet application. When the extended packet tracking function is enabled, the non-blocking within the priority function will be disabled automatically. CPS-16/12/8 User Manual 3 - 2 July 10, 2012 Revision 1.5...

  • Page 26: Switching Scheduler And Priorities

    In another words, one blocked desti- nation port of the multicast list will not block the forwarding to other destination ports (multicast splitting), but it does hold the input buffer resource. CPS-16/12/8 User Manual 3 - 3 July 10, 2012 Revision 1.5...
  • Page 27 They may be filled with 4 unicast packets, 4 multicast packets, or any combination of unicast and multi- cast packets. CPS-16/12/8 User Manual 3 - 4 July 10, 2012 Revision 1.5...

  • Page 28: Flow Control And Congestion Management

    Quick transportation and quick response minimize the buffer dimension. 3.5.2 Flow Control External The CPS family SRIO port supports receiver based flow control. (See sRIO spec for detail information about receiver based flow control) CPS-16/12/8 User Manual 3 - 5 July 10, 2012 Revision 1.5...

  • Page 29: Overview

    C port can be thought of primarily as a control plane access point for the CPS-16/12/8. An external device such as a host processor can use it to access the CPS-16/12/8’s registers. The port can also be used by the CPS-16/12/8 to load registers.
  • Page 30 (successfully or unsuccessfully), it reverts to slave mode (where the ADS signal will become active). 4.3.3 Master Clock Frequency While in the Master mode, the CPS-16/12/8 can be configured to supply a clock of either 100 kHz (Standard mode) or 400 kHz (Fast mode). 4.3.4 Register Map The device’s register map is based on the concept of configuration blocks whose definition and...

  • Page 31: Table 4.1 Eeprom Register Address Map

    Block 2. entered here is m-1. n + 1 Bits 8:9 of the 10-bit block count n + 1 Bits 0:5 of the block address CPS-16/12/8 User Manual 4 - 3 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 32 The CRC is calculated using a standard CRC-16 polynomial x16 + x15 + x2 + 1 with an initial value of zero. The algorithm used by the CPS-16/12/8 to calculate the CRC differs from standard CRC algorithms in that the standard CRC algorithm normally pads the data by the width of the CRC as a final 16 bits of data to shift through the algorithm.

  • Page 33: Table 4.2 Register Map Example

    0x00600000 Block 1 0xE00000 0x01 Block 2 0xE00004 0x02 0xE00008 0x03 0xE0000C 0x04 0xE00010 0x05 0xE00014 0x06 0xE00018 0x07 0xE0001C 0x08 0x6c 0x14 Block 3 CPS-16/12/8 User Manual 4 - 5 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 34: Table 4.3 Eeprom Format Example

    0xE00008 0x0013 0x04 Data for address 0xE00010 0x0014 0x05 Data for address 0xE00014 0x0015 0x06 Data for address 0xE00018 0x0016 0x07 Data for address 0xE0001C CPS-16/12/8 User Manual 4 - 6 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 35: Slave Mode

    0x46 Slave Mode When the CPS-16/12/8 is configured as a slave, its physical device address is defined by 10 external pins, ID[9:0]. The device can operate as either a 10-bit or 7-bit addressable device, as defined by an additional external pin called ADS. If the ADS pin is tied to V (1.2V), then the device operates as a 10-bit...

  • Page 36: Figure 4.1 Bit Transfer On The I2C Bus

    ID [0] I2C address bit 0 4.4.1 Signaling in Slave Mode Communication with the CPS-16/12/8 in Slave mode on the I C bus supports the following cases: 1. Master device to CPS-16/12/8: a. Master device addresses the CPS-16/12/8 as a slave b.

  • Page 37: Figure 4.3 Data Transfer

    Figure 4.4 Acknowledgment Figure 4.5 Master Addressing a Slave with a 7-bit Address (Transfer Direction is Not Changed) Figure 4.6 Master Reads a Slave Immediately After the First Byte CPS-16/12/8 User Manual 4 - 9 July 10, 2012 Revision 1.5...

  • Page 38: Figure 4.7 Combined Format

    Figure 4.9 Master Addresses a Slave Transmitter with 10-bit Address Figure 4.10 Combined Format: Master Addresses a Slave with 10-bit Address 1.Then transmits data to slave and reads data from slave. CPS-16/12/8 User Manual 4 - 10 July 10, 2012 Revision 1.5...

  • Page 39: Figure 4.11 Combined Format: Master Transmits Data To Two Slaves, Both With 10-Bit Address

    Note that the device address can be configured to any arbitrary value using the external address select pins. A slave address should also be used that is unique to each device on the bus. IDT also recommends to avoid using reserved addresses as specified in the I C Specification, such as CBUS addresses.

  • Page 40: Figure 4.12 Write Protocol With 10-Bit Slave Address (Ads Is 1)

    DATA DATA Input Data Input Data Input Data Input Data [31:24] [23:16] [15:8] [7:0] Figure 4.14 Write Protocol with 7-bit Slave Address (ADS is 0) CPS-16/12/8 User Manual 4 - 12 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 41: Figure 4.15 Read Protocol With 7-Bit Slave Address (Ads Is 0)

    Output Data Output Data Output Data Output Data Address [6:0] [31:24] [23:16] [15:8] [7:0] Figure 4.15 Read Protocol with 7-bit Slave Address (ADS is 0) CPS-16/12/8 User Manual 4 - 13 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 42: Error Management

    Table 5.1 Error Sources and Codes Error Source Code Lane 0 0x2A Lane 1 0x29 Lane 2 0x34 Lane 3 0x33 Lane 4 0x32 Lane 5 0x31 Lane 6 0x3C CPS-16/12/8 User Manual 5 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 43: Table 5.2 I2C Errors And Codes -- Group Number 0X1

    C Errors and Codes -- Group Number 0x1 Error Code Description Length Error 0x10 I2C Transmission has an invalid data payload length (read or write transaction) CPS-16/12/8 User Manual 5 - 2 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 44: Table 5.3 Jtag Errors And Codes -- Group Number 0X2

    Table 5.3 JTAG Errors and Codes -- Group Number 0x2 Error Code Description Incomplete Write 0x20 Unexpected termination of write data to registers if serial data input is not 32 bit aligned CPS-16/12/8 User Manual 5 - 3 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 45: Table 5.4 Maintenance Handler Errors And Codes -- Group Number 0X3

    Maintenance packet 0x36 Triggered if a Maintenance packet is received which exceeds exceeds maximum payload the RIO specified maximum payload size for maintenance packets CPS-16/12/8 User Manual 5 - 4 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 46: Table 5.5 Configuration Errors And Codes -- Group Number 0X5

    Triggered if the above scenario occurs during a write of the CPSC_INPUT_PORTS and CPSC_OUTPUT_PORTS registers as well. CPS-16/12/8 User Manual 5 - 5 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 47: Table 5.6 Rio Serdes Errors And Codes -- Group Number 0X6

    0. If the quad is in 1x mode then an error detected in lane i will be reported in port i. Reported only when Port_err_report is enabled. Invalid outstanding 0x72 Triggered when an invalid outstanding ackID packet received. ackID Received CPS-16/12/8 User Manual 5 - 6 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 48: Table 5.8 Rio Link Protocol Errors And Codes -- Group Number 0X8

    0x8B Triggered when a link response control symbol is received with an with invalid AckID invalid AckID. Reported only when Port error reporting is enabled. CPS-16/12/8 User Manual 5 - 7 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 49: Table 5.9 Rio Logical And Transport Errors And Codes -- Group Number 0X9

    This error code is a logical or of the errors represented by codes 0x92 through 0x95 and of those repre- sented by codes 0x 9A through 0x9D CPS-16/12/8 User Manual 5 - 8 July 10, 2012 Revision 1.5...
  • Page 50 Flag Register bits such that, if any one of the error flag bits are set, the Interrupt pin is driven to its low voltage state. Open-drain allows multiple such devices to be connected to a single bus, likely to an interrupt input of a host processor. CPS-16/12/8 User Manual 5 - 9 July 10, 2012 Revision 1.5...
  • Page 51 Code, 3) the Error Flag Register contents (8-bits), and 4) the Error Counter Register value (16-bit). Each maintenance packet type is a “port-write” packet as defined in the applicable RIO specifications and will carry one 64-bit data word. It supports the following payload layout: CPS-16/12/8 User Manual 5 - 10 July 10, 2012 Revision 1.5...

  • Page 52: Table 5.10 Port Write Payload Definition

    LARGE_TRANS field in the RIO_PORT_WRITE_INFO register ttype (transaction) = 0b0100 vii. rdsize/wrsize = 0b1011 viii. Hop_Count = 0xFF W (wptr) = 0b0 CPS-16/12/8 User Manual 5 - 11 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 53: Jtag & Boundary Scan

    Access (CRA) capability. For the full specification, please refer to the device’s datasheet. The CPS-16/12/8’s JTAG functionality does not support register access when it is part of a chain, and must be the only device on the JTAG bus when its registers are accessed using JTAG interface.

  • Page 54: Device Id Register

    IDT JTAG & Boundary Scan Table 6.1 Test Instructions IR Code [3:0] Instruction Comments Die_Signature Dumps fab information including die location, version, and wafer number Bypass Implemented per IEEE 1149.1-2001 6.3 DEVICE ID REGISTER The JTAG Device ID register length is 32 bits wide. The Capture Data Register value is the Device ID.

  • Page 55: Boundary Scan

    IDT JTAG & Boundary Scan 6.5.1 Configuration Register Access -- Writes When bit 0 of the data stream is 0, data shifted in after the address is written to the address specified in jtag_config_addr. The TDO pin will transmit all 0s. Timing is shown below.

  • Page 56: Reference Clock

    The resultant PHY_CLK is also divided by 5 for the byte time of the internal parallel data. If half clock is applied to the reference clock, all the output clocks are changed to half frequency. CPS-16/12/8 User Manual 7 - 1 July 10, 2012 Revision 1.5...

  • Page 57: Figure 7.2 Internal Pll Clock Generator

    PHY_CLK (625 MHz) x4/5 Byte_CLK (125 MHz) PHY_CLK (1.25 GHz) x8/5 Byte_CLK (250 MHz) PHY_CLK (1.56 GHz) x10/5 Byte_CLK (312 MHz) Figure 7.2 Internal PLL Clock Generator CPS-16/12/8 User Manual 7 - 2 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 58: Programming The Device

    AckID rsvd Prio ftype = 0b1000 destination ID source ID ttype rdsize/wrtsize Source Transaction ID srcTID Hop_Count Config_Offset [20:13] Config_Offset [12:0] 0b00 Data Data......................Data Data CPS-16/12/8 User Manual 8 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 59: Table 8.2 Rio Defined Maintenance Response Packet Generated By Cps

    IDT Programming the Device As the response to a Maintenance Request Packet, a Maintenance Response Packet is created using the format below with the hop_count field set to 0xFF. Responses are sent via the port on which the Mainte- nance Packet was received.

  • Page 60: Route Tables

    IDT Programming the Device 8.2 ROUTE TABLES 8.2.1 Route Tables The CPS device provides route tables which are used to determine the port(s) to which packets must be output. The CPS performs lookups into these route tables to associate the destination ID of each received packet with an output port configuration.

  • Page 61: Table 8.3 Port Configuration

    IDT Programming the Device When a packet is received, the CPS decodes the tt field to determine if the destination ID is 16 bits or 8 bits. If the tt field indicates that the destination ID is 16 bits: 1) The CPS divides the field into two 8-bit fields -- the domain ID and the device ID.
  • Page 62 0x001070). The first two registers listed above are implemented as defined in the RIO Part 3 rev 1.3 Speci- fication. The third listed register is an IDT specific RIO register which is used to determine which route tables are referenced for a given access request.

  • Page 63: Table 8.4 Multicast Mask Register References For Multicast Mask Port Csr Usage

    IDT Programming the Device 8.2.5.2 Direct Route Table Programming (IDT Standard Route Programming) The CPS device supports direct programming of the route tables without using the RIO CSRs described above. There is global route table (0xE00000 - 0xE00400) and per-port route table (Port0: 0xE10000 - 0xE10400).

  • Page 64: Table 8.5 Region Select

    IDT Programming the Device Table 8.4 Multicast Mask Register References for Multicast Mask Port CSR Usage Mask Register 8.2.7 Destination Address to Route Table Mapping CPS use Destination Addresses in the route tables in order to determine the proper output mapping of a given packet.

  • Page 65: Table 8.7 Multicast Mask References

    IDT Programming the Device Table 8.6 Port Number References Port Number Port number references are supported in both the Domain Route Table and the Device Route table. 8.2.7.2 Multicast Mask References The device supports the ability to multicast packets to multiple output ports. In support of this, the Multicast Mask Registers must be referenced in the Device Route Table.

  • Page 66: Device Programming

    IDT Programming the Device 8.2.7.5 Force Local The CPS supports “force local” references in its Domain Route Table. A Force Local reference of 0xDD in the Domain Route Table forces a lookup with the 8 lower (lsb) bits of the destination ID in the Device Route Table.
  • Page 67 IDT Programming the Device The ackid queue in the input side of the port which buffers up the ackids of packets received is cleared. This queue buffers up the ackids for which the port must send packet-accept control symbols. 8. Detectable errors on control symbols or packets received by the port in the cycle in which the local soft reset event occurs are suppressed from being asserted.

  • Page 68: Reset Configuration

    IDT Programming the Device to favorable values (typically zero) before the clocks are gated off. In this way, when the register clocks are restored, there will not be any stale values in the registers that could cause the port logic to behave in expected ways.

  • Page 69: Example Of Programming

    IDT Programming the Device 8.3.6 Quad Configuration (PHY Layer) The physical layer ports on the CPS are next to be programmed. Doing so establishes the port configura- tion, and the CPS’s response to sRIO reset control symbols. This functionality is controlled through three...

  • Page 70: Optional Api Calls

    IDT Programming the Device 8.5 OPTIONAL API CALLS The IDT API fully supports all calls necessary to control the CPS’s switch functionality as detailed above. These high level calls include the following: Configure_Quads  – This call passes the appropriate parameterized data structure per standard sRIO HAL require- ments.

  • Page 71: Reset & Initialization

    Enhanced 1x Enhanced 1x CPS-8 Enhanced 1x Enhanced 1x Enhanced 1x Enhanced 1x Enhanced 1x CPS-12 Enhanced 1x Enhanced 1x Enhanced 1x Enhanced 1x CPS-16 CPS-16/12/8 User Manual 9 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 72: Initialization Steps

    IDT Reset & Initialization The device provides two external pins, (SPD0 and SPD1) which determines the initial (default) port speed. These pins support the configurations defined below: Table 9.2 Default Speed Settings with SPD0 and SPD1 SPD1/SPD0 States Port Speed 1.25 Gbits/sec...

  • Page 73: Registers

    Fixed Read. The values in these registers are fixed and can be only read from an external device. Write Once Reset. CPS-16/12/8 User Manual 10 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 74: Address Map

    0x000088 MCAST_ASSOC_OP_CSR 0x000100 - 0x0002BC RIO Extended Feature Registers 0x000100 PORT_MAINT_BLK_HEAD 0x000120 PORT_LINK_TIME_OUT_CTRL_CSR 0x00013C PORT_GEN_CTRL_CSR 0x000140 PORT_0_LINK_MAINT_REQ_CSR 0x000144 PORT_0_LINK_MAINT_RESP_CSR 0x000148 PORT_0_LOCAL_ACKID_CSR 0x000158 PORT_0_ERR_N_STAT_CSR 0x00015C PORT_0_CTRL_CSR CPS-16/12/8 User Manual 10 - 2 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 75 0xE40064 Port 0 Trace Mask 3 0xE40078 Port 0 Trace Comparison Value 4 0xE4008C Port 0 Trace Mask 4 0xE40000+0x100*PORT_ Registers start for port PORT_NUM CPS-16/12/8 User Manual 10 - 3 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 76 Vendor access only 0xF20014 CONF_MOD_ERR_REPORT_ENABLE 0xF20018 AUXPORT_ERR_REPORT_ENABLE 0xF2001C MAINT_ERR_REPORT_ENABLE 0xF20020 RIO_DOMAIN 0xF20024 RIO_PORT_WRITE_INFO 0xF20028 RIO_PORT_WRITE_SRCID 0xF2002C RIO_ASSY_IDENT_CAR 0xF20030 RIO_ASSY_INF_CAR 0xF20034 Reserved 0xF20038 Reserved 0xF20040 SOFT_RESET 0xF20050 I2C_MASTER_CONTROL CPS-16/12/8 User Manual 10 - 4 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 77 Reserved 0xF4001C PORT_0_SW_PKT_CNTR 0xF40020 PORT_0_TRACE_MATCH_CNTR_1 0xF40024 PORT_0_TRACE_MATCH_CNTR_2 0xF40028 PORT_0_TRACE_MATCH_CNTR_3 0xF4002C PORT_0_TRACE_MATCH_CNTR_4 0xF40030 PORT_0_FILTER_MATCH_CNTR_1 0xF40034 PORT_0_FILTER_MATCH_CNTR_2 0xF40038 PORT_0_FILTER_MATCH_CNTR_3 0xF4003C PORT_0_FILTER_MATCH_CNTR_4 0xF40000+0x100*PORT_ Registers start for port PORT_NUM CPS-16/12/8 User Manual 10 - 5 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 78 Error Handling Registers 0xFD0000 ERR_CAP_REG 0xFD0004 ERR_LOG 0xFD0008 SPECIAL_ERR_REG_0 0xFD000C SPECIAL_ERR_REG_1 0xFD0010 SPECIAL_ERR_REG_2 0xFD0014 SPECIAL_ERR_REG_3 0xFD0018 SPECIAL_ERR_REG_4 0xFD001C SPECIAL_ERR_REG_5 0xFD0020 SPECIAL_ERR_REG_6 0xFD0024 SPECIAL_ERR_REG_7 0xFD0028 ERR_FLAG CPS-16/12/8 User Manual 10 - 6 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 79 ERR_RESET 0xFF0000 - 0xFFF000 Quad Control Registers 0xFF0000 QUAD_0_CTRL 0xFF0004 QUAD_0_ERR_REPORT_EN 0xFF1000 QUAD_1_CTRL 0xFF1004 QUAD_1_ERR_REPORT_EN 0xFF2000 QUAD_2_CTRL 0xFF2004 QUAD_2_ERR_REPORT_EN 0xFF3000 QUAD_3_CTRL 0xFF3004 QUAD_3_ERR_REPORT_EN 0xFFF000 QUAD_CTRL_BROADCAST CPS-16/12/8 User Manual 10 - 7 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 80: Rapid Io Registers

    Field Name Type Comment Value 15 - 0 DEV_VENDOR_IDENT 0x0038 Device Vendor Identifier. Assigned by the RTA specifically for IDT 31 - 16 DEV_IDENT 0x35B Specific Device Identifier. 0x35C 0x35B is for the 16 port version. 0x35D 0x35C is for the 8 port version.

  • Page 81: Table 10.5 Assy_Ident_Car 0X000008

    Pointer to the first entry in the extended features list. 31 - 16 ASSY_REV 0x0000 Assembly revision level. The reader is referred to the RIO_ASSY_INF_CAR CPS-16/12/8 User Manual 10 - 9 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 82 The device can bridge to another Rapid IO interface 1 = bridge support PROCESSOR The device does not provide a pro- cessor that executes code 0 = processor not supported CPS-16/12/8 User Manual 10 - 10 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 83: Table 10.7 Proc_Elem_Feat_Car 0X000010

    For I2C accessed, value is 0xFE. 15 - 8 PORT_TOTAL 0x10 The total number of ports configurable 0x0B through the configuration registers 0x08 CPS-16: 16 ports. CPS-12: 12 ports. CPS-8: 8 ports. 31 - 16 Reserved CPS-16/12/8 User Manual 10 - 11 July 10, 2012 Revision 1.5...

  • Page 84: Table 10.9 Src_Ops_Car 0X000018

    0 = no 1 = yes DATA_MESSAGE Defines the ability of the device to support a data message operation 0 = no 1 = yes CPS-16/12/8 User Manual 10 - 12 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 85: Table 10.10 Sw_Mcast_Sup_Car 0X000030

    Field Name Type Comment Value 30 - 0 Reserved SIMPLE_ASSOC Defines the device’s support of the simple multicast model 0 = no 1 = yes CPS-16/12/8 User Manual 10 - 13 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 86: Table 10.11 Sw_Rte_Tbl_Lim_Car 0X000034

    Field Name Type Comment Value 15 - 0 HOST_BASE_DEV_ID 0xFFFF Base Device ID for the device that ini- tializes this device 31 - 16 Reserved CPS-16/12/8 User Manual 10 - 14 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 87: Std_Rte_Conf_Destid_Sel_Csr 0X000070

    Route Config Port CSR is used. 30 - 16 Reserved EXTENDED_CONFIGURATION_ Extended Configuration Enable. ENABLE 0 = Disable 1 = Enabled CPS-16/12/8 User Manual 10 - 15 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 88: Table 10.16 Std_Rte_Conf_Port_Sel_Csr 0X000074

    Table 10.17 STD_RTE_DEFAULT_PORT 0x000078 Reset Field Name Type Comment Value 7 - 0 DEFAULT_OUTPUT_PORT 0x00 Defines the device’s default output port. 31 - 8 Reserved CPS-16/12/8 User Manual 10 - 16 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 89: Table 10.18 Mcast_Mask_Port 0X000080

    Selects a destination ID for an association operation 31 - 24 LARGE_DESTINATION_ID 0x00 Selects the most significant byte of a large transport destination ID for an association operation CPS-16/12/8 User Manual 10 - 17 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 90: Table 10.20 Mcast_Assoc_Op_Csr 0X000088

    10.4.20 Port Link Time Out Control Command and Status Register (PORT_LINK_TO_CTRL_CSR) Table 10.22 PORT_LINK_TO_CTRL_CSR 0x000120 Reset Field Name Type Comment Value 7 - 0 Reserved 31 - 8 TIME_OUT_VALUE 0xFFFFFF Time out internal value CPS-16/12/8 User Manual 10 - 18 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 91: Rio Extended Feature Register

    0x0002A0- 0x0002BC For PORT 11 0x0002C0- 0x0002DC For PORT 12 0x0002E0- 0x0002FC For PORT 13 0x000300- 0x00031C For PORT 14 0x000320- 0x00033C For PORT 15 CPS-16/12/8 User Manual 10 - 19 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 92: Table 10.25 Port_0_Link_Maint_Req_Csr 0X000140

    If the link request did not cause a link response, this bit indi- cates that the link request has been trans- mitted. This bit clears on read. CPS-16/12/8 User Manual 10 - 20 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 93: Table 10.27 Port_0_Local_Ackid_Csr 0X000148

    This bit should only be written when trying to recover a failed link. This bit will always return a value of zero when read. CPS-16/12/8 User Manual 10 - 21 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 94: Table 10.28 Port_0_Err_Stat_Csr 0X000158

    1 = Serial 3 - 1 Reserved 11 - 4 RETRANSMIT_SUPPRESSION_MASK Mask for retransmission sup- pression 16 - 12 Reserved ENUMERATION_BOUNDARY The enumeration boundary Reserved CPS-16/12/8 User Manual 10 - 22 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 95 001 = single lane port lane 2 010 = 4 Lane Port Others reserved 31 - 30 PORT_WIDTH 0b00 00 = Single Lane Port 01 = 4 Lane Port Others Reserved CPS-16/12/8 User Manual 10 - 23 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 96: Idt Specific Srio Extended Feature Set

    IDT CPS Registers 10.6 IDT SPECIFIC SRIO EXTENDED FEATURE SET 10.6.1 Local Route Configuration Destination ID Select Command and Status Register (LOCAL_RTE_CONF_DESTID_SEL_CSR) Table 10.30 LOCAL_RTE_CONF_DESTID_SEL_CSR 0x010070 Reset Field Name Type Comment Value 4 - 0 PORT_ROUTE_TABLE_SELECTION 0b00000 Defines the port whose route...

  • Page 97: Routing Table Registers

    Field Name Type Reset Value Comment Port_Number 0xDE 0x00 - x0F for unicast port number 0-15. 0x40 - x4F for multicast register 0 - 9 CPS-16/12/8 User Manual 10 - 25 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 98: Trace Registers

    Port 14 Trace Comparison Values and Masks Register 0xE40F00-0xE40F98 Port 15 Trace Comparison Values and Masks Register 0xE4FF00-0xE4FF98 Broadcast Trace Comparison Values and Masks Register CPS-16/12/8 User Manual 10 - 26 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 99: Table 10.34 Port_0_Trace_Value_1_Block_0 0Xe40000

    Bit 31 will be compared to the 33rd packet bit Bit 30 will be compared to the 34th packet bit Bit 0 will be compared to the 64th packet bit CPS-16/12/8 User Manual 10 - 27 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 100: Table 10.36 Port_0_Trace_Value_1_Block_2 0Xe40008

    Bit 31 will be compared to the 97th packet bit Bit 30 will be compared to the 98th packet bit Bit 0 will be compared to the 128th packet bit CPS-16/12/8 User Manual 10 - 28 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 101: Table 10.39 Port_0_Mask_Value_1_Block_0 0Xe40014

    Bit 30 will be a mask for the second comparison bit Bit 0 will be a mask for the 32nd comparison bit CPS-16/12/8 User Manual 10 - 29 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 102: Table 10.42 Port_0_Mask_Value_1_Block_3 0Xe40020

    Bit 31 will be a mask for the 97th comparison bit Bit 30 will be a mask for the 98th comparison bit Bit 0 will be a maks for the 128th comparison bit CPS-16/12/8 User Manual 10 - 30 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 103: Global Configuration Registers

    0xF Defines Port 15 as the Trace Port 10 - 5 Reserved CUT_THRU_ENABLE 0b0: Store and Forward Mode 0b1: Cut Through Mode SYSPLL_HALF_CLK_RATE 0 = PLL/1 1 = PLL/2 Reserved CPS-16/12/8 User Manual 10 - 31 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 104: Table 10.45 Conf_Mod_Err_Report_Enable 0Xf20014

    Table 10.45 CONF_MOD_ERR_REPORT_ENABLE 0xF20014 Reset Field Name Type Comment Value CONF_MOD_ERR_REPORT_ENABLE 0 = Disable Error Reporting 1 = Enable Error Reporting 31 - 1 Reserved CPS-16/12/8 User Manual 10 - 32 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 105: Table 10.46 Auxport_Err_Report_Enable 0Xf20018

    This register is used for the user to define the domain this device belongs to. Table 10.48 RIO_DOMAIN 0xF20020 Field Name Type Reset Value Comment 7 - 0 Domain 0x00 Device Domain Configuration 31 - 8 Reserved CPS-16/12/8 User Manual 10 - 33 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 106: Table 10.49 Rio_Port_Write_Info 0Xf20024

    15 - 0 Reserved 23 - 16 SRCID 0x00 Port-Write source device ID 31 - 24 SRCID_MSB 0x00 MSB of the port-write device ID (Large only) CPS-16/12/8 User Manual 10 - 34 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 107: Table 10.52 Rio_Assy_Inf_Car 0Xf20030

    10.9.10 Soft Reset Register (SOFT_RESET) Table 10.53 PPS_SOFT_RESET 0xF20040 Field Name Type Reset Value Comment 31 - 0 SOFT_RESET Write Only 0x00000000 0x00030097 Resets the part CPS-16/12/8 User Manual 10 - 35 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 108: Table 10.54 I2C_Master_Ctrl 0Xf20050

    SYS_CLK can vary between 75 MHz and 156 MHz. 24 - 23 Reserved MASTER_FREQ_SEL 0 = 400 KHz 1 = 100KHz 31 - 26 Reserved CPS-16/12/8 User Manual 10 - 36 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 109 Reset on read I2C_NACK A value of 1 indicates that an expected ack was not received Reset on read CPS-16/12/8 User Manual 10 - 37 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 110: Multicast Registers

    Base Address (Hex) Associated Registers 0xF30000 MULTICAST0 0xF30004 MULTICAST1 0xF30008 MULTICAST2 0xF3000C MULTICAST3 0xF30010 MULTICAST4 0xF30014 MULTICAST5 0xF30018 MULTICAST6 0xF3001C MULTICAST7 0xF30020 MULTICAST8 0xF30024 MULTICAST9 CPS-16/12/8 User Manual 10 - 38 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 111: Table 10.57 Multicast0 0Xf30000

    0 = Port 15 is not included in Multicast group 0 1 = Port 15 is included in Multicast group 0 31 - 16 Reserved CPS-16/12/8 User Manual 10 - 39 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 112: Switching Port Registers

    0xF40D00-0xF40D3C Switching Port 13 Registers 0xF40E00-0xF40E3C Switching Port 14 Registers 0xF40F00-0xF40F3C Switching Port 15 Registers 0xF4FF00-0xF4FF08 Switching Port Broadcast Register, only first three register valid CPS-16/12/8 User Manual 10 - 40 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 113: Table 10.59 Port_0_Buf_Size 0Xf40000

    1 = Port Write will be gener- ated on a trace match (Active only if bit 6 set to 1) CPS-16/12/8 User Manual 10 - 41 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 114 0 = disable 1 = enable EXTENDED_PKT_RX_ENABLE 0 = Track up to 4 packets 1 = Track up to 8 packets 31 - 18 Reserved CPS-16/12/8 User Manual 10 - 42 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 115: Table 10.61 Port_0_Err_Report_Enable 0Xf40008

    RETRY_ERROR_REPORT_ENABLE 0 = Disable Retry Symbol Received Reporting from Port 1 = Enable Retry Symbol Received Reporting from Port 31 - 3 Reserved CPS-16/12/8 User Manual 10 - 43 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 116: Table 10.62 Port_0_Switch_Buf_Status 0Xf4000C

    Table 10.63 PORT_0_ACK_CNTR 0xF40010 Field Name Type Reset Value Comment 31 - 0 ACK_COUNT 0x00000000 A saturating count of packet acknowledge- ments issued by port 0 CPS-16/12/8 User Manual 10 - 44 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 117: Table 10.64 Port_0_Nack_Cntr 0Xf40014

    Comment 31 - 0 TRACE_COUNT_2 0x00000000 A saturating count of packets at port 0 that have met the defined trace criteria with comparison Value 2 CPS-16/12/8 User Manual 10 - 45 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 118: Table 10.68 Port_0_Trace_Match_Cntr_3 0Xf40028

    Reset Value Comment 31 - 0 FILTER_COUNT_2 0x00000000 A saturating count of packets that have met the defined filter criteria with compari- son Value 2 CPS-16/12/8 User Manual 10 - 46 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 119: Error Registers

    0 = discard further errors when the error log is full 1 = overwrite the error log with new errors when it is full 31 - 3 Reserved CPS-16/12/8 User Manual 10 - 47 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 120: Table 10.75 Err_Log_Rd 0Xfd0004

    13 - 8 ERROR_SOURCE 0x00 Error Source (6 bits) 15 - 14 Reserved STOP_ENABLE Enable Stopping the error management function and generation of a maintenance packet CPS-16/12/8 User Manual 10 - 48 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 121 1 = do not compare the error group ERROR_SOURCE_MASK 0 = compare the error source 1 = do not compare the error source 31 - 23 Reserved CPS-16/12/8 User Manual 10 - 49 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 122: Table 10.78 Err_Flag 0Xfd0028

    10.12.5 Error Counter (ERR_COUNTER) Table 10.79 ERR_COUNTER 0xFD002C Reset Field Name Type Comment Value 15 - 0 COUNT 0x00 The error count 31 - 16 Reserved CPS-16/12/8 User Manual 10 - 50 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 123: Table 10.80 Err_Reset 0Xfd0030

    Stops the error manage- ment function. Setting this bit to 1 will disable all port writes including those that result from trace matches. 31 - 6 Reserved CPS-16/12/8 User Manual 10 - 51 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 124: Quad Control Registers

    010 = Long Haul 100 = Short Haul 111 = Minimum PLL_LANE_0_1_RESET Forces reset of Lanes 0 and 1 0 = Reset 1 = Deassert reset CPS-16/12/8 User Manual 10 - 52 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 125 Transmitter Drive Strength for Lanes 2 and 3. Only active if [16] = 1 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum 31 - 26 Reserved CPS-16/12/8 User Manual 10 - 53 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 126: Quad_0_Err_Report_En 0Xff0004

    010 = Long Haul 100 = Short Haul 111 = Minimum PLL_LANE_0_1_RESET Forces reset of Lanes 0 and 1 0 = Reset 1 = Deassert reset CPS-16/12/8 User Manual 10 - 54 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 127: Table 10.84 Quad_Ctrl_Broadcast 0Xfff000

    3. Only active if [16] = 1 000 = Maximum 010 = Long Haul 100 = Short Haul 111 = Minimum 31 - 12 Reserved CPS-16/12/8 User Manual 10 - 55 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.

  • Page 128: References

    10. IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks 11. IDT80KSW0001 Users Manual and Datasheet. 12. IDT80KSW002 Datasheet 13. The I C-BUS Specification”, version 2.1, January 2000, Philips CPS-16/12/8 User Manual 11 - 1 July 10, 2012 Revision 1.5 Integrated Device Technology, Inc.
  • Page 129 The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

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