IDT PCI Express 89HPES32NT24xG2 Manuals

Manuals and User Guides for IDT PCI Express 89HPES32NT24xG2. We have 1 IDT PCI Express 89HPES32NT24xG2 manual available for free PDF download: User Manual

IDT PCI Express 89HPES32NT24xG2 User Manual

IDT PCI Express 89HPES32NT24xG2 User Manual (744 pages)

Brand: IDT | Category: Switch | Size: 4.18 MB

Table of Contents

About this Manual

3
- Content Summary
  3
- Signal Nomenclature
  4
- Numeric Representations
  5
- Data Units
  5
- Register Terminology
  6
- Use of Hypertext
  7
- Reference Documents
  7
- Revision History
  7
- Table of Contents
  11
Pes32Nt24Xg2 Device Overview

37
Clocking

57
Reset and Initialization

65
Switch Core

79
Switch Partition and Port Configuration

101
Failover

125
- Overview
  125
- Failover Initiation
  125
Notes

129
Link Operation

129
- Overview
  129
- Port Merging
  129
- Port Maximum Link Width
  129
- Polarity Inversion
  130
- Lane Reversal
  130
- Figure 7.1 Lane Reversal for Highest Achievable Link Width of X2
  130
- Figure 7.2 Lane Reversal for Highest Achievable Link Width of X4
  131
- Link Width Negotiation
  132
  - Figure 7.3 Lane Reversal for Highest Achievable Link Width of X8
    132
  - Link Width Negotiation in the Presence of Bad Lanes
    133
- Dynamic Link Width Reconfiguration
  133
  - Dynamic Link Width Reconfiguration in the Pes32Nt24Xg2
    134
- Link Speed Negotiation
  134
  - Link Speed Negotiation in the Pes32Nt24Xg2
    135
  - Software Management of Link Speed
    136
- Link Retraining
  137
- Link States
  137
- Link down Handling
  138
- Figure 7.4 Pes32Nt24Xg2 ASPM Link State Transitions
  138
- Slot Power Limit Support
  139
  - Upstream Port
    139
  - Downstream Switch Port
    140
- Link Active State Power Management (ASPM)
  140
  - L0S ASPM
    140
  - L1 Aspm
    141
- Link Status
  144
- De-Emphasis Negotiation
  144
- Crosslink
  145
- Gen 1 Compatibility Mode
  146
- Table 7.2 Gen 1 Compatibility Mode: Bits Cleared in Training Sets
  146
Serdes

149
Power Management

165
Notes

171
Transparent Switch Operation

171
Hot-Plug and Hot-Swap

197
Smbus Interfaces

205
General Purpose I/O

245
- Overview
  245
- GPIO Configuration
  245
  - Input
    245
  - Output
    245
  - Alternate Function
    245
  - Table 13.1 GPIO Pin Configuration
    245
  - Table 13.2 GPIO Alternate Function Pin Assignment
    246
  - Table 13.3 GPIO Alternate Function Pins
    246
Notes

249
Non-Transparent Switch Operation

249
DMA Controller

289
Switch Events

325
- Overview
  325
  - Link up
    326
  - Figure 16.1 Switch Event Detection and Signaling Mechanism
    326
  - Link down
    327
  - Fundamental Reset
    327
  - Hot Reset
    327
  - Failover
    327
  - Global Signals
    328
  - Figure 16.2 Global Signaling Mechanism
    328
  - Port AER Errors
    329
Multicast

331
- Transparent Multicast Operation
  331
- Non-Transparent Multicast Operation
  336
  - NT Multicast Configuration
    337
  - Figure 17.3 Transparent and Non-Transparent Multicast
    337
  - NT Multicast TLP Determination
    338
  - NT Multicast TLP Routing
    338
  - NT Multicast Egress Processing
    339
  - Usage Restrictions
    341
Temperature Sensor

343
- Overview
  343
Register Organization

345
- Overview
  345
- Address Maps
  348
Notes

385
PCI-To-PCI Bridge Registers

385
Proprietary Port Specific Registers

449
- Port Control Register
  449
- Upstream PCI-To-PCI Bridge Interrupt and Signaling
  449
- Port AER Mask Register
  451
- Port Slot Control
  453
- Internal Error Control and Status Registers
  455
- Physical Layer Control and Status Registers
  476
- Request Metering
  480
- WRR Port Arbitration Counts
  481
- Non-Transparent Multicast Overlay
  486
- AER Error Emulation
  488
- Global Address Space Access Registers
  491
NT Endpoint Registers

493
- Type 0 Configuration Header Registers
  493
- PCI Express Capability Structure
  505
- PCI Power Management Capability Structure
  520
- Message Signaled Interrupt Capability Structure
  521
- Subsystem ID and Subsystem Vendor ID
  523
- Extended Configuration Space Access Registers
  523
- Advanced Error Reporting (AER) Extended Capability
  525
- Device Serial Number Extended Capability
  535
- PCI Express Virtual Channel Capability
  536
- ACS Extended Capability
  540
- Multicast Extended Capability
  542
- NT Registers
  545
  - NT Control & Status
    545
  - NT Interrupt and Signaling
    546
  - Internal Error Reporting Masks
    548
  - Doorbell Registers
    556
  - Message Registers
    557
  - BAR Configuration
    559
  - Mapping Table
    577
- Lookup Table
  580
- AER Error Emulation
  581
- Punch-Through Configuration Registers
  584
- NT Multicast
  586
- Global Address Space Access Registers
  587
DMA Function Registers

589
- Type 0 Configuration Header Registers
  589
- PCI Express Capability Structure
  597
- PCI Power Management Capability Structure
  610
- Message Signaled Interrupt Capability Structure
  612
- Extended Configuration Space Access Registers
  613
- Advanced Error Reporting (AER) Extended Capability
  614
- ACS Extended Capability
  625
- DMA Registers
  627
  - BAR Configuration
    627
  - DMA AER Error Emulation
    627
  - Internal Error Reporting Masks
    630
  - DMA Multicast Control
    637
  - DMA Channel Registers
    638
- Global Address Space Access Registers
  647
Switch Configuration and Status Registers

649
- Switch Control and Status Registers
  649
- Internal Switch Timers
  653
- Switch Partition and Port Registers
  655
- Failover Capability Registers
  661
- Protection
  663
- Switch Event Registers
  664
- Global Doorbells and Message Registers
  673
- Serdes Control and Status Registers
  674
- General Purpose I/O Registers
  681
- Hot-Plug and Smbus Interface Registers
  683
- Temperature Sensor Registers
  693
JTAG Boundary Scan

699
- Introduction
  699
- Test Access Point
  699
- Signal Definitions
  699
- Figure 25.1 Diagram of the JTAG Logic
  699
- Table 25.1 JTAG Pin Descriptions
  700
- Figure 25.2 State Diagram of the TAP Controller
  700
- Boundary Scan Chain
  701
- Table 25.2 Boundary Scan Chain
  701
- Test Data Register (DR)
  704
- Instruction Register (IR)
  706
  - Figure 25.5 Diagram of Bidirectional Cell
    706
  - Bypass
    707
  - Extest
    707
  - Sample/Preload
    707
  - Table 25.3 Instructions Supported by the JTAG Boundary Scan
    707
  - Clamp
    708
  - Extest_Train
    708
  - Figure 25.6 Device ID Register Format
    708
  - Idcode
    708
  - Table 25.4 System Controller Device Identification Register
    708
  - Validate
    708
  - Extest_Pulse
    709
  - Reserved
    709
  - Usage Considerations
    709
Usage Models

711

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