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CPS-1848
IDT CPS-1848 Serial RapidIO Switch Manuals
Manuals and User Guides for IDT CPS-1848 Serial RapidIO Switch. We have
1
IDT CPS-1848 Serial RapidIO Switch manual available for free PDF download: User Manual
IDT CPS-1848 User Manual (450 pages)
Central Packet Switch
Brand:
IDT
| Category:
Switch
| Size: 2.44 MB
Table of Contents
Table of Contents
3
About this Document
17
Content Summary
17
Additional Resources
17
Document Conventions and Definitions
17
Device Revision Information
18
Revision History
18
1 Device Overview
23
Device Description
23
Key Features
23
Block Diagrams
25
Figure 1: CPS-1848 Block Diagram
25
Typical Applications
26
Wireless Application Benefits
26
Figure 2: CPS-1848 Interconnect Diagram
26
Figure 3: Wireless Application
26
Defense and Aerospace Application Benefits
27
Video and Imaging Application Benefits
27
Figure 4: Military Open VPX System Application
27
Figure 5: Video and Imaging Application
27
2 Rapidio Ports
28
Overview
28
Key Features
29
Figure 6: S-RIO Port Diagram
29
Packet Routing
30
Packet Routing Overview
30
Figure 7: Routing Table Flowchart
30
Unicast Programming Model
31
Table 1: Route Table Reference Restrictions
31
Multicast Programming Model
33
Programming Examples
34
Table 2: Unicast Programming Examples - Indirect Programming
34
Table 3: Unicast Programming Examples - Direct Programming
36
Table 4: Multicast Programming Examples - Indirect Programming Model
37
Flow Control
38
Transmitter- and Receiver-Controlled Flow Control Programming Model
38
Table 5: Multicast Programming Examples - Direct Programming Model
38
Multicast Event Control Symbols
39
Port Reconfiguration Operations
39
Table 6: Port Reconfiguration Operations
39
Disabling IDLE2 Operation
40
Reset Control Symbol Processing
40
Per-Port Reset
40
Table 7: Disabling IDLE2 Operation on Port 3
40
Port Disable/Enable
42
Generating a Reset Request
42
Hot Extraction/Insertion
42
Hot Extraction
43
Controlled Removal/Reset
43
Table 8: Preparation for Hot Extraction on Port y
44
Table 9: Preparation for Hot Insertion on Port y
45
Table 10: Preparation of Port that Can be Subjected to Unexpected Hot Extraction Event
47
Link Partner Insertion
48
Table 11: System Recovery Controller Operation, HS-LP on Port y
49
Table 12: HS-LP Recovery Controller
50
Packet Trace and Filtering
53
Packet Trace
53
Figure 8: Trace Criteria
53
Figure 9: Trace Function Within a Port
54
Packet Filtering
57
Packet Generation and Capture
57
Packet Generation and Capture Mode Overview
58
Figure 10: System Connectivity Test in PGC Mode - Transmitted Directly to Link Partner
58
Packet Generation and Capture Mode Programming Model
59
Figure 11: System Testing Using PGC Mode - Cabled Loopback through Serdes
59
Table 13: PGC Mode Example - Connectivity Test
59
Packet Transfer Validation and Debug
62
Overview
62
Successful Packet Transfer
63
Switch Cannot Accept Packets
63
Table 14: Success Case Packet Transfer Counters
63
Table 15: Packet Counters and Configuration Issues - Switch Cannot Accept Packets
63
Table 16: Configuration and Status Values to Check - Switch Cannot Accept Packets
64
Switch Is Not Routing Packets Correctly
65
Table 17: Packet Counters and Configuration Issues - Switch Is Not Routing Packets Correctly
65
Switch Cannot Transmit Packets
66
Table 18: Packet Counters and Configuration Issues - Switch Cannot Transmit Packets
66
Table 19: Configuration and Status Values to Check - Switch Cannot Transmit Packets
67
Requesting Debug Assistance
68
3 Rapidio Lanes
69
Figure 12: S-RIO Lane Block Diagram
69
Lane to Port Mapping
70
Table 20: Lane to Port Mapping
70
Table 21: PWIDTH_OVRD Examples
72
Lane and Port Speeds
73
Lane Speed Change Examples
73
Table 22: Changing Lane Speed Group on Ports 0 and 12 - Example 1
74
Table 23: Changing Lane Speed on Port 5 - Example 2
74
Lane, PLL, and Port Power-Down
75
Port and Lane Initialization Sequence
75
Signal Quality Optimization
76
Figure 13: Optimizing Lane Signal Quality
76
Table 24: Configuring Bit Error Measurement
81
Loopback Capabilities
82
Figure 14: Loopback Locations
82
Lane Loopback Modes
83
Port Loopback Mode
83
Bit Error Rate Testing
84
PRBS Polynomials
84
User-Defined Patterns
84
PRBS Pattern Generator
85
PRBS Pattern Checker and Log (Revision C)
85
Table 25: Programming Model for CPS-1848 Data Generation, Link Partner Checking
85
4 Switch Fabric
87
Key Features
87
Switch Fabric Architecture
88
Figure 15: Switch Fabric Block Diagram
88
Input Buffer
89
Input Buffer to Crosspoint Buffer Transfers
89
Table 26: Input Buffer Allocation Mode
89
Multicast Packets
90
Voq Fairness/Starvation Avoidance
90
Crosspoint Buffers
90
Table 27: Crosspoint Buffer Allocation Mode
90
Crosspoint Buffer to Final Buffer Transfers
91
Maintenance Transaction Support
91
Final Buffer
92
Table 28: Final Buffer Allocation
92
5 Performance
93
Overview
93
Throughput
93
Latency
93
Latency Variation
94
Performance Monitoring
94
Figure 16: Latency Example
94
Congestion Detection
95
Resetting Performance Registers
95
Table 29: Performance Monitoring Parameters
95
Traffic Efficiency
95
Performance Measurements
96
Buffer Management Settings
96
Store-And-Forward or Cut-Through Mode
98
Transmitter-Controlled or Receiver-Controlled Flow Control Mode
98
Port-To-Port Performance Characteristics
99
Packet Latency Performance
99
Table 30: 4X/2X/1X Latency Numbers under no Congestion
99
Packet Throughput Performance
100
Table 31: Typical Latency from Receipt of Packet EOP to Packet Accept Issuance
100
Multicast Latency Performance
102
Multicast Throughput Performance
102
Table 32: 4X/2X/1X Multicast Latency Numbers under no Congestion
102
Multicast-Event Control Symbol (MECS) Latency
103
Table 33: 4X/2X/1X Multicast-Event Control Symbol Latency Numbers
103
6 Event Management
104
Event Management Overview
104
Figure 17: Event Management Overview (Revision A/B)
105
Figure 18: Event Management Overview (Revision C)
106
Table 34: Event Management Enable Bits
107
Figure 19: Logical/Transport Layer Error Management Programming Model Flow Chart
108
Logical/Transport Layer Events Overview
108
Figure 20: Standard Physical Layer Error Management Programming Model Flow Chart
109
Physical Layer Error Management Overview
109
Figure 21: Implementation Specific Physical Layer Error Management Programming Model Flow Chart
110
Figure 22: Lane Error Management Programming Model Flow Chart
111
Lane Error Management Overview
111
Figure 23: I2C Error Management Programming Model Flow Chart
112
I2C Error Management Overview
112
Configuration Error Management Overview
113
Event Detection
113
Logical and Transport Layer Events
113
Figure 24: Configuration Error Management Programming Model Flow Chart
113
Table 35: Logical/Transport Layer Event Enable and Information Capture Summary
114
Physical Layer Events
115
Table 36: Physical Layer Events Information Captured Value Descriptions
115
Table 37: Physical Layer "Leaky Bucket" Events and Information Capture Summary
117
Lane Events
124
Table 38: Lane Event Information Captured Value Descriptions
124
Table 39: Lane Event Enable and Information Capture Summary
125
I2C Events
126
JTAG Events (Revision A/B Only)
126
Table 40: I2C Event Enable and Information Capture Summary
126
Table 41: JTAG Event Enable and Information Capture Summary (Revision A/B Only)
126
Configuration Block Events
127
Trace and Filter Events
127
Packet Generation and Capture Mode Events
127
Error Log Events
127
Table 42: Configuration Block Event Enable and Information Capture Summary
127
Figure 25: Error Management Block Architecture
128
Table 43: Event Source Encoding
128
Table 44: Error Codes for Implementation Specific LT Errors
131
Table 45: Error Log Standard Port Error Encoding
131
Table 46: Error Log Implementation Specific Port Error Encoding
132
Table 47: Error Log Lane Level Encoding
135
Table 48: I2C Errors and Codes
135
Table 49: JTAG Errors and Codes (Revision A/B Only)
136
Table 50: Configuration Errors and Codes
136
Table 51: Trace, Filter, and PGC Mode Error Log Encoding
136
Event Notification
137
Logical Layer Events Notification
137
Table 52: Logical/Transport Layer Event Notification Control
138
Physical Layer Events Notification
139
Table 53: Physical Layer Event Notification Control
140
Lane Event Notification
146
I2C Event Notification
146
JTAG 1149.1 Event Notification (Revision A/B Only)
147
Configuration Block Event Notification
147
Trace and Filter Event Notification
147
Packet Generation and Capture Mode Event Notification
147
Port-Write Formats, Programming Model, and Generation
148
Table 54: Port-Write Programming Model Registers and Fields
148
Figure 26: Type 1 Port-Write Packet Data Payload Format
149
Table 55: Standard (Type 1) Port-Write Format
149
Table 56: IDT (Type 2) Port-Write Format
151
Interrupt Notification
152
Error Log Event Notification Programming Model
152
Table 57: Error Log Event Notification Examples
153
Event Isolation
154
Table 58: Standard Event Isolation Behaviors
154
Table 59: Additional Packet Discard Isolation Trigger Functions
155
Fatal Link Response Timeout Isolation
156
Packet Received with a CRC Error While CRC Error Suppression Enabled Isolation
157
Received Retry Count Trigger Congestion Isolation
157
Transmit Packet Dropped Via CRC Retransmit Limit Isolation
157
TTL Event Isolation
157
Software Controlled Isolation Functions
158
Event Clearing and Recovery
158
Logical Layer Event Clearing and Handling
158
Table 60: Logical/Transport Layer Event Enable and Information Capture Summary
158
Physical Layer Events Clearing and Handling
159
Table 61: Physical Layer Events and Information Capture Summary
159
Lane Event Clearing and Handling
167
I2C Event Clearing and Handling
167
Table 62: Lane Event Clearing and Handling
167
Table 63: I2C Event Clearing and Handling
167
JTAG 1149.1 Events (Revision A/B Only)
168
Configuration Block Events
168
Table 64: JTAG Event Clearing and Handling (Revision A/B Only)
168
Table 65: Configuration Block Event Clearing and Handling
168
Trace, Filter, and PGC Events
169
Table 66: Trace, Filter, and PGC Mode Event Clearing
169
7 I2C Interface
170
Overview
170
Master/Slave Configuration
170
Temporary Master Mode
170
Obtaining Configuration in Master Mode
171
Commanded Master Mode
171
Master Clock Frequency
171
EEPROM Format
171
Table 67: EEPROM Register Address Map
172
CRC Calculation
173
Register Map Example
175
EEPROM Format Example
175
Table 68: Register Map Example
175
Table 69: EEPROM Format Example
175
I2C Master Mode Validation Debug
176
Slave Mode
177
Signaling in Slave Mode
177
Table 70: I2C Address Pins
177
Figure 27: Bit Transfer on the I2C Bus
178
Figure 28: START and STOP Signaling
178
Figure 29: Data Transfer
178
Figure 30: Acknowledgment
178
Figure 31: Master Addressing a Slave with a 7-Bit Address (Transfer Direction Is Not Changed)
179
Figure 32: Master Reads a Slave Immediately after the First Byte
179
Figure 33: Combined Format
179
Figure 34: Master Addresses a Slave-Receiver with 10-Bit Address
179
Figure 35: Master Addresses a Slave Transmitter with 10-Bit Address
179
Figure 36: Combined Format - Master Addresses a Slave with 10-Bit Address
179
Connecting to Standard-, Fast-, and Hs-Mode Devices as a Slave
180
CPS-1848 Memory Access through I2C as a Slave
180
Figure 37: Combined Format - Master Transmits Data to Two Slaves, both with 10-Bit Address
180
Figure 38: Write Protocol with 10-Bit Slave Address (ADS Is 1)
181
Figure 39: Read Protocol with 10-Bit Slave Address (ADS Is 1)
181
Figure 40: Write Protocol with 7-Bit Slave Address (ADS Is 0)
181
Figure 41: Read Protocol with 7-Bit Slave Address (ADS Is 0)
182
8 JTAG and Boundary Scan
183
Overview
183
JTAG and AC Extest Compliance
183
Test Instructions
184
Device ID Register
184
Table 71: Test Instructions
184
Initialization and Reset
185
Configuration Register Access (Revision A/B)
185
Table 72: Configuration Registers
185
Configuration Register Access - Reads
186
Configuration Register Access - Writes
186
Figure 42: JTAG Write Access Timing Diagram
186
Figure 43: JTAG Read Access Timing Diagram
186
Configuration Register Access (Revision C)
187
Table 73: JTAG Configuration Register Access Command and Status Instruction
187
Inter-Command Delay
188
Figure 44: Inter-Command Delay
189
Table 74: Minimum Inter-Command Delay
189
Configuration Register Access - Reads
190
Configuration Register Access - Writes
190
Figure 45: JTAG Register Access - Write Timing Diagram
190
Figure 46: JTAG Register Access - Read Timing Diagram
190
JTAG Clock Constraints
191
Boundary Scan
191
Figure 47: JTAG Clock Constraints
191
9 Reset and Initialization
192
Hardware Reset
192
Power-Up Reset
192
Resets after Power-Up
192
Initialization
193
I2C Initialization
193
Link Initialization
193
Register Initialization
194
Computing Timeout Values
195
10 Registers
197
Overview
197
Rapidio Compliance
197
Interpretation of Reserved Register Bits
198
Backward Compatibility
198
Register Type Field Definitions
198
Address Map
198
Table 75: Address Map
198
Rapidio Capability Registers (Cars)
212
Device Identity CAR
212
Device Information CAR
213
Assembly Identity CAR
214
Assembly Information CAR
214
Processing Element Features CAR
215
Switch Port Information CAR
217
Source Operations CAR
218
Switch Multicast Support CAR
219
Switch Route Table Entries Table Limit CAR
220
Switch Multicast Information CAR
221
Rapidio Control and Status Registers (Csrs)
222
Host Base Deviceid Lock CSR
222
Component Tag CSR
222
Standard Route Table Entries Configuration Destid Select CSR
223
Standard Route Table Entry Configuration Port Select CSR
224
Standard Route Table Entry Default Port CSR
225
Multicast Mask Port CSR
226
Multicast Association Selection CSR
227
Multicast Association Operations CSR
228
LP-Serial Extended Features Registers with Software Assisted Error Recovery
229
Port Maintenance Block Header Register
229
Port Link Timeout Control CSR
230
Port General Control CSR
230
Port {0
231
Port {0
232
Port {0
233
Port {0
234
Port {0
235
Port {0
238
Port {0
242
Virtual Channel Extended Features Block Registers
244
VC Register Block Header Register
244
Error Management Extensions Block Registers
245
Error Management Extensions Block Header Register
245
Logical/Transport Layer Error Detect CSR
246
Logical/Transport Layer Error Enable CSR
247
Logical/Transport Layer Deviceid Capture CSR
248
Logical/Transport Layer Control Capture CSR
249
Port-Write Target Deviceid CSR
251
Packet Time to Live CSR
252
Port Error Management Register Base Addresses
253
Port {0
254
Port {0
256
Port {0
258
Port {0
259
Port {0
260
Port {0
261
Port {0
262
Port {0
264
Lane Status Registers
265
Lane {0..47} Status Base Addresses
265
Lane Status Block Header Register
267
Lane {0
268
Lane {0
270
Lane {0
272
Lane {0
273
Lane {0
275
IDT Specific Miscellaneous Registers
276
Route Port Select Register
276
Multicast Route Select Register
277
Port N Watermarks Base Addresses
278
Port {0
279
Broadcast Watermarks Register
280
IDT Specific Event Notification Control Registers
281
Aux Port Error Capture Enable Register
281
Aux Port Error Detect Register
282
Configuration Block Error Capture Enable Register
283
Configuration Block Error Detect Register
284
Impl. Specific Logical/Transport Layer Address Capture Register
286
Logical/Transport Layer Error Report Enable Register
287
Port {0
288
Port {0
289
Port {0
291
Broadcast Port Error Report Enable Register
294
Broadcast Port Implementation Specific Error Report Enable Register
296
Lane N Error Report Enable Base Addresses
298
Lane {0
300
Broadcast Lane Error Report Enable Register
301
Packet Generation and Capture Registers
302
Packet Generation and Capture Base Addresses
302
Port {0
303
Port {0
304
IDT Specific Routing Table Registers
305
Base Addresses for IDT Specific Routing Table Registers
305
Broadcast Device Route Table Register {0
306
Broadcast Domain Route Table Register {0
307
Port {0
308
Port {0
309
Trace Comparison Values and Masks Registers
310
Base Addresses for Trace Comparison Values and Masks Registers
310
Port {0
311
Port {0
312
Port {0
313
Port {0
314
Port {0
315
Port {0
316
Port {0
317
Port {0
318
Port {0
319
Port {0
320
Port {0
321
Port {0
322
Port {0
323
Port {0
324
Port {0
325
Port {0
326
Port {0
327
Port {0
328
Port {0
329
Port {0
330
Broadcast Trace 0 Value 0 Register
331
Broadcast Trace 0 Value 1 Register
331
Broadcast Trace 0 Value 2 Register
332
Broadcast Trace 0 Value 3 Register
332
Broadcast Trace 0 Value 4 Register
333
Broadcast Trace 0 Mask 0 Register
333
Broadcast Trace 0 Mask 1 Register
334
Broadcast Trace 0 Mask 2 Register
334
Broadcast Trace 0 Mask 3 Register
335
Broadcast Trace 0 Mask 4 Register
335
Broadcast Trace 1 Value 0 Register
336
Broadcast Trace 1 Value 1 Register
336
Broadcast Trace 1 Value 2 Register
337
Broadcast Trace 1 Value 3 Register
337
Broadcast Trace 1 Value 4 Register
338
Broadcast Trace 1 Mask 0 Register
338
Broadcast Trace 1 Mask 1 Register
339
Broadcast Trace 1 Mask 2 Register
339
Broadcast Trace 1 Mask 3 Register
340
Broadcast Trace 1 Mask 4 Register
340
Broadcast Trace 2 Value 0 Register
341
Broadcast Trace 2 Value 1 Register
341
Broadcast Trace 2 Value 2 Register
342
Broadcast Trace 2 Value 3 Register
342
Broadcast Trace 2 Value 4 Register
343
Broadcast Trace 2 Mask 0 Register
343
Broadcast Trace 2 Mask 1 Register
344
Broadcast Trace 2 Mask 2 Register
344
Broadcast Trace 2 Mask 3 Register
345
Broadcast Trace 2 Mask 4 Register
345
Broadcast Trace 3 Value 0 Register
346
Broadcast Trace 3 Value 1 Register
346
Broadcast Trace 3 Value 2 Register
347
Broadcast Trace 3 Value 3 Register
347
Broadcast Trace 3 Value 4 Register
348
Broadcast Trace 3 Mask 0 Register
348
Broadcast Trace 3 Mask 1 Register
349
Broadcast Trace 3 Mask 2 Register
349
Broadcast Trace 3 Mask 3 Register
350
Broadcast Trace 3 Mask 4 Register
350
Global Device Configuration Registers
351
Device Control 1 Register
351
Configuration Block Error Report Register
353
Aux Port Error Report Enable Register
354
Rapidio Domain Register
355
Port-Write Control Register
356
Rapidio Assembly Identification CAR Override
357
Rapidio Assembly Information CAR Override
357
Device Soft Reset Register
358
I2C Master Control Register
358
I2C Master Status and Control Register
360
JTAG Control Register (Revision A/B)
361
External MCES Trigger Counter Register
362
Maintenance Dropped Packet Counter Register
362
Switch Parameters 1 Register
363
Switch Parameters 2 Register
365
Quadrant Configuration Register
366
Device Reset and Control Register
368
Implementation Specific Multicast Mask Registers
369
Implementation Specific Multicast Mask Base Addresses
369
Broadcast Multicast Mask Register {0
370
Port {0
371
Port Function Registers
372
Port {0
372
Port {0
373
Port {0
376
Port {0
379
Port {0
382
Port {0
383
Port {0
384
Port {0
385
Port {0
386
Port {0
387
Port {0
388
Port {0
389
Port {0
390
Port {0
391
Port {0
392
Port {0
393
Port {0
394
Port {0
395
Port {0
396
Port {0
397
Broadcast Port Operations Register
398
Broadcast Port Implementation Specific Error Detect Register
401
Broadcast Port Implementation Specific Error Rate Enable Register
404
Implementation Specific Error Logging Registers
407
Error Log Register
407
Error Log Data Register
408
Special Error Registers
408
Special Error Registers Base Addresses
408
Error Log Match Register {0
409
Error Log Match Status Register
410
Error Log Events Register
411
Error Log Control 2 Register
412
PLL Registers
413
PLL Register Base Addresses
413
Pll {0
414
Pll {0
415
Broadcast PLL Control Register
416
Lane Control Registers
417
Lane Control Base Addresses
417
Lane {0
419
Lane {0
423
Lane {0
424
Lane {0
425
Lane {0
426
Lane {0
428
Lane {0
429
Lane {0
430
Lane {0
432
Broadcast Lane Control Register
434
Broadcast Lane PRBS Generator Seed Register
438
Broadcast Lane Error Detect Register
439
Broadcast Lane Error Rate Enable Register
440
Broadcast Lane Attributes Capture Register
441
Broadcast Lane DFE 1 Register
442
Broadcast Lane DFE 2 Register
444
Error Management Broadcast Registers
445
Broadcast Port Error Detect Register
445
Broadcast Port Error Rate Enable Register
447
11 References
449
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