1. Manuals
  2. Brands
  3. IDT Manuals
  4. Switch
  5. 89HPES24N3A
  6. User manual

IDT 89HPES24N3A User Manual

Pci express switch
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
IDT
89HPES24N3A
™
PCI Express® Switch

User Manual

April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

Advertisement

Table of Contents
loading

Related Manuals for IDT 89HPES24N3A

Summary of Contents for IDT 89HPES24N3A

  • Page 1: User Manual

    ® 89HPES24N3A ™ PCI Express® Switch User Manual April 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Content Summary Chapter 1, “PES24N3A Device Overview,” provides a complete introduction to the performance capa- bilities of the 89HPES24N3A. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

  • Page 4: Numeric Representations

    Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

  • Page 5: Register Terminology

    Notes The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2. bit 31 bit 0 Address of Bytes within Words: Big Endian...

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Peer-to-Peer Transactions......................3-8 Bus Locking ............................ 3-8 Port Interrupts ..........................3-10 Legacy Interrupt Emulation......................3-10 Standard PCIe Error Detection and Handling................3-11 Physical Layer Errors ......................3-11 Data Link Layer Errors......................3-11 Transaction Layer Errors ...................... 3-12 Routing Errors ........................
  • Page 9 IDT Table of Contents Hot-Plug and Hot-Swap Notes Introduction ............................. 8-1 Hot-Plug I/O Expander ......................8-4 Hot-Plug Interrupts and Wake-up ................... 8-4 Legacy System Hot-Plug Support ..................8-4 Hot-Swap ............................8-6 Configuration Registers Introduction ............................. 9-1 Upstream Port (Port 0) ......................9-3 Downstream Ports (Ports 2 and 4) ..................
  • Page 10 IDT Table of Contents Notes PES24N3A User Manual April 10, 2008...
  • Page 11 List of Tables ® Table 1.1 PES24N3A Device ID ......................1-5 Notes Table 1.2 PES24N3A Revision ID .......................1-5 Table 1.3 PCI Express Interface Pins....................1-6 Table 1.4 SMBus Interface Pins ......................1-6 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins......................... 1-7 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes PES24N3A User Manual April 10, 2008...
  • Page 13 List of Figures ® Figure 1.1 PES24N3A Architectural Block Diagram ................1-3 Notes Figure 1.2 I/O Expansion Application ....................1-3 Figure 1.3 PES24N3A Logic Diagram ....................1-4 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
  • Page 14 IDT List of Figures Notes PES24N3A User Manual viii April 10, 2008...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-41 AERCTL - AER Control (0x118) ......................9-42 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCICMD - PCI Command Register (0x004)....................9-12 PCIECAP - PCI Express Capability (0x040) ...................9-21 PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-21 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-31 PCIEDCTL - PCI Express Device Control (0x048)..................9-22 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-31...
  • Page 17 IDT Register List Notes SWSTS - Switch Status (0x400) ......................9-50 SWTOCNT - Switch Time-Out Count (0x75C) ..................9-64 SWTOCTL - Switch Time-Out Control (0x750) ..................9-62 SWTORCTL - Switch Time-Out Reporting Control (0x758) ..............9-63 SWTOSTS - Switch Time-Out Status (0x754) ..................9-62 SWTOTSCTL - Switch Time-Out Time-Stamp Control (0x760) ..............9-64 SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) .............9-61...
  • Page 18 IDT Register List Notes PES24N3A User Manual April 10, 2008...

  • Page 19: Pes24N3A Device Overview

    Introduction Notes The 89HPES24N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES24N3A is a 24-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and communications/ networking.
  • Page 20 IDT PES24N3A Device Overview Notes Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O –...

  • Page 21: System Diagrams

    IDT PES24N3A Device Overview System Diagrams 3-Port Switch Core Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer...

  • Page 22: Logic Diagram

    IDT PES24N3A Device Overview Logic Diagram PEREFCLKP PE0TP[0] Reference PEREFCLKN PCI Express PE0TN[0] Clocks Switch REFCLKM SerDes Output PE0TP[7] Port 0 PE0RP[0] PE0TN[7] PCI Express PE0RN[0] PE2TP[0] Switch SerDes Input PCI Express PE2TN[0] PE0RP[7] Port 0 Switch PE0RN[7] SerDes Output...

  • Page 23: System Identification

    IDT PES24N3A Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES24N3A device ID is shown in Table 1.1. PCIe Device...

  • Page 24: Pin Description

    IDT PES24N3A Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 25: Table 1.5 General Purpose I/O Pins

    IDT PES24N3A Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] General Purpose I/O.

  • Page 26: Table 1.7 Test Pins

    IDT PES24N3A Device Overview Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside PES24N3A and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES24N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 27: Pin Characteristics

    IDT PES24N3A Device Overview Notes Signal Type Name/Description PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 1.8 Power and Ground Pins Pin Characteristics Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
  • Page 28 IDT PES24N3A Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor System Pins CCLKDS LVTTL Input pull-up CCLKUS pull-up MSMBSMODE pull-down PERSTN RSTHALT pull-down SWMODE[3:0] pull-down EJTAG / JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO JTAG_TMS pull-up...

  • Page 29: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES24N3A has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.

  • Page 30: Figure 2.2 Non-Common Clock On Upstream; Common Clock On Downstream

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES24N3A Port B Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock)

  • Page 31: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES24N3A Port B Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Clock Generator Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES24N3A...

  • Page 32: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside PES24N3A and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express...
  • Page 33 IDT Clocking, Reset, and Initialization Clock Operation Notes The following reset sequence is executed. 1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN). 2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental...

  • Page 34: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes The PES24N3A provides a reset output signal for each downstream port implemented as a GPIO alter- nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated.

  • Page 35: Upstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes 6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES24N3A registers are updated.

  • Page 36: Downstream Port Reset Outputs

    IDT Clocking, Reset, and Initialization Clock Operation Notes When a downstream secondary bus reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted All TLPs received from corresponding downstream port and queued in the PES24N3A are discarded.

  • Page 37: Power Good Controlled Reset Output

    IDT Clocking, Reset, and Initialization Clock Operation Notes While slot power is enabled, the corresponding downstream port reset output is negated. When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is asserted and then slot power is disabled.
  • Page 38 IDT Clocking, Reset, and Initialization Clock Operation Notes PES24N3A User Manual 2 - 10 April 10, 2008...

  • Page 39: Theory Of Operation

    Chapter 3 Theory of Operation ® Introduction Notes An architectural block diagram of the PES24N3A is shown in Figure 1.1 in Chapter 1. The PES24N3A contains three ports labeled port 0, port 2, and port 4. Port 0 is always the upstream port and port 2 and port 4 are always downstream ports.

  • Page 40: Data Paths

    IDT Theory of Operation Notes used to provide a per-port output buffer. This output buffer enables switch core transfers to occur at x8 rates even when the corresponding output port has negotiated to a lower link width. The size is shown in Table 3.2.

  • Page 41: Switch Core

    IDT Theory of Operation Notes Ingress to Egress Latency (ns) x8 to x8 x8 to x4 x8 to x1 x4 to x4 x4 to x1 x1 to x1 Table 3.4 Latency If the ingress link width is less than the egress link width, then an entire TLP must be received before it can be transmitted on the switch egress port.

  • Page 42: Transaction Routing

    IDT Theory of Operation Transaction Routing Notes The PES24N3A supports routing of all transaction types defined in the PCIe base 1.1 specification. This includes routing of specification-defined transactions as well as those that may be used in vendor defined messages and in future revisions of the PCIe specification.

  • Page 43: Scheduling And Port Arbitration

    IDT Theory of Operation Notes The generation of “valid” signals is based on PCIe ordering rules and is summarized Table 3.6. The notation x > y indicates that the TLP of type x is older (i.e., has an older time-stamp) than the TLP of type y.
  • Page 44 IDT Theory of Operation Notes The candidate vector produced by each port’s ESP is presented to the U-Bus and D-Bus arbiters. – For downstream ports: • The upstream portion of the candidate vector is provided to the D-Bus arbiter. • The downstream portion of the candidate vector is provided to the U-Bus arbiter. An assertion in this portion of the candidate vector indicates a peer-to-peer or downstream route-to-self transfer.

  • Page 45: Figure 3.2 U-Bus Arbitration

    IDT Theory of Operation Notes For downstream-to-upstream transfers, the upstream port’s port arbiter selects the transaction that is initiated. The upstream port arbiter implements both a hardwired fixed round robin algorithm as well as a weighted round robin with 32 phases algorithm as defined by the PCIe base 1.1 specification. The arbitra- tion algorithm, as well as weighted round robin arbitration parameters, are software selectable.

  • Page 46: Peer-To-Peer Transactions

    IDT Theory of Operation Notes pler queue transfer is initiated). However, since the upstream input frame buffer has a queue per transac- tion type, it is possible for multiple upstream to downstream transactions to simultaneously request service. In such a situation, the oldest transaction (i.e., the one with the oldest time-stamp) is selected.
  • Page 47 IDT Theory of Operation Notes stream port. Regardless of the success of a lock, the root complex is required to terminate all lock sequences with an Unlock message. The upstream port lock associated with an unsuccessful completion is released when this Unlock message is received.

  • Page 48: Port Interrupts

    IDT Theory of Operation Port Interrupts Notes The upstream port, port 0, does not generate legacy interrupts or MSIs. Downstream ports support generation of legacy interrupts and MSIs. The following are sources of downstream port interrupts and MSIs. – Downstream port’s hot-plug controller –...

  • Page 49: Standard Pcie Error Detection And Handling

    IDT Theory of Operation Notes An Assert_INTx message is sent to the root by the upstream port (i.e., port 0), when the aggregated state of the corresponding interrupt in the upstream port transitions from a negated to an asserted state. A Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre- sponding interrupt in the upstream port transitions from an asserted to a negated state.

  • Page 50: Transaction Layer Errors

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section TLP ending in ENDB with LCRC that does not 3.5.3.1 TLP discarded match inverted calculated LCRC TLP received with incorrect LCRC 3.5.3.1 Correctable error processing TLP received with sequence number not equal 3.5.3.1...

  • Page 51: Table 1.1 Table

    IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section Completer abort 2.3.1 Not applicable. The PES24N3A Completion time-out never generates non-posted transactions as a requester. Unexpected completion 2.3.2 For the non-advisory cases: non- fatal error processing.

  • Page 52: Routing Errors

    IDT Theory of Operation Notes TLP Type Error Check I/O read or write request LENGTH = 1 (doubleword) TC = 0 ATTR = 0 Last DWord BE[3:0] = 0b0000 Configuration read or write request LENGTH = 1 (doubleword) TC = 0...

  • Page 53: Switch Specific Error Detection And Handling

    IDT Theory of Operation Notes Address Routed TLPs – TLPs whose address decoding indicates they are to route back to the port on which they were received. – TLPs received on the upstream port that match the upstream port’s address range but which do not match a downstream port’s address range (i.e., TLPs that do not route through the...

  • Page 54: Switch Time-Outs

    IDT Theory of Operation Switch Time-Outs Notes The switch core discards any TLP that reaches the head of an IFB queue and is more than 64 seconds old. This includes posted, non-posted, completion and inserted TLPs. Although this feature is enabled by default, it may be disabled by setting the Enable Switch Time-outs (ETO) bit in a port’s Switch Time-Out...

  • Page 55: Tlp Processing

    IDT Theory of Operation Notes If a parity error is detected by the DL layer of an egress port, then the TLP is nullified by inverting the computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are discarded.
  • Page 56 IDT Theory of Operation Notes requests that are Message Signaled Interrupts (MSIs), and Message requests (except where specifically permitted). Since MSIs cannot be distinguished from memory write transactions by the switch, the no-snoop attribute of MSIs will be modified. PES24N3A User Manual...

  • Page 57: Link Operation

    Chapter 4 Link Operation ® Introduction Notes The PES24N3A contains three x8 ports. The default link width of each port is x8 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES24N3A supports automatic polarity inversion as required by the PCIe specification. Polarity inversion is a function of the receiver and not the transmitter.

  • Page 58: Figure 4.1 Port Lane Reversal For Maximum Link Width Of X2 (Maxlnkwdth[5:0]=0X2)

    IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES24N3A PES24N3A PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal...

  • Page 59: Figure 4.2 Port Lane Reversal For Maximum Link Width Of X4 (Maxlnkwdth[5:0]=0X4)

    IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES24N3A PES24N3A PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal...

  • Page 60: Link Retraining

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES24N3A PES24N3A PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5]...

  • Page 61: Link Down

    IDT Link Operation Link Down Notes When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR).

  • Page 62: Active State Power Management

    IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.4 PES24N3A ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is independent of power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.

  • Page 63: Link Status

    IDT Link Operation Link Status Notes Associated with each port is a Port Link Up (PxLINKUP) status output and a Port Activity (PxACTIVE) status output. These outputs are provided on I/O Expander 4. See section I/O Expanders on page 6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
  • Page 64 IDT Link Operation Notes PES24N3A User Manual 4 - 8 April 10, 2008...

  • Page 65: General Purpose I/O

    Chapter 5 General Purpose I/O ® Introduction Notes The PES24N3A has 8 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 66: Gpio Pin Configured As An Input

    IDT General Purpose I/O GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.

  • Page 67: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES24N3A contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES24N3A, allowing every register in the device to be read or written by an external SMBus master.

  • Page 68: Master Smbus Interface

    IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses. Thus, multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.

  • Page 69: Table 6.2 Pes24N3A Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.2 PES24N3A Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.

  • Page 70: Figure 6.3 Sequential Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.3 Sequential Double Word Initialization Sequence Format...

  • Page 71: Table 6.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence . The correct result should always be 0xFF (i.e., all ones).

  • Page 72: I/O Expanders

    IDT SMBus Interfaces Notes To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), the write operation may be initiated by writing the value to be written to the...
  • Page 73 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander zero: – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 74 IDT SMBus Interfaces Notes An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initialized to its default value. When this occurs, the internal PES24N3A state of the hot-plug signals is in conflict with the state of I/O expander hot-plug output signals.

  • Page 75: Table 6.5 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes System Design Recommendations 1. I/O expander addresses and default output values may be configured during serial EEPROM initial- ization. If I/O expander addresses are configured via the serial EEPROM, then the PES24N3A will initialize the I/O expanders when normal device operation begins following the completion of the fundamental reset sequence.

  • Page 76: Table 6.6 I/O Expander 2 Signals

    IDT SMBus Interfaces Notes I/O Expander 2 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) Reserved Tie high 1 (I/O-0.1) Reserved Tie high 2 (I/O-0.2) Reserved Tie high 3 (I/O-0.3) Reserved Tie high 4 (I/O-0.4) Reserved Tie high or low 5 (I/O-0.5)

  • Page 77: Slave Smbus Interface

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 10 (I/O-1.2) P2ACTIVEN Port 2 activity output 11 (I/O-1.3) Reserved Tie high or low 12 (I/O-1.4) P4ACTIVEN Port 4 activity output 13 (I/O-1.5) Reserved Tie high or low 14 (I/O-1.6)

  • Page 78: Table 6.9 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Notes SIZE FUNCTION START Figure 6.5 Slave SMBus Command Code Format Name Description End of transaction indicator. Setting both START and END signifies a single transaction sequence. 0 - Current transaction is not the last read or write sequence.

  • Page 79: Table 6.10 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Name Description Position CCODE Command Code. Slave Command Code field described in Table 6.9. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field. The byte count field indi- cates the number of bytes following the byte count field when performing a write or setting up for a read.

  • Page 80: Table 6.12 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Bit Field Name Type Description Read/Write CSR Operation. This field encodes the CSR operation to be performed. 0 - CSR write 1 - CSR read Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus and Clear transaction was not claimed by a device.

  • Page 81: Table 6.13 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes LAERR NAERR OTHERERR Figure 6.7 Serial EEPROM Read or Write CMD Field Format Bit Field Name Type Description Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address.

  • Page 82: Figure 6.8 Csr Register Read Using Smbus Block Write/Read Transactions With Pec

    IDT SMBus Interfaces Notes PES24N3A Slave CCODE BYTCNT=3 CMD=read ADDRL ADDRU SMBus Address START,END PES24N3A Slave CCODE (PES24N3A not ready with data) SMBus Address START,END PES24N3A Slave CCODE PES24N3A Slave BYTCNT=7 CMD (status) ADDRL SMBus Address START,END SMBus Address ADDRU...

  • Page 83: Figure 6.11 Serial Eeprom Write Using Smbus Block Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES24N3A Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES24N3A Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled...

  • Page 84: Figure 6.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES24N3A Slave CCODE CMD=read ADDRL SMBus Address START, Word PES24N3A Slave CCODE ADDRU SMBus Address END, Byte PES24N3A Slave CCODE (PES24N3A not ready with data) SMBus Address START,Word PES24N3A Slave CCODE SMBus Address START,Word PES24N3A Slave...

  • Page 85: Power Management

    Chapter 7 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES24N3A is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 86: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the state.

  • Page 87: Power Budgeting Capability

    IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES24N3A receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES24N3A transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 88 IDT Power Management Notes PES24N3A User Manual 7 - 4 April 10, 2008...

  • Page 89: Notes

    Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES24N3A in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 90: Figure 8.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES24N3A Port 1 Port 2 PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES24N3A Master SMBus...

  • Page 91: Table 8.1 Downstream Port Hot-Plug Signals

    IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES24N3A in an application involving an add-in card hot-plugged into a downstream slot. Associated with each downstream port in the PES24N3A is a hot- plug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capa- bilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).

  • Page 92: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes The default value of hot-plug registers following a hot or fundamental reset may be configured via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result of serial EEPROM initialization.

  • Page 93: Figure 8.4 Pes24N3A Hot-Plug Event Signalling

    IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.

  • Page 94: Hot-Swap

    The hot-swap I/O buffers of the PES24N3A may also be used to construct proprietary hot-swap systems. See the 89PES24N3A Data Sheet on IDT’s web site (www.IDT.com) for a detailed specification of I/O buffer characteristics. PES24N3A User Manual...

  • Page 95: Configuration Registers

    Chapter 9 Configuration Registers ® Introduction Notes Each software-visible register in the PES24N3A is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES24N3A that cannot be accessed by the root. Each software- visible register in the PES24N3A has a system address.

  • Page 96: Figure 9.1 Port Configuration Space Organization

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting...

  • Page 97: Upstream Port (Port 0)

    IDT Configuration Registers Upstream Port (Port 0) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 98 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte P0_INTRPIN...
  • Page 99 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-42 0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 9-42 0x124...
  • Page 100 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword P0_PWRBDV3 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x310 Dword P0_PWRBDV4 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x314...
  • Page 101 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page 9-62 0x74C Dword P0_SWPECNT SWPECNT - Switch Parity Error Count (0x74C) on page 9-62 0x750 Dword...

  • Page 102: Downstream Ports (Ports 2 And 4)

    IDT Configuration Registers Downstream Ports (Ports 2 and 4) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 103 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte Px_INTRPIN...
  • Page 104 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F0 Dword SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Px_SSIDSSVIDCAP Capability (0x0F0) on page 9-36 0x0F4 Dword Px_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on page 9-36...

  • Page 105: Register Definitions

    VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-5. PES24N3A User Manual 9 - 11 April 10, 2008...
  • Page 106 Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. See section Device ID on page 1-5. PCICMD - PCI Command Register (0x004) Field Default Type Description Field...
  • Page 107 IDT Configuration Registers Notes Field Default Type Description Field Name Value FB2B Fast Back-to-Back Enable. Not applicable. INTXD INTx Disable. Controls the ability of the PCI-PCI bridge to generate an INTx interrupt message. When this bit is set, any interrupts generated by this bridge are negated.
  • Page 108 IDT Configuration Registers Notes RID - Revision Identification Register (0x008) Field Default Type Description Field Name Value — Revision ID. This field contains the revision identification number for the device. See section Revision ID on page 1-5. CCODE - Class Code Register (0x009)
  • Page 109 IDT Configuration Registers Notes BAR0 - Base Address Register 0 (0x010) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. BAR1 - Base Address Register 1 (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable.
  • Page 110 IDT Configuration Registers Notes IOBASE - I/O Base Register (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. 0x0 -(io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing.
  • Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value RW1C Detected Parity Error. This bit is set by the bridge when- ever it receives a poisoned TLP on the secondary side regardless of the state of the PERRE bit in the PCI Com-...
  • Page 112 IDT Configuration Registers Notes PMLIMIT - Prefetchable Memory Limit Register (0x026) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. This bit always reflects the value in the PMCAP field in the PMBASE register.
  • Page 113 IDT Configuration Registers Notes IOLIMITU - I/O Limit Upper Register (0x032) Field Default Type Description Field Name Value 15:0 IOLIMITU Prefetchable IO Limit Upper. This field specifies the upper 16-bits of IOLIMIT. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 114 IDT Configuration Registers Notes BCTRL - Bridge Control Register (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the bridges response to poisoned TLPs on the secondary inter- face. 0x0 - (ignore) Ignore poisoned TLPs (i.e., parity errors) on the secondary interface.

  • Page 115: Pci Express Capability Structure

    IDT Configuration Registers PCI Express Capability Structure Notes PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure. 15:8 NXTPTR 0xC0 Next Pointer.
  • Page 116 IDT Configuration Registers Notes Field Default Type Description Field Name Value Attention Button Present. In PCIe base 1.1 when set, this bit indicates that an Attention Button is implemented on the card/module. The value of this field is undefined in PCIe base 1.1 Attention Indicator Present.
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value Max Payload Size. This field sets maximum TLP payload size for the device. 0x0 -(s128) 128 bytes max payload size 0x1 -(s256) 256 bytes max payload size 0x2 -(s512) 512 bytes max payload size...
  • Page 118 IDT Configuration Registers Notes Field Default Type Description Field Name Value Transactions Pending. The bridge does not issue Non- Posted Requests on its own behalf. Therefore, this field is hardwired to zero. 15:6 Reserved Reserved field. PCIELCAP - PCI Express Link Capabilities (0x04C)
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value DLLLA Upstream: Data Link Layer Link Active Reporting. The PES24N3A downstream ports support the capability of reporting the DL_Active state of the data link control and management Downstream: State machine.
  • Page 120 IDT Configuration Registers Notes Field Default Type Description Field Name Value LRET Link Retrain. Writing a one to this field initiates Link retrain- ing by directing the Physical Layer LTSSM to the Recovery state. This field always returns zero when read.
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value TERR Training Error. In PCIe base 1.0a when set, this bit indi- cates that a link training error has occurred. The value of this field is undefined in PCIe base 1.1 LTRAIN Link Training.
  • Page 122 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLP MRL Sensor Present. This bit is set when an MRL Sensor is implemented for the port. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 123 IDT Configuration Registers Notes PCIESCTL - PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. This bit when set enables generation of a Hot-Plug interrupt or wake-up event on an attention button pressed event.
  • Page 124 IDT Configuration Registers Notes Field Default Type Description Field Name Value Power Indicator Control. When read, this register returns the current state f the Power Indicator. Writing to this regis- ter sets the indicator. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
  • Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value Presence Detect State. This bit indicates the presence of a card in the slot corresponding to the port and reflects the state of the Presence Detect status. 0x0 -(empty) Slot empty 0x1 -(present) Card present Electromechanical Interlock Status.
  • Page 126 IDT Configuration Registers Notes PCIELCTL2 - PCI Express Link Control 2 (0x070) Field Default Type Description Field Name Value Target Link Speed. For downstream ports, this field sets an upper limit on the link operational speed by restricting the values advertised by the upstream component in its training sequences.

  • Page 127: Power Management Capability Structure

    IDT Configuration Registers Notes PCIESSTS2 - PCI Express Slot Status 2 (0x07A) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. Power Management Capability Structure PMCAP - PCI Power Management Capabilities (0x0C0) Field Default Type Description Field Name...

  • Page 128: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes PMCSR - PCI Power Management Control and Status (0x0C4) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state and to set a new power state.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value Enable. This bit enables MSI. 0x0 -(disable) disabled 0x1 -(enable) enabled 19:17 Multiple Message Capable. This field contains the number of requested messages. 22:20 Multiple Message Enable. Hardwired to one message.

  • Page 130: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) Field Default Type Description Field Name Value 15:0 MDATA Message Data. This field contains the lower 16-bits of data that are written when a MSI is signalled. 31:16 Reserved Reserved field.

  • Page 131: Advanced Error Reporting (Aer) Enhanced Capability

    IDT Configuration Registers Notes ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configuration space register value pointed to by the ECF- GADDR register.
  • Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value COMPTO Completion Time-out Status. A switch port does not ini- tiate non-posted requests on its own behalf. Therefore, this field is hardwired to zero. CABORT Completer Abort Status. The PES24N3A never responds to a non-posted request with a completer abort.
  • Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value UECOMP Unexpected Completion Mask. When this bit is set, the Sticky corresponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value POISONED Poisoned TLP Status Severity. If the corresponding event Sticky is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 135 IDT Configuration Registers Notes AERCES - AER Correctable Error Status (0x110) Field Default Type Description Field Name Value RCVERR RW1C Receiver Error Status. This bit is set when the physical Sticky layer detects a receiver error. Reserved Reserved field. BADTLP RW1C Bad TLP Status.
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADVISO- Advisory Non-Fatal Error Status.When this bit is set, the RYNF Sticky corresponding bit in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.

  • Page 137: Device Serial Number Enhanced Capability

    IDT Configuration Registers Notes AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 4th doubleword of the Sticky TLP header that resulted in the first reported uncorrectable error.
  • Page 138 IDT Configuration Registers Notes PVCCAP1- Port VC Capability 1 (0x204) Field Default Type Description Field Name Value EVCCNT Extended VC Count. The value 0x0 indicates only imple- mentation of the default VC. Reserved Reserved field. LPEVCCNT Low Priority Extended VC Count. The value of 0x0 indi- cates only implementation of the default VC.
  • Page 139 IDT Configuration Registers Notes PVCCTL - Port VC Control (0x20C) Field Default Type Description Field Name Value LVCAT Load VC Arbitration Table. This bit, when set, updates the VC arbitration logic from the VC Arbitration Table for the VC resource. Since the device does not implement a VC arbitra- tion table, this field has no functional effect.
  • Page 140 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 PATBLOFF Upstream: Port Arbitration Table Offset. This field contains the offset of the port arbitration table from the base address of the Vir- tual Channel Capability structure in double quad words (16 Downstream: bytes).
  • Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value PATS Port Arbitration Table Status. This bit indicates the coher- ency status of the port arbitration table associated with the VC resource and is valid only when the port arbitration table is used by the selected arbitration algorithm.
  • Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value PHASE9 Phase 9. This field contains the port ID for the correspond- ing port arbitration period. 11:8 PHASE10 Phase 10. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 143: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:16 PHASE28 Phase 28. This field contains the port ID for the correspond- ing port arbitration period. 23:20 PHASE29 Phase 29. This field contains the port ID for the correspond- ing port arbitration period.

  • Page 144: Switch Control And Status Registers

    IDT Configuration Registers Notes PWRBPBC - Power Budgeting Power Budget Capability (0x28C) Field Default Type Description Field Name Value System Allocated. When this bit is set, it indicates that the power budget for the device is included within the system power budget and that reported power data for this device should be ignored.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value 11:10 PEMODE HWINIT PCI Express Base Specification Mode. This field selects the PCIe base specification operating mode for the PES24N3A. 0x0 - reserved 0x1 - (pebase1p1) PCIe 1.1 base specification compliant mode.
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value PWRBDVUL Power Budgeting Data Value Unlock. When this bit is set, Sticky the Power Budgeting Data Value [7:0] (PWRBDV[7:0]) reg- isters in all ports may be read and written. When this bit is cleared, then the PWRBDV registers in all ports are read- only.
  • Page 147 IDT Configuration Registers Notes Field Default Type Description Field Name Value IPXPIN Invert Polarity of PxPIN. When this bit is set, the polarity of Sticky the PxPIN output is inverted in all ports. IPXPEP Invert Polarity of PxPEP. When this bit is set, the polarity Sticky of the PxPEP output is inverted in all ports.
  • Page 148 IDT Configuration Registers Notes GPIOFUNC - General Purpose I/O Control Function (0x418) Field Default Type Description Field Name Value 15:0 GPIOFUNC GPIO Function. Each bit in this field controls the corre- Sticky sponding GPIO pin. When set to a one, the corresponding GPIO pin operates as the alternate function as defined in Table 5.1 of Chapter 5.
  • Page 149 IDT Configuration Registers Notes Field Default Type Description Field Name Value EEPROM- Serial EEPROM Initialization Done. When the switch is DONE configured to operate in a mode in which serial EEPROM initialization occurs during a fundamental reset, this bit is set when serial EEPROM initialization completes or when an error is detected.
  • Page 150 IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:18 SSMBMODE Slave SMBus Mode. The salve SMBus contains internal Sticky glitch counters on the SSMBCLK and SSMBDAT signals that wait approximately 1uS before sampling or driving these signals. This field allows the glitch counter time to be reduced or entirely removed.
  • Page 151 IDT Configuration Registers Notes Field Default Type Description Field Name Value DONE RW1C EEPROM Operation Completed. This bit is set when a serial EEPROM operation has completed. 0x0 -(notdone) interface is idle or operation in progress 0x1 -(done) operation completed EEPROM Operation Select.
  • Page 152 IDT Configuration Registers Notes Field Default Type Description Field Name Value DONE RW1C I/O Expander Operation Done. This bit is set when any of the following conditions occurs: - RELOADIOEX bit in this register is written, the corre- sponding I/O expander is selected by the SELECT field in this register, and the corresponding IO expander SMBus transaction completes.
  • Page 153 IDT Configuration Registers Notes Field Default Type Description Field Name Value P2GPEE Port 2 General Purpose Event Enable. When this bit is Sticky set, the hot-plug INTx, MSI and PME event notification mechanisms defined by the PCIe base 1.1 specification are disabled for port 2 and are instead signalled through Gen- eral Purpose Event (GPEN) signal assertions.
  • Page 154 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 U2STC 0x01 Upstream to Self Transfer Count. This field contains the Sticky upstream to self transfer count. The U2SCTC field in the UARBCTC register is set to this value after each arbitration period.

  • Page 155: Internal Switch Error Control And Status Registers

    IDT Configuration Registers Notes SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) Field Default Type Description Field Name Value 31:0 PRESETVAL Time-Stamp Preset Value. A write to this register will cause bits 34 through three of the time-stamp counter associated with all ports to take on the value written and bits two through zero to be set to zero.
  • Page 156 IDT Configuration Registers Notes SWPERCTL - Switch Parity Error Reporting Control (0x748) Field Default Type Description Field Name Value EEPE End-to-End Parity Error Reporting. This field controls the manner in which end-to-end parity errors detected at this port are reported. An end-to-end parity error is reported as...
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value CPTLPTO RW1C Completion TLP Time-Out. This bit is set when a TLP is discarded from the port’s IFB completion queue because of a time-out. ITLPTO RW1C Inserted TLP Time-Out. This bit is set when a TLP is dis- carded from the port’s IFB insertion queue because of a...
  • Page 158 IDT Configuration Registers Notes Field Default Type Description Field Name Value ITLPTO Inserted TLP Time-Out Reporting. This field controls the Sticky manner in which inserted TLP time-outs are reported. A time-out is reported as specified in this field whenever the corresponding bit in the Switch Time-Out Status (SWTOSTS) register transitions from a zero to a one.
  • Page 159 IDT Configuration Registers Notes Field Default Type Description Field Name Value 30:22 TCOUNT 0x1DD Terminal Count. This field contains the value associated Sticky with bits 24 to 32 which signify a terminal count. When the time-stamp counter is greater than or equal to this value, then time-stamp epoch values contained in bits 33 and 34 of the time-stamp are incremented.The default value of 0x1DD...
  • Page 160 IDT Configuration Registers Notes PES24N3A User Manual 9 - 66 April 10, 2008...

  • Page 161: Jtag Boundary Scan

    Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES24N3A: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 162: Table 10.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 163: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PE0RN[7:0] face PE0RP[7:0] PE0TN[7:0] PE0TP[7:0] PE2RN[7:0] PE2RP[7:0] PE2TN[7:0] PE2TP[7:0] PE4RN[7:0] PE4RP[7:0] PE4TN[7:0] PE4TP[7:0] PEREFCLKN[2:1] — PEREFCLKP[2:1] — REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1]...

  • Page 164: Test Data Register (Dr)

    IDT JTAG Boundary Scan Test Data Register (DR) Notes The Test Data register contains the following: Bypass register Boundary Scan registers Device ID register These registers are connected in parallel between a common serial input and a common serial data output and are described in the following sections.

  • Page 165: Figure 10.4 Diagram Of Output Cell

    IDT JTAG Boundary Scan Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 10.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 10.5.

  • Page 166: Instruction Register (Ir)

    IDT JTAG Boundary Scan Instruction Register (IR) Notes The Instruction register allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both.

  • Page 167: Sample/Preload

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x801C This field identifies the silicon as PES24N3A. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES24N3A.

  • Page 168: Validate

    IDT JTAG Boundary Scan VALIDATE Notes The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std. 1149.1 specification. RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.

Table of Contents