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IDT 89HPES12N3 User Manual

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IDT
89HPES12N3
™
PCI Express® Switch
User Manual
June 2006
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2006 Integrated Device Technology, Inc.

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  • Page 1 89HPES12N3 ™ PCI Express® Switch User Manual June 2006 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2006 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Content Summary Chapter 1, “PES12N3 Device Overview,” provides a complete introduction to the performance capa- bilities of the 89HPES12N3. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

  • Page 4: Numeric Representations

    IDT About This Manual Numeric Representations Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
  • Page 5 IDT About This Manual Register Terminology Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition...

  • Page 6: Revision History

    IDT About This Manual Use of Hypertext Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. How- ever, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents About This Manual Notes Introduction ............................. 1 Finding Additional Information....................1 Content Summary........................... 1 Signal Nomenclature ........................1 Numeric Representations ....................... 2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Revision History..........................4 1 PES12N3 Device Overview Introduction ..........................1-1 Features............................1-3...
  • Page 8 IDT Table of Contents Notes 4 Switch Operation Introduction ..........................4-1 Routing ............................4-3 Data Integrity ..........................4-4 Switch Time-Outs ........................4-5 Locking ............................4-5 Interrupts............................4-7 Switch Core Errors........................4-8 5 Power Management Introduction ..........................5-1 PME Messages ........................5-2 Link States ...........................5-2 Active State Power Management ....................5-3 6 Hot-Plug and Hot-Swap Introduction ..........................6-1...
  • Page 9 IDT Table of Contents Notes Configuration Requests......................9-6 Port Configuration Space Organization ..................9-6 Upstream Port A Configuration Space Registers ................9-8 Register Specialization.....................9-10 Downstream Port B Configuration Space Registers..............9-11 Register Specialization.....................9-13 Downstream Port C Configuration Space Registers..............9-14 Register Specialization.....................9-16 Generic PCI to PCI Bridge Register Definition ................9-17 Type 1 Configuration Header Registers ................9-17...
  • Page 10 IDT Table of Contents Notes PES12N3 User Manual June 7, 2006...
  • Page 11 List of Tables Table 1.1 PES12N3 Offset Device IDs .....................1-4 Notes Table 1.2 PES12N3 Revision IDs.....................1-5 Table 1.3 PCI Express Interface Pins....................1-7 Table 1.4 SMBus Interface Pins .......................1-8 Table 1.5 General Purpose I/O Pins....................1-8 Table 1.6 System Pins........................1-9 Table 1.7 Test Pins .........................1-10 Table 1.8 Power and Ground Pins....................1-10...
  • Page 12 IDT List of Tables Notes Table 11.4 System Controller Device Identification Register............11-8 PES12N3 User Manual June 7, 2006...
  • Page 13 List of Figures Figure 1.1 PES12N3 Functional Block Diagram ................1-2 Notes Figure 1.2 PES12N3 Architectural Block Diagram ................1-3 Figure 1.3 PES12N3 Logic Diagram ....................1-6 Figure 2.1 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ....2-6 Figure 3.1 Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[1:0]=0x2) .......
  • Page 14 IDT List of Figures Notes PES12N3 User Manual viii June 7, 2006...
  • Page 15 Register List BAR0 - Base Address Register 0 (0x010) ....................9-20 Notes BAR1 - Base Address Register 1 (0x014) ....................9-20 BCTRL - Bridge Control (0x03E) ......................9-26 BIST - Built-in Self Test (0x00F).......................9-20 CAPPTR - Capabilities Pointer (0x034) ....................9-25 CCODE - Class Code (0x009) .........................9-19 CLS - Cache Line Size (0x00C) .......................9-20 DID - Device Identification (0x002)......................9-17 ECFGADDR - Extended Configuration Space Access Address (0x0F8) ..........9-49...
  • Page 16 IDT Register List Notes PMCSR - PCI Power Management Control and Status (0x074) ..............9-36 PMLIMIT - Prefetchable Memory Limit (0x026)..................9-24 PMLIMITU - Prefetchable Memory Limit Upper (0x02C)................9-24 PMPC - PCI Power Management Proprietary Control (0x078) ..............9-37 PVCCAP1- Port VC Capability 1 (0x104)....................9-50 RID - Revision Identification (0x008)......................9-19...

  • Page 17: Pes12N3 Device Overview

    It provides 6 GBps (48 Gbps) of aggregate switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions. The PES12N3 is fully compliant with PCI Express Base specification 1.0a.

  • Page 18: Introduction

    IDT PES12N3 Device Overview Introduction Notes Port A (Upstream Port) Type 1 Configuration Header PCI-PCI Transparent Bridge Virtual PCI Bus Type 1 Type 1 Configuration Header Configuration Header PCI-PCI PCI-PCI Transparent Bridge Transparent Bridge (Device 1) (Device 0) Port B...

  • Page 19: Features

    IDT PES12N3 Device Overview Features Notes 3-Port Switch Core Egress Egress Egress GPIO Port Arbiter Port Arbiter Port Arbiter Scheduler Scheduler Scheduler Controller Input Frame Buffer Input Frame Buffer Input Frame Buffer Route Route Route Table Table Table Hot-Plug Controller...

  • Page 20: System Identification

    IDT PES12N3 Device Overview System Identification Notes – Supports ECRC passed through – Supports PCI Express Native Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap Power Management – Supports PCI Express Power Management Interface specification, Revision 1.1 (PCI-PM) –...

  • Page 21: Revision Id

    IDT PES12N3 Device Overview System Identification Revision ID Notes All revision IDs in the PES12N3 are set to the same value. The value of the revision ID is determined in one place and is easily modified during a metal mask change. The revision ID shall be incremented with each all layer or metal mask change.

  • Page 22: Logic Diagram

    IDT PES12N3 Device Overview Logic Diagram Logic Diagram Notes PEREFCLKP Reference PEREFCLKN Clock REFCLKM PEALREV PEARP[0] PEATP[0] PEARN[0] PEATN[0] PCI Express PCI Express Switch PEARP[1] PEATP[1] Switch SerDes Input PEARN[1] PEATN[1] SerDes Output Port A Port A PEARP[3] PEATP[3] PEARN[3]...

  • Page 23: Pin Description

    IDT PES12N3 Device Overview Pin Description Pin Description Notes The following tables lists the functions of the pins provided on the PES12N3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.

  • Page 24: Table 1.4 Smbus Interface Pins

    IDT PES12N3 Device Overview Pin Description Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus.

  • Page 25: Table 1.6 System Pins

    IDT PES12N3 Device Overview Pin Description Notes Signal Type Name/Description CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.

  • Page 26: Table 1.7 Test Pins

    IDT PES12N3 Device Overview Pin Description Notes Signal Type Name/Description JTAG_TCK JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle.

  • Page 27: Pin Characteristics

    IDT PES12N3 Device Overview Pin Characteristics Pin Characteristics Notes Some input pads of the PES12N3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation.

  • Page 28: Table 1.9 Pin Characteristics

    IDT PES12N3 Device Overview Pin Characteristics Notes Internal Function Pin Name Type Buffer Notes Type Resistor System Pins CCLKDS LVTTL Input pull-up CCLKUS LVTTL Input pull-up MSMBSMODE LVTTL Input pull-down PERSTN LVTTL Input RSTHALT LVTTL Input pull-down TSTRSVD LVTTL Input...

  • Page 29: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization Introduction Notes The PES12N3 has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.

  • Page 30: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Initialization Notes May Be Signal Description Overridden CCLKDS Common Clock Downstream. The assertion of this pin indi- cates that all downstream ports are using the same clock source as that provided to downstream devices.This pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.

  • Page 31: Reset

    IDT Clocking, Reset, and Initialization Reset Notes May Be Signal Description Overridden RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12N3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 32 IDT Clocking, Reset, and Initialization Reset Notes Global Global Local Fund. Reset to Reset to Reset Downstr Entire Reset Device Ports Switch Core N (flush buffer only) Port A All Registers Port A All Registers Except Those of Type Sticky or RWL...

  • Page 33: Fundamental Reset

    IDT Clocking, Reset, and Initialization Reset Fundamental Reset Notes A fundamental reset of the entire device may be initiated by one of three conditions: – A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input pin.

  • Page 34: Hot Reset

    IDT Clocking, Reset, and Initialization Reset Notes PA_SMBUSSTS register is set. 12. Wait for link training on all ports to complete or fail. 13. If the Reset Halt (RSTHALT) bit is set in the PA_SWCTL register, all of the logic is held in a reset state except the master and slave SMBuses, the control/status registers, and the stacks which continue to be held in a quasi-reset state and respond to configuration transactions with a retry.
  • Page 35 IDT Clocking, Reset, and Initialization Reset Notes Hot reset is only propagated downstream. TS1 ordered-sets indicating a hot reset received on a down- stream port do not result in a hot reset of the downstream port or any function inside the switch.
  • Page 36 IDT Clocking, Reset, and Initialization Reset Notes PES12N3 User Manual 2 - 8 June 7, 2006...

  • Page 37: Link Operation

    Chapter 3 Link Operation Introduction Notes The PES12N3 contains three ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES12N3 supports automatic polarity inversion as required by the PCIe® specification. Polarity inversion is a function of the receiver and not the transmitter.

  • Page 38: Figure 3.1 Lane Reversal For Maximum Link Width Of X4 (Maxlnkwdth[1:0]=0X2)

    IDT Link Operation Lane Reversal Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PES12N3 PES12N3 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 (a) x4 Port with PExLREV negated (b) x4 Port with PExLREV asserted...

  • Page 39: Link Retraining

    IDT Link Operation Link Retraining Notes When link training occurs, the corresponding lane reversal bits in the PA_SWCTL register are examined. If a bit is set, then the lanes associated with that link are revered. This mechanism may be used to configure lane reversal via the serial EEPROM, slave SMBus, or root.
  • Page 40 IDT Link Operation Slot Power Limit Support Notes PES12N3 User Manual 3 - 4 June 7, 2006...

  • Page 41: Notes

    Chapter 4 Switch Operation Introduction Notes The PES12N3 utilizes an input buffered cut-through switch to forward PCIe® TLPs between switch ports. At a high level the switch may be viewed as consisting of three PCIe stacks and a switch core. The PCIe stacks are each responsible for performing the per port Phy, data link and transaction layer functions defined in the PCIe specification.

  • Page 42: Table 4.1 Pes12N3 Buffer Sizes

    IDT Switch Operation Introduction Notes Buffer Size and Limitations Posted FIFO 4 KB and up to 32 TLPs Non-posted FIFO 1 KB and up to 32 TLPs Completions FIFO 4 KB and up to 32 TLPs Egress Stack Replay Buffer 5120 bytes and up to 15 TLPs Table 4.1 PES12N3 Buffer Sizes...

  • Page 43: Routing

    IDT Switch Operation Routing Notes Default Flow Control Advertised Notes Category Credits Posted Header 30 credits Each credit represents 20 bytes (i.e., 5 doublewords) for a max- imum of 600 bytes Posted Data 204 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max-...

  • Page 44: Data Integrity

    IDT Switch Operation Data Integrity Notes Routing Method TLP Type Using Routing Method Route by Address MRd, MrdLk, MWr, IORd, IOWr, Msg, MsgD ID Based Routing CfgRd0, CfgWr0, CfgRd1, CfgWr1, Cpl, CpdD, CplLk, CplDLk, Msg, MsgD Imlicit Routing - Route to Root...

  • Page 45: Switch Time-Outs

    IDT Switch Operation Switch Time-Outs Notes root; increments the End-to-End Parity Error Count (EEPERRC) field in the SWSIPECNT register associ- ated with the port on which the error was detected; and sets the Detected Parity Error (DPE) bit in the PCISTS register if the error was detected by a downstream port or sets DPE bit in the PCI Secondary Status (SECSTS) register if the error was detected by an upstream port.
  • Page 46 IDT Switch Operation Locking Notes When the PES12N3 receives a MRdLk transaction on its root port destined for a down-stream port, it forwards the MRdLK transaction to the downstream port and locks the downstream port so that all subse- quent TLPs destined to the downstream port from ports other than the root are blocked until the lock is released.

  • Page 47: Interrupts

    IDT Switch Operation Interrupts Notes The PME Lock Error (PMELOCK) bit in the PA_SWSTS register is set and the transaction is dropped when a PME_Turn_Off message is received by a locked downstream PCI-PC I bridge (i.e., that associated with port B or C). If error reporting is enabled, an ERR_NON_FATAL message is sent to the root when the switch is unlocked.

  • Page 48: Switch Core Errors

    IDT Switch Operation Switch Core Errors Notes Port A Interrupt Interrupt Sources INTA Port B INTA Port C INTD INTB Port B INTB Port C INTA INTC Port B INTC Port C INTB INTD Port B INTD Port C INTC Table 4.5 PES12N3 Upstream Port Bridge Interrupt Mapping...
  • Page 49 IDT Switch Operation Switch Core Errors Notes – Reception of TLPs that have no route (i.e., do not match an address or ID route through the switch). TLPs that have no route should be treated as unsupported requests. – Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared in PA_PCICMD register).
  • Page 50 IDT Switch Operation Switch Core Errors Notes PES12N3 User Manual 4 - 10 June 7, 2006...

  • Page 51: Power Management

    Chapter 5 Power Management Introduction Notes A power management capability structure is located in the configuration space of each PCI-PCI bridge in the PES12N3. The structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 52: Pme Messages

    IDT Power Management Link States Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 53: Active State Power Management

    IDT Power Management Active State Power Management Notes L2/L3 Ready Figure 5.2 PES12N3 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express® Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.
  • Page 54 IDT Power Management Active State Power Management Notes PES12N3 User Manual 5 - 4 June 7, 2006...

  • Page 55: Hot-Plug And Hot-Swap

    Chapter 6 Hot-Plug and Hot-Swap Introduction Notes As illustrated in Figures 6.1 through 6.3, a PCIe® switch may be used in one of three hot-plug configura- tions. Figure 6.1 illustrates the use of the PES12N3 in an application in which the two downstream ports are connected to slots into which add-in cards may be hot-plugged.

  • Page 56: Figure 6.2 Hot-Plug With Switch On Add-In Card Application

    IDT Hot-Plug and Hot-Swap Introduction Notes Upstream Link Add-In Card Port A GPIO Hot-Plug Signals PES12N3 Port B Port C PCI Express PCI Express Device Device Figure 6.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port A...

  • Page 57: Hot-Plug With Downstream Port(S) Connected To A Slot

    IDT Hot-Plug and Hot-Swap Introduction Notes The PCI Express® Base Specification revision 1.0a allowed a hot-plug attention indicator, power indi- cator, and attention button to be located on the board on which the slot is implemented or on the add-in board.

  • Page 58: Table 6.8 Smbus I/O Expander Signals

    IDT Hot-Plug and Hot-Swap Introduction Notes The port B and C electromechanical interlock outputs are only used in PCIe 1.1 mode (i.e., HPMODE bit set). These signals are driven to their negated state in PCIe 1.0a mode. SMBus I/O Expander...
  • Page 59 IDT Hot-Plug and Hot-Swap Introduction Notes The I/O expander has an open drain interrupt output that is asserted when a pin configured as an input changes state from the value previously read. The interrupt output from the SMBus I/O expander should be connected to GPIO[2], and GPIO[2] should be initialized during configuration to operate in alternate function mode as the Hot-plug I/O expander interrupt input.

  • Page 60: Hot-Plug With Switch On An Add-In Card

    IDT Hot-Plug and Hot-Swap Introduction Notes A downstream POWER_INDICATOR_ON, POWER_INDICATOR_BLINK, or POWER_INDICATOR_OFF message is sent down on port B or C when the hot-plug controller associated with the port is enabled and the state of the Power Indicator Control (PIC) field is modified in the PB_PCIESCTL or PC_PCIESCTL register.

  • Page 61: Hot-Swap

    The hot-swap I/O buffers of the PES12N3 may also be used to construct proprietary hot-swap systems. For a detailed specification of I/O buffer characteristic, see the 89HPES12N3 Data Sheet on the IDT web site. PES12N3 User Manual 6 - 7 June 7, 2006...
  • Page 62 IDT Hot-Plug and Hot-Swap Hot-Swap Notes PES12N3 User Manual 6 - 8 June 7, 2006...

  • Page 63: Smbus Interfaces

    Chapter 7 SMBus Interfaces Introduction Notes The PES12N3 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES12N3, allowing every register in the device to be read or written by an external SMBus master.

  • Page 64: Smbus Registers

    IDT SMBus Interfaces SMBus Registers Notes some systems, this external SMBus master interface may be implemented using general purpose I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these systems, the PES12N3 may be configured to operate in a split configuration as shown in Figure 7.1(b).

  • Page 65: Table 7.2 Smbusctl - Smbus Control

    IDT SMBus Interfaces SMBus Registers Notes Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock prescalar value used during master SMBus transac- tions. The prescalar clock period is equal to 32 ns multi- plied by the value in this field.

  • Page 66: Master Smbus Interface

    IDT SMBus Interfaces Master SMBus Interface Master SMBus Interface Notes The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM. It is also used to support an optional I/O expander for hot-plug signals.

  • Page 67: Table 7.4 Base Addresses For Pci Configuration Spaces In The Pes12N3

    IDT SMBus Interfaces Master SMBus Interface Notes Base Address Value PCI Configuration Space used to form CSR System Address Upstream Port A 0x0000 Downstream Port B 0x1000 Downstream Port C 0x2000 Table 7.4 Base Addresses for PCI Configuration Spaces in the PES12N3...

  • Page 68: Figure 7.2 Single Double Word Initialization Sequence Format

    IDT SMBus Interfaces Master SMBus Interface Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 DATA[7:0] Byte 3 DATA[15:8] Byte 4 DATA[23:16] Byte 5 DATA[31:24] Figure 7.2 Single Double Word Initialization Sequence Format The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.

  • Page 69: Figure 7.4 Configuration Done Sequence Format

    IDT SMBus Interfaces Master SMBus Interface Notes If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a configuration space (i.e., does not appear in Tables 9.6, 9.7, or 9.8), then the Unmapped Register Initializa- tion Attempt (URIA) bit is set in the SMBUSSTS register and the write is ignored.

  • Page 70: Hot-Plug I/O Expander

    IDT SMBus Interfaces Master SMBus Interface Notes Error Action Taken Configuration Done Sequence checksum - Set RSTHALT bit in PA_SWCTL register mismatch with that computed by the - ICSERR bit is set in the PA_SMBUSSTS register PES12N3 - Abort initialization, set DONE bit in the PA_SMBUSSTS register...

  • Page 71: Slave Smbus Interface

    IDT SMBus Interfaces Slave SMBus Interface Slave SMBus Interface Notes The slave SMBus interface provides the PES12N3 with a configuration, management and debug inter- face. Using the slave SMBus interface, an external master can read or write any software visible register in the device.

  • Page 72: Table 7.8 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Slave SMBus Interface Notes Name Description Field End of transaction indicator. Setting both START and END signifies a single transaction sequence 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence.

  • Page 73: Table 7.9 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Slave SMBus Interface Notes Byte Field Position Name Description CCODE Command Code. Slave Command Code field described in Table 7.8. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field.

  • Page 74: Table 7.11 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Slave SMBus Interface Notes Field Name Type Description Read/Write CSR Operation. This field encodes the CSR operation to be per- formed. 0 - CSR write 1 - CSR read Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus transaction was and Clear not claimed by a device.

  • Page 75: Table 7.12 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Slave SMBus Interface Notes Field Name Type Description Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address. When this bit is set the serial EEPROM SMBus address specified in the EEADDR is used instead of that specified in the MSMBADDR field in the SMBUSSTS register.

  • Page 76: Figure 7.9 Serial Eeprom Read Using Smbus Block Write/Read Transactions

    IDT SMBus Interfaces Slave SMBus Interface Notes PES12N3 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES12N3 Slave CCODE (PES12N3 not ready with data) SMBus Address START,END PES12N3 Slave CCODE PES12N3 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address...

  • Page 77: Figure 7.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Slave SMBus Interface Notes PES12N3 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES12N3 Slave CCODE ADDRU SMBus Address END, Byte PES12N3 Slave CCODE (PES12N3 not ready with data) SMBus Address START,Word PES12N3 Slave CCODE SMBus Address...
  • Page 78 IDT SMBus Interfaces Slave SMBus Interface Notes PES12N3 User Manual 7 - 16 June 7, 2006...

  • Page 79: General Purpose I/O

    Chapter 8 General Purpose I/O Introduction Notes The PES12N3 has eight General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Control and Status (GPIOCS) register located in upstream port A’s PCI configuration space (see Table 8.1).

  • Page 80: Gpio Configuration

    IDT General Purpose I/O GPIO Configuration Notes Alternate Alternate GPIO Function Alternate Function Description Function Pin Name Pin Type IOEXPINTN Hot-plug I/O expander interrupt Input PAABN Hot-plug port A attention button Input PAAIN Hot-plug port A attention indicator output Output...

  • Page 81: Transparent Mode Operation

    Chapter 9 Transparent Mode Operation Introduction Notes When the PES12N3 is configured during a fundamental reset to operate in transparent mode or trans- parent mode with serial EEPROM initialization, the device functionally operates as illustrated in Figure 9.1. In this mode, the PES12N3 may logically viewed as consisting of three PCI-PCI transparent bridges, one per port, and an internal virtual PCI bus.

  • Page 82: End-To-End Crc

    IDT Transparent Mode Operation End-to-End CRC End-to-End CRC Notes PCIe® defines an optional end-to-end CRC associated with TLPs. The PES12N3 fully supports ECRC for all TLPs that pass through the switch except for transactions utilizing gathered and routed to root complex implicit routing. For transactions received with this routing type, the ECRC is discarded and not checked and the resulting gathered message is generated without an ECRC.

  • Page 83: Table 9.2 Physical Layer Errors

    IDT Transparent Mode Operation Error Detection and Handling Notes PCIe Base 1.0a Error Condition Specification Action Taken Section Invalid symbol or running disparity error 4.2.1.3 Correctable error processing detected. Any TLP or DLLP framing rule violation. 4.2.2.1 Correctable error processing 8b/10b decode error 4.2.4.4...

  • Page 84: Table 9.4 Transaction Layer Errors

    IDT Transparent Mode Operation Error Detection and Handling Notes PCIe Base 1.0a Error Condition Specification Action Taken Section ECRC check failure 2.7.1 None. The PES12N3 does not check ECRC for transactions that terminate in the switch. Malformed TLP Fatal error processing.
  • Page 85 IDT Transparent Mode Operation Error Detection and Handling Notes TLP Type Error Check Memory read request (32- and 64-bit address The packet length is correct. mode) 32-bit address mode: 3 doublewords when ECRC is present, 4 doublewords otherwise 64-bit address mode: 4 doublewords when ECRC...

  • Page 86: Configuration Requests

    IDT Transparent Mode Operation Port Configuration Space Organization Configuration Requests Notes The PCI-PCI bridges associated with ports A, B and C all have configuration registers that may be accessed with Type 0 configuration read and write requests. PCIe allows multiple outstanding configuration read and write requests.

  • Page 87: Figure 9.2 Port Configuration Space Organization

    IDT Transparent Mode Operation Port Configuration Space Organization Notes 0x000 Type 1 Configuration Header 0x040 PCI Express Capability Structure 0x070 PCI Power Management Capability Structure 0x07C MSI Capability Structure Configuration Space *** Ports B & C Only *** (64 DWords)

  • Page 88: Upstream Port A Configuration Space Registers

    IDT Transparent Mode Operation Upstream Port A Configuration Space Registers Upstream Port A Configuration Space Registers Notes All configuration space locations not listed in Table 9.6 return a value of zero when read. Writes to these locations are ignored and have no side-effects.
  • Page 89 IDT Transparent Mode Operation Upstream Port A Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x032 Word PA_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25 0x034 Byte PA_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25...

  • Page 90: Register Specialization

    IDT Transparent Mode Operation Upstream Port A Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0D4 DWord PA_TMCNT2 TMCNT2 - Test Mode Count 2 (0x0D4) on page 9-60 0x0F4 Word PA_INTSTS INTSTS - Interrupt Status (0x0F4) on page 9-49...

  • Page 91: Downstream Port B Configuration Space Registers

    IDT Transparent Mode Operation Downstream Port B Configuration Space Registers Notes Field Default Type Description Field Name Value SLOT Slot Implemented. This bit is set when the PCI Express link associated with this Port is connected to a slot. Does not apply to the upstream port and should be set to zero.
  • Page 92 IDT Transparent Mode Operation Downstream Port B Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x028 DWord PB_PMBASEU PMBASEU - Prefetchable Memory Base Upper (0x028) on page 9-24 0x02C DWord PB_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page...

  • Page 93: Register Specialization

    IDT Transparent Mode Operation Downstream Port B Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F8 DWord PB_ECFGADDR ECFGADDR - Extended Configuration Space Access Address (0x0F8) on page 9-49 0x0FC DWord PB_ECFGDATA ECFGDATA - Extended Configuration Space Access Data...

  • Page 94: Downstream Port C Configuration Space Registers

    IDT Transparent Mode Operation Downstream Port C Configuration Space Registers Downstream Port C Configuration Space Registers Notes All configuration space locations not listed in Table 9.8 return a value of zero when read. Writes to these locations are ignored and have no side-effects.
  • Page 95 IDT Transparent Mode Operation Downstream Port C Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x032 Word PC_IOLIMITU IOLIMITU - I/O Limit Upper (0x032) on page 9-25 0x034 Byte PC_CAPPTR CAPPTR - Capabilities Pointer (0x034) on page 9-25...

  • Page 96: Register Specialization

    IDT Transparent Mode Operation Downstream Port C Configuration Space Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x100 DWord PC_PCIEVCECAP PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100) on page 9-50 0x104 DWord PC_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x104) on page 9-50...

  • Page 97: Generic Pci To Pci Bridge Register Definition

    Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit ven- dor ID value assigned to IDT. See section Vendor ID on page 1-4. DID - Device Identification (0x002) Field Default Type Description Field Name...
  • Page 98 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value PERRE Parity Error Enable. The Master Data Parity Error bit is set in the PCI Status register (PCISTS) if this bit is set and the bridge receives a poisoned completion or a poisoned write.
  • Page 99 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 10:9 DEVT DEVSEL# Timing. Not applicable. STAS Signalled Target Abort. Not applicable since a target abort is never signalled. RTAS Received Target Abort. Not applicable.
  • Page 100 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes CLS - Cache Line Size (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s functionality but may be read and written by software.
  • Page 101 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes PBUSN - Primary Bus Number (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary inter- face of the bridge is connected.
  • Page 102 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes IOLIMIT - I/O Limit (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
  • Page 103 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes MBASE - Memory Base (0x020) Field Default Type Description Field Name Value Reserved 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT regis- ters are used to control the forwarding of non-prefetchable transactions between the primary and secondary interfaces of the bridge.
  • Page 104 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes PMLIMIT - Prefetchable Memory Limit (0x026) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing.
  • Page 105 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes IOLIMITU - I/O Limit Upper (0x032) Field Default Type Description Field Name Value 15:0 IOLIMITU Prefetchable IO Limit Upper. This field specifies the upper 16-bits of IOLIMIT. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.

  • Page 106: Pci Express Capability Structure

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes BCTRL - Bridge Control (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the bridges response to poisoned TLPs on the secondary inter- face.
  • Page 107 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 15:8 NXTPTR 0x70 Next Pointer. This field contains a pointer to the next capability structure. 19:16 PCI Express Capability Version. This field indicates the PCI-SIG defined PCI Express capability structure version number.
  • Page 108 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value Power Indicator Present. When set, this bit indicates that a Power Indicator is implemented on the card/module. This bit should not be set on downstream ports.
  • Page 109 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value ETFEN Extended Tag Field Enable. Since the transparent bridge never generates a transaction that requires a completion, this bit has no functional effect on the device during normal operation.
  • Page 110 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes PCIELCAP - PCI Express Link Capabilities (0x04C) Field Default Type Description Field Name Value MAXLNKSPD Maximum Link Speed. This field is hardwired to 0x1 to indicate 2.5 Gbps.
  • Page 111 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value LDIS Link Disable. When set, this bit disables the link. This field is hardwired to 0x0 for the upstream port. LRET Link Retrain.
  • Page 112 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes PCIESCAP - PCI Express Slot Capabilities (0x054) Field Default Type Description Field Name Value Attention Button Present. This bit is set when the Atten- tion Button is implemented for the port. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 113 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value Electromechanical Interlock Present. This bit is set if an electromechanical interlock is implemented on the chassis for this slot. This bit is unused in PCIe 1.0a mode (i.e., HPMODE bit cleared) and should be set to zero.
  • Page 114 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value CCIE Command Complete Interrupt Enable. This bit when set enables the generation of a Hot-Plug interrupt when a com- mand is completed by the Hot-Plug Controller.
  • Page 115 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.

  • Page 116: Power Management Capability Structure

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Power Management Capability Structure Notes PMCAP - PCI Power Management Capabilities (0x070) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0x1 identifies this capability as a PCI power management capability structure.
  • Page 117 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value PMEE PME Enable. When this bit is set, PME message genera- Sticky tion is enabled for the port. for ports B & C...
  • Page 118 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value Mode Configuration Switch. When this bit is set to zero, the PMPC register is configured as Mode1, shown in this table. When this bit is set to one, the register is configured as Mode2, shown in the Mode2 table.

  • Page 119: Message Signaled Interrupt Capability Structure

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value Mode Configuration Switch. When this bit is set to zero, the PMPC register is configured as Mode1, shown in the Mode1 table. When this bit is set to one, the register is con- figured as Mode2, shown in this table.

  • Page 120: Switch Control And Status Registers

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes MSIUADDR - Message Signaled Interrupt Upper Address (0x084) Field Default Type Description Field Name Value 31:0 UADDR Upper Message Address. This field specifies the upper portion of the DWORD address of the MSI memory write transaction.
  • Page 121 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value PALREV HWINIT PCI Express Port A Lane Reverse. This bit reflects the value of the PALREV signal sampled during the fundamen- tal reset.
  • Page 122 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value INTD INTD Aggregated State. Aggregated switch state for INTD. 0x0 - (negated) INTD negated 0x1 - (asserted) INTD asserted LOCKDIS RW1C Lock Discard.
  • Page 123 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value PALREV HWINIT Port A Lane Reversal. When this bit is set, the lanes asso- ciated with port A are reversed. The initial value of this reg- ister corresponds to the state of the PALREV pin.
  • Page 124 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 17:13 TSTCLK0SEL Test Clock 0 Output Select. This field selects the clock output driven on the TSTCLK0 pin (GPIO[6] alternate func- tion).
  • Page 125 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes GPIOCS - General Purpose I/O Control and Status (0x0A8) Field Default Type Description Field Name Value GPIOFUNC GPIO Function. Each bit in this field controls the corre- sponding GPIO pin. When set to a one, the corresponding GPIO pin operates as the alternate function as defined in Chapter 8, General Purpose I/O.
  • Page 126 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value NAERR RW1C No Acknowledge Error. This bit is set if an unexpected NACK is observed during a master SMBus transaction. The setting of this bit may indicate the following: that the addressed device does not exist on the SMBus (i.e.,...
  • Page 127 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 19:18 SSMBMODE Slave SMBus Mode. The slave SMBus contains internal glitch counters on the SSMBCLK and SSMBDAT signals that wait approximately 1uS before sampling or driving these signals.
  • Page 128 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value BUSY EEPROM Busy. This bit is set when a serial EEPROM read or write operation is in progress. 0x0 - (idle) serial EEPROM interface idle...

  • Page 129: Extended Configuration Space Access And Intx Status Registers

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value IOEXTM I/O Expander Test Mode. Setting this bit puts the I/O expander into a test mode. In this test mode, Port B and...

  • Page 130: Pci Express Virtual Channel Capability

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 31:12 Reserved Reserved. ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configuration space register value pointed to by the ECF- GADDR register.
  • Page 131 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 11:10 PATBLSIZ Port Arbitration Table Entry Size. This field indicates the size of the port arbitration table in the device. The value in the PES12N3 is set to 0x1 to indicate a 2-bit table.
  • Page 132 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 15:8 Reserved LPAT Load Port Arbitration Table. This bit, when set, updates the Port Arbitration logic from the Port Arbitration Table for the VC resource.
  • Page 133 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 134 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124) Field Default Type Description Field Name Value PHASE16 Phase 16. This field contains the port ID for the corre- sponding port arbitration period.

  • Page 135: Test Mode Registers

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Test Mode Registers Notes TMCTL - Test Mode Control (0x0BC) Field Default Type Description Field Name Value PAEN 0xFF Port A Enable. Each bit in this field corresponds to a port lane (e.g., bit zero corresponds to lane zero of the port).
  • Page 136 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value TXRS Transmit Re-Sync. Writing a one to this bit position while the PES12N3 is in a test mode that requires synchroniza- tion, causes the PRBS or pattern generator on each lane to start a synchronization sequence.
  • Page 137 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 15:8 PBSA RW1C Port B Synchronization Achieved. Each bit in this field corresponds to a port lane (e.g., bit zero corresponds to lane zero of the port).
  • Page 138 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 14:13 TMCNTPSEL2 Test Mode Count Port Select 2. In SerDes test mode, this field selects the port for which SerDes lane failures are...
  • Page 139 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 31:30 Reserved Reserved field. TMCNT0 - Test Mode Count 0 (0x0CC) Field Default Type Description Field Name Value 15:0 TMERRCNT0 Test Mode Error Count 0. When the switch is configured...

  • Page 140: System Integrity

    IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes TMCNT2 - Test Mode Count 2 (0x0D4) Field Default Type Description Field Name Value 15:0 TMERRCNT4 Test Mode Error Count 4. When the switch is configured to operate in a SerDes test mode, and an error is detected...
  • Page 141 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes Field Default Type Description Field Name Value 15:8 LENGTH Error Match Length. When the GBEEP bit is set, bad par- ity is generated for all double words in TLPs emitted to the switch core (i.e., those received on the ingress port or gen-...
  • Page 142 IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition Notes PES12N3 User Manual 9 - 62 June 7, 2006...

  • Page 143: Test And Debug

    Chapter 10 Test and Debug Device Test Modes Notes In addition to normal operating mode, the PES12N3 has four test modes. These test modes are selected by asserting the appropriate test mode value on the Switch Mode (SWMODE[3:0]) pins during a funda- mental reset.

  • Page 144: Internal Pseudo Random Bit Stream Self-Test Test Mode (Swmode[3:0] = 0Xa)

    IDT Test and Debug Device Test Modes Internal Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0] Notes = 0xA) In the Internal Pseudo Random Bit Stream Self-test Test mode, a pseudo random bit stream is gener- ated, looped back internally through the SerDes, and checked. This mode is graphically illustrated in Figure 10.2.

  • Page 145: External Pseudo Random Bit Stream Self-Test Test Mode (Swmode[3:0] = 0Xb)

    IDT Test and Debug Device Test Modes Notes Errors on up to six lanes may be concurrently counted using the six error counters. When a lane is selected by a Test Mode Count Lane Select (TMCNTLSEL[0..5]) and the corresponding Test Mode Count Port Select (TMCNTPSEL[0..5]) fields in the port A Test Mode Count Configuration (TMCNTCTL) register,...

  • Page 146: Table 10.2 Serdes Broadcast Test Mode Operation Transmit Delay Operation

    IDT Test and Debug Device Test Modes Symbol Transmitted Symbol Received Clock on Port C Port C Lane Port A Lane Port B Lane Cycle Lane 0 Table 10.2 SerDes Broadcast Test Mode Operation Transmit Delay Operation PES12N3 User Manual...

  • Page 147: Serdes Test Clock

    IDT Test and Debug SerDes Test Clock SerDes Test Clock Notes Each of the six on-chip PLLs generates a 250 MHz clock. The output of any of these PLL clocks divided by four (i.e., a 62.5 MHz clock) may be output on GPIO alternate function pins. In addition, the 2.5 GHz recovered SerDes receive clock from any of the 24 lanes divided by 40 (i.e., 62.5 MHz) may be selected.
  • Page 148 IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 - 6 June 7, 2006...

  • Page 149: Jtag Boundary Scan

    Chapter 11 JTAG Boundary Scan Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES12N3: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 150: Table 11.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Signal Definitions Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 151: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PEALREV face PEARN[7:0] PEARP[7:0] PEATN[7:0] PEATP[7:0] PEBLREV PEBRN[7:0] PEBRP[7:0] PEBTN[7:0] PEBTP[7:0] PECLREV PECRN[7:0] PECRP[7:0] PECTN[7:0] PECTP[7:0] PEREFCLKN[1:0] PEREFCLKP[1:0] REFCLKM SMBus...

  • Page 152: Test Data Register (Dr)

    IDT JTAG Boundary Scan Test Data Register (DR) Test Data Register (DR) Notes The Test Data register contains the following: Bypass register Boundary Scan registers Device ID register These registers are connected in parallel between a common serial input and a common serial data output and are described in the following sections.

  • Page 153: Figure 11.4 Diagram Of Output Cell

    IDT JTAG Boundary Scan Test Data Register (DR) Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 11.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 11.5.

  • Page 154: Instruction Register (Ir)

    IDT JTAG Boundary Scan Instruction Register (IR) Notes From previous cell Output enable from core Output Enable Cell EXTEST Output from core Capture Cell Input to core To next cell Figure 11.6 Diagram of Bidirectional Cell Instruction Register (IR) The Instruction register allows an instruction to be shifted serially into the processor at the rising edge of JTAG_TCK.

  • Page 155: Extest

    IDT JTAG Boundary Scan Instruction Register (IR) Notes Instruction Definition Opcode HIGHZ Tri-states all output and bidirectional boundary scan cells. 000011 RESERVED Behaviorally equivalent to the BYPASS instruction as per the IEEE 000100 — Std. 1149.1 specification. However, the user is advised to use the 100011 explicit BTPASS instruction.

  • Page 156: Clamp

    Bit(s) Mnemonic Description Reset reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x800C This field identifies the silicon as PES12N3. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES12N3.

  • Page 157: Usage Considerations

    IDT JTAG Boundary Scan Usage Considerations Usage Considerations Notes As previously stated, there are internal pull-ups on JTAG_TRST_N, JTAG_TMS, and JTAG_TDI. However, JTAG_TCK also needs to be driven to a known value. It is best to either drive a zero on the JTAG_TCK pin when it is not being used or to use an external pull-down resistor.
  • Page 158 IDT JTAG Boundary Scan Usage Considerations Notes PES12N3 User Manual 11 - 10 June 7, 2006...

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