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IDT 89HPES5T5 Preliminary User's Manual

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IDT
89HPES5T5
™
PCI Express® Switch
Preliminary User Manual
January 2011
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2011 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89HPES5T5

  • Page 1 ® 89HPES5T5 ™ PCI Express® Switch Preliminary User Manual January 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Content Summary Chapter 1, “PES5T5 Device Overview,” provides a complete introduction to the performance capabili- ties of the 89HPES5T5. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.
  • Page 4 Notes To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included. Throughout this manual, when describing signal transitions, the following terminology is used. Rising edge indicates a low-to-high (0 to 1) transition.
  • Page 5 Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Table 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Note: Software in the context of this register terminology refers to modifications made by PCIe root configuration writes to registers made through the slave SMBus interface, or serial EEPROM register initialization.

  • Page 6: Reference Documents

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.
  • Page 7 Revision History Notes June 5, 2007: Initial Publication. July 11, 2007: Corrected AERUCS to AERUES in AERCTL register, Chapter 8. July 16, 2007: Made numerous minor edits throughout manual. January 23, 2008: In Table 9.2, changed pins PE0RN/RP/TN/TP to read [0] instead of [1:0]. September 24, 2009: In Chapter 3, change made to L2 description in Link States section.
  • Page 8 Notes PES5T5 User Manual January 28, 2011...

  • Page 9: Table Of Contents

    Table of Contents ® PES5T5 Device Overview Notes Introduction ............................. 1-1 List of Features ..........................1-1 System Diagrams..........................1-3 Logic Diagram..........................1-4 SSID/SSVID..........................1-4 Device Serial Number Enhanced Capability................1-5 Pin Description..........................1-5 Pin Characteristics ..........................1-9 System Identification........................1-10 Vendor ID..........................1-10 Device ID ..........................
  • Page 10 IDT Table of Contents Notes General Purpose Inputs/Outputs Introduction ............................. 5-1 GPIO Configuration ........................5-1 GPIO Pin Configured as an Input ................... 5-2 GPIO Pin Configured as an Output ..................5-2 GPIO Pin Configured as an Alternate Function..............5-2 SMBus Interfaces Introduction .............................
  • Page 11 IDT Table of Contents Notes Power Budgeting Enhanced Capability ................9-49 Switch Control and Status Registers ..................9-51 Internal Switch Error Control and Status Registers .............. 9-61 Wakeup Protocol Registers ....................9-64 JTAG Boundary Scan Introduction ........................... 10-1 Test Access Point ......................... 10-1 Signal Definitions ..........................
  • Page 12 IDT Table of Contents Notes PES5T5 User Manual January 28, 2011...
  • Page 13 List of Tables ® Table 1.1 PCI Express Interface Pins....................1-5 Notes Table 1.2 SMBus Interface Pins ......................1-6 Table 1.3 General Purpose I/O Pins....................1-6 Table 1.4 System Pins.........................1-7 Table 1.5 Test Pins..........................1-8 Table 1.6 Power and Ground Pins....................... 1-8 Table 1.7 Pin Characteristics.......................
  • Page 14 IDT List of Tables Notes PES5T5 User Manual January 28, 2011...
  • Page 15 List of Figures ® Figure 1.1 PES5T5 Architectural Block Diagram ................1-3 Notes Figure 1.2 PES5T5 Logic Diagram .....................1-4 Figure 1.3 PES5T5 Port Configuration ....................1-11 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
  • Page 16 IDT List of Figures Notes PES5T5 User Manual viii January 28, 2011...
  • Page 17 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-40 AERCTL - AER Control (0x118)......................9-41 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 18 IDT Register List Notes PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-21 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-31 PCIEDCTL - PCI Express Device Control (0x048)..................9-22 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-31 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-23 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................9-31...
  • Page 19 IDT Register List Notes SWTOCTL - Switch Time-Out Control (0x4E4)..................9-63 SWTORCTL - Switch Time-Out Reporting Control (0x4E8)..............9-63 VCR0CAP- VC Resource 0 Capability (0x210)..................9-45 VCR0CTL- VC Resource 0 Control (0x214)....................9-46 VCR0STS - VC Resource 0 Status (0x218)....................9-47 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............9-47 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............9-48...
  • Page 20 IDT Register List Notes PES5T5 User Manual January 28, 2011...

  • Page 21: Pes5T5 Device Overview

    Introduction Notes The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connec- tivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports.
  • Page 22 IDT PES5T5 Device Overview Notes 11 General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions...

  • Page 23: System Diagrams

    IDT PES5T5 Device Overview System Diagrams Packet Queuing Memory Structure Write Read Processor Processor GPIO Reset Completion Processor Message Egress Hot Plug Processor Parser Return Buffer Ingress Parser SMBUS CSRM 1-lane 1-lane 1-lane 1-lane 4-lane Stack Stack Stack Stack Stack...

  • Page 24: Logic Diagram

    IDT PES5T5 Device Overview Logic Diagram Notes PCI Express Switch PEREFCLKP PE0TP[0] Reference SerDes Output PEREFCLKN PE0TN[0] Clock Port 0 REFCLKM PCI Express PE0RP[0] Switch PCI Express PE2TP[0] SerDes Input Switch PE0RN[0] Port 0 SerDes Output PE2TN[0] Port 2 PCI Express...

  • Page 25: Device Serial Number Enhanced Capability

    IDT PES5T5 Device Overview Device Serial Number Enhanced Capability Notes The PES5T5 contains the mechanisms necessary to implement the PCI express device serial number enhanced capability. However, in the default configuration this capability structure is not enabled. To enable the device serial number enhanced capability, the Serial Number Lower Doubleword (SNUMLDW) and the Serial Number Upper Doubleword (SNUMUDW) registers should be initialized.

  • Page 26: Table 1.3 General Purpose I/O Pins

    IDT PES5T5 Device Overview Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus.

  • Page 27: Table 1.4 System Pins

    IDT PES5T5 Device Overview Notes Signal Type Name/Description GPIO[7] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] General Purpose I/O.

  • Page 28: Table 1.5 Test Pins

    IDT PES5T5 Device Overview Notes Signal Type Name/Description RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES5T5 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins.

  • Page 29: Pin Characteristics

    IDT PES5T5 Device Overview Pin Characteristics Notes Note: Some input pads of the PES5T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.

  • Page 30: System Identification

    IDT PES5T5 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor System Pins APWRDISN LVTTL Input pull-down CCLKDS pull-up CCLKUS pull-up MSMBSMODE pull-down PERSTN RSTHALT pull-down SWMODE[2:0] pull-down WAKEN open-drain EJTAG / JTAG JTAG_TCK LVTTL pull-up JTAG_TDI...

  • Page 31: Jtag Id

    IDT PES5T5 Device Overview JTAG ID Notes The JTAG ID is: – Version: Same value as Revision ID. See Table 1.9 – Part number: Same value as base Device ID. See Table 1.8. – Manufacturer ID: 0x33 – LSB: 0x1 Port Configuration The PES5T5 supports five ports: one x4 upstream port and four x1 downstream ports.
  • Page 32 IDT PES5T5 Device Overview Notes PES5T5 User Manual 1 - 12 January 28, 2011...

  • Page 33: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES5T5 has a differential reference clock input that is used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both refer- ence clock input pairs be driven from a common clock source.
  • Page 34 IDT Clocking, Reset, and Initialization Clock Operation Notes Port 2 PES5T5 Port 0 Root Complex Port 5 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock)
  • Page 35 IDT Clocking, Reset, and Initialization Clock Operation Notes PES5T5 Port 2 Port 0 Root Complex Port 5 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator * Clock Generator Clock Generator * May be unique for each EP Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES5T5 during...

  • Page 36: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes May Be Signal Description Overridden CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This pin is used as the initial value of the Slot Clock Configura- tion bit in all of the Link Status Registers for downstream ports.

  • Page 37: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Reset Notes The PES5T5 defines four reset categories: fundamental reset, hot reset, upstream secondary bus reset, and downstream secondary bus reset. – A fundamental reset causes all logic in the PES5T5 to be returned to an initial state.
  • Page 38 IDT Clocking, Reset, and Initialization Clock Operation Notes If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the current link parameters.

  • Page 39: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes REFCLK Tpvperl PERSTN RSTHALT 20ms max. 11μs SerDes PLL Reset and Lock CDR Reset & Lock Link Training Ready for Normal Operation 1.01 ms max. Master SMBus Idle Serial EEPROM Initialization Ready...

  • Page 40: Upstream Secondary Bus Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes the current link parameters. If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the SMBUSSTS register.

  • Page 41: Downstream Port Reset Outputs

    IDT Clocking, Reset, and Initialization Clock Operation Notes When a downstream secondary bus reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted. 2. All TLPs received from corresponding downstream port and queued in the PES5T5 are discarded.

  • Page 42: Power Good Controlled Reset Output

    IDT Clocking, Reset, and Initialization Clock Operation Power Good Controlled Reset Output Notes As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply.

  • Page 43: Theory Of Operation

    Chapter 3 Theory of Operation ® Port Interrupts Notes The upstream port (Port 0) generates legacy interrupts and MSIs to report internal switch errors such as parity errors and errors in reading configuration registers. Downstream ports support generation of legacy interrupts and MSIs.

  • Page 44: Table 3.2 Pes5T5 Downstream To Upstream Port Interrupt Routing

    IDT Theory of Operation Notes The PES5T5 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through D) at each port. – The value of the INTA, INTB, INTC and INTD aggregated state for the entire switch may be deter- mined by examining the corresponding field in the upstream port’s Interrupt Status (P0_INTSTS)

  • Page 45: Link Operation

    Chapter 4 Link Operation ® Introduction Notes The PES5T5 is a 5 port switch device. The upstream port link width is configured as a x1 link width and all the downstream ports are also configured as x1 link widths. Polarity Inversion Each port of the PES5T5 supports automatic polarity inversion as required by the PCIe specification.

  • Page 46: Slot Power Limit Support

    IDT Link Operation Slot Power Limit Support Notes The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream switch port or root port to the upstream port of a connected device or switch. Upstream Port When a Set_Slot_Power_Limit message is received by the upstream switch port, the fields in the message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.

  • Page 47: Active State Power Management

    IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.1 PES5T5 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.

  • Page 48: Link Status

    IDT Link Operation Notes sition to the L1 state from its link partner. Note that L1 entry requests are only made by the PES5T5 upstream port. If the link partner acknowledges the transition, the L1 state is entered. Otherwise the L0s state is entered.

  • Page 49: General Purpose Inputs/Outputs

    Chapter 5 General Purpose Inputs/Outputs ® Introduction Notes The PES5T5 has 11 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.

  • Page 50: Gpio Pin Configured As An Input

    IDT General Purpose Inputs/Outputs GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.
  • Page 51 IDT General Purpose Inputs/Outputs PES5T5 User Manual 5 - 3 January 28, 2011...
  • Page 52 IDT General Purpose Inputs/Outputs PES5T5 User Manual 5 - 4 January 28, 2011...
  • Page 53 IDT General Purpose Inputs/Outputs PES5T5 User Manual 5 - 5 January 28, 2011...
  • Page 54 IDT General Purpose Inputs/Outputs Notes PES5T5 User Manual 5 - 6 January 28, 2011...

  • Page 55: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES5T5 contains two SMBus interfaces. The slave SMBus interface provides full access to all soft- ware visible registers in the PES5T5, allowing every register in the device to be read or written by an external SMBus master.

  • Page 56: Master Smbus Interface

    IDT SMBus Interfaces Notes the PES5T5 may be configured to operate in a split configuration as shown in Figure 6.1(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is not required.

  • Page 57: Table 6.2 Pes5T5 Compatible Serial Eeproms

    IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.2 PES5T5 Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.
  • Page 58 IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.3 Sequential Double Word Initialization Sequence Format...

  • Page 59: Table 6.3 Serial Eeprom Initialization Errors

    IDT SMBus Interfaces Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence.

  • Page 60: I/O Expanders

    IDT SMBus Interfaces Notes To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy (i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to...

  • Page 61: Table 6.5 I/O Expander Default Output Signal Value

    IDT SMBus Interfaces Notes The default value of I/O expander outputs is shown in Table 6.5. Note that this default value may be modified via serial EEPROM or SMBus configuration prior to SMBus initialization by changing the state of the PCI Express Slot Control Register (PCIESCTL) or Hot-Plug Configuration Control (HPCFGCTL).
  • Page 62 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES5T5 to I/O expander four (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.

  • Page 63: Table 6.6 I/O Expander 0 Signals

    IDT SMBus Interfaces Notes For example, a user who neglects to configure a GPIO as an alternate function may use this feature to determine that master SMBus transactions to the I/O expander function properly and that the issue is with the interrupt logic.

  • Page 64: Table 6.7 I/O Expander 1 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 13 (I/O-1.5) P4PIN Port 4 power indicator output 14 (I/O-1.6) P4PEP Port 4 power enable output 15 (I/O-1.7) P4ILOCKP Port 4 electromechanical interlock Table 6.6 I/O Expander 0 Signals (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

  • Page 65: Table 6.9 I/O Expander 4 Signals

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 3 (I/O-0.3) Reserved Tie High 4 (I/O-0.4) Reserved Tie High or Low 5 (I/O-0.5) Reserved Tie High or Low 6 (I/O-0.6) Reserved Tie High or Low 7 (I/O-0.7) Reserved Tie High or Low 8 (I/O-1.0)

  • Page 66: Slave Smbus Interface

    IDT SMBus Interfaces Slave SMBus Interface Notes The slave SMBus interface provides the PES5T5 with a configuration, management and debug inter- face. Using the slave SMBus interface, an external master can read or write any software visible register in the device.

  • Page 67: Table 6.11 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Notes Name Description Field End of transaction indicator. Setting both START and END signifies a single transaction sequence 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence.

  • Page 68: Table 6.13 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Position Name Description ADDRL Address Low. Lower 8-bits of the doubleword CSR system address of register to access. ADDRU Address Upper. Upper 6-bits of the doubleword CSR system address of register to access. Bits 6 and 7 in the byte must be zero and are ignored by the hardware.

  • Page 69: Table 6.14 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Serial EEPROM Read or Write Operation Table 6.13 indicates the sequence of data as it is presented on the slave SMBus following the byte address of the Slave SMBus interface. Byte Field Positio Description Name CCODE Command Code.

  • Page 70: Table 6.15 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Name Type Description Field Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address. When this bit is set the serial EEPROM SMBus address specified in the EEADDR is used instead of that specified in the ADDR field in the EEPROMINTF register.
  • Page 71 IDT SMBus Interfaces Notes PES5T5 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES5T5 Slave CCODE (PES5T5 not ready with data) SMBus Address START,END PES5T5 Slave CCODE PES5T5 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address...
  • Page 72 IDT SMBus Interfaces Notes PES5T5 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES5T5 Slave CCODE ADDRU SMBus Address END, Byte PES5T5 Slave CCODE (PES5T5 not ready with data) SMBus Address START,Word PES5T5 Slave CCODE SMBus Address START,Word PES5T5 Slave...

  • Page 73: Power Management

    Chapter 7 Power Management ® Introduction Notes The PES5T5 supports the following device power management states: D0 Uninitialized, D0 Active, , and D3 . A power management state transition diagram for the states supported by the PES5T5 Cold is provided in Figure 7.1 and described in Table 7.1. A power management capability structure is located in the configuration space of each PCI-PCI bridge in the PES5T5.

  • Page 74: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software. D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 75: Power Express Power Management Fence Protocol

    IDT Power Management Power Express Power Management Fence Protocol Notes The Root complex takes the following steps to turn off power to a system: – The root places all devices in the D3 state – Upon entry to D3 , all devices transition their links to the L1 state –...

  • Page 76: Wakeup Protocol

    IDT Power Management Notes register. When the PWRBDVUL bit is cleared, these register are read-only and writes to these registers are ignored. To enable the power budgeting capability, the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM.

  • Page 77: Waken Signal As An Input

    IDT Power Management WAKEN Signal as an Input Notes The WAKEN signal may be configured as an input to make use of the PES5T5’s ability to translate WAKEN input to Beacon transmission (on the upstream link). To enable this feature, the following must be true: –...

  • Page 78: Auxiliary Power Control

    IDT Power Management Notes In Device OFF state, both main power and the auxiliary power is off. The device enters Inactive Standby when the auxiliary power is applied and Main Power is Off. When main power is applied the device enters the Device ON state. As shown in Figure 7.3, when main power is applied for the first time after auxiliary power is switched ON, the external POR circuitry is required to assert PERSTN and sequence the APWRDISN signal with respect to PERSTN .
  • Page 79 IDT Power Management Notes APWRDISN PERSTN 256 Clks 8 Clks a. L2 Mode Enabled, FRSticky bits initialized APWRDISN (High) PERSTN 256 Clks 8 Clks b. L2 Mode Enabled, FRSticky bits not initialized APWRDISN (Low) PERSTN 256 Clks 8 Clks b. L2 Mode Disabled Figure 7.3 L2 Mode Enable/Disable and FRSticky Bit Initialization...

  • Page 80: Pes5T5 Auxiliary Power Usage

    IDT Power Management Notes turned ON using in-band beacon or out-of-band WAKEN signaling when the traffic resumes). The signal is sampled High, resulting in retention of the state of the FRSticky bits. The APWRDISN signal input is sampled again 256 clock cycles after de-assertion of the fundamental reset (PERSTN). A high state of this signal continues to set the APWREN bit in the SWCTL register.

  • Page 81: Table 7.2 Auxiliary Power Enabled (Beacon Off)

    IDT Power Management Notes Current Estimate Item Comment (mA) 3.3 V IO Power In L2 mode, auxiliary power supply is Supply used to power up all the I/Os. Rambus L2 (2 Ser- Des quads ON with Beacon OFF in both the SerDes) Core Logic 3.3 V I/O...
  • Page 82 IDT Power Management Notes 3.3 V Regulator VDDIO VDDCORE +12V 1.0 V VDDAPE Switcher Regulator VDDPE PES5T5 1.5 V VTTPE Regulator Regulator 3.3 Vaux Power Voltage 1.0 V Regulator 1.5 V Figure 7.5 Conceptual Diagram of the PES5T5 Auxiliary Power Connection...

  • Page 83: Hot-Plug And Hot-Swap

    Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES5T5 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
  • Page 84 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES5T5 Port x Port y PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES5T5 Master SMBus...
  • Page 85 RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of corre- sponding PxILOCKP I/O expander signal output. Note: For further information on this register, please contact ssdhelp@idt.com. PES5T5 User Manual 8 - 3...

  • Page 86: Hot-Plug I/O Expander

    IDT Hot-Plug and Hot-Swap Notes When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.
  • Page 87 IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.

  • Page 88: Hot-Swap

    In summary, the PES5T5 meets all of the I/O requirements necessary to build a PICMG compliant hot- swap board or system. The hot-swap I/O buffers of the PES5T5 may also be used to construct proprietary hot-swap systems. See the 89HPES5T5 Data Sheet for a detailed specification of I/O buffer characteristics. PES5T5 User Manual...

  • Page 89: Configuration Registers

    Chapter 9 Configuration Registers ® Configuration Space Organization Notes Each software visible register in the PES5T55T5A is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES5T5A that cannot be accessed by the root. Each software visible register in the PES5T5A has a system address.

  • Page 90: Configuration Space Organization

    IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting...

  • Page 91: Table 9.2 Upstream Port 0 Configuration Space Registers

    IDT Configuration Registers Upstream Port (Port 0) Notes Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 9-11 0x002 Word P0_DID DID - Device Identification Register (0x002) on page 9-11 0x004...
  • Page 92 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 9-19 0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 9-21 0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 9-21...
  • Page 93 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 9-41 0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 9-41 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-...
  • Page 94 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x308 Dword P0_PWRBDV2 PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300) on page 9-50 0x30C Dword P0_PWRBDV3 PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300) on page 9-50 0x310...

  • Page 95: Downstream Ports (Ports 2 Through 5)

    IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x4E8 Dword P0_SWTORCTL SWTORCTL - Switch Time-Out Reporting Control (0x4E8) on page 9- 0x4EC Dword P0_SWTOCNT SWTOCNT - Switch Time-Out Count (0x4EC) on page 9-64 0x5CC Dword P0_WAKEUPCNT WAKEUPCNTL - Wakeup Protocol Control Register (0x5CC) on page 9-64 Table 9.2 Upstream Port 0 Configuration Space Registers (Part 5 of 5)
  • Page 96 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on page 9-18 0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-18 0x032 Word...
  • Page 97 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0D8 DWord Px_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) on page 9-35 0x0DC DWord Px_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) on page 9-35 0x0F0...
  • Page 98 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x280 Dword Px_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 9-49 0x284 Dword Px_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 9-50 0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-50...

  • Page 99: Register Definitions

    Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. See section Device ID on page 1-10. PCICMD - PCI Command Register (0x004) Field Default Type Description Field...
  • Page 100 IDT Configuration Registers Notes Field Default Type Description Field Name Value PERRE Parity Error Enable. The Master Data Parity Error bit is set in the PCI Status register (PCISTS) if this bit is set and the bridge receives a poisoned completion or generates a poi- soned write.
  • Page 101 IDT Configuration Registers Notes Field Default Type Description Field Name Value FB2B Fast Back-to-Back (FB2B). Not applicable. MDPED RW1C Master Data Parity Error Detected. This bit is set when the PERRE bit is set in the PCI Command register and the bridge receives a poisoned completion or generates a poi- soned write request on the primary side of the bridge.
  • Page 102 IDT Configuration Registers Notes CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s functionality but may be read and written by software. This field is implemented for compatibility with legacy soft- ware.
  • Page 103 IDT Configuration Registers Notes PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary inter- face of the bridge is connected.
  • Page 104 IDT Configuration Registers Notes IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
  • Page 105 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable trans- actions between the primary and secondary interfaces of the bridge.
  • Page 106 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:4 PMLIMIT Prefetchable Memory Address Limit. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forwarding of prefetchable transactions between the primary and secondary interfaces of the bridge. This field...
  • Page 107 IDT Configuration Registers Notes CAPPTR - Capabilities Pointer Register (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. This field specifies a pointer to the head of the capabilities structure. EROMBASE - Expansion ROM Base Address Register (0x038)
  • Page 108 IDT Configuration Registers Notes Field Default Type Description Field Name Value SERRE System Error Enable. This bit controls forwarding of ERR_NONFATAL or ERR_FATAL from the secondary inter- face of the bridge to the primary interface. Note that error reporting must be enabled in the Command...

  • Page 109: Pci Express Capability Structure

    IDT Configuration Registers PCI Express Capability Structure Notes PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure. 15:8 NXTPTR 0xC0 Next Pointer.
  • Page 110 IDT Configuration Registers Notes Field Default Type Description Field Name Value 11:9 E1AL Endpoint L1 Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L1 state to the L0 state. The value is hardwired to 0x0 as this field does not apply to a switch.
  • Page 111 IDT Configuration Registers Notes Field Default Type Description Field Name Value FEREN Fatal Error Reporting Enable. This bit controls reporting of fatal errors. URREN Unsupported Request Reporting Enable. This bit controls reporting of unsupported requests. Enable Relaxed Ordering. When set, this bit enables relaxed ordering.
  • Page 112 IDT Configuration Registers Notes Field Default Type Description Field Name Value NFED RW1C Non-Fatal Error Detected. This bit indicates the status of correctable errors. Errors are logged in this register regard- less of whether error reporting is enabled or not.
  • Page 113 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:12 L0SEL see text L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express link. This field depends on whether a common or separate reference clock is used.
  • Page 114 IDT Configuration Registers Notes Field Default Type Description Field Name Value Read Completion Boundary. This field is not applicable and is hardwired to zero. LDIS Link Disable. When set in a downstream port, this bit dis- ables the link. This bit is not applicable in the upstream port.
  • Page 115 IDT Configuration Registers Notes Field Default Type Description Field Name Value SCLK HWINIT Slot Clock Configuration. When set, this bit indicates that the component uses the same physical reference clock that the platform provides. The initial value of this field is the state of the CCLKUS signal for the upstream port and the CCLKDS signal for downstream ports.
  • Page 116 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power sup- plied by the slot. A Set_Slot_Power_Limit message is generated using this field whenever this register is written or when the link transi- tions from a non DL_Up status to a DL_Up status.
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSCE MRL Sensor Change Enable. This bit when set enables the generation of a Hot-Plug interrupt or wake-up event on a MRL sensor change event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP register.
  • Page 118 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.
  • Page 119 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Status. When an electrome- chanical interlock is implemented, this bit indicates the cur- rent status of the interlock. 0x0 - (disengaged) Electromechanical interlock disengaged 0x1 - (engaged) Electromechanical interlock engaged...

  • Page 120: Power Management Capability Structure

    IDT Configuration Registers Notes PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) Field Default Type Description Field Name Value 31:0 Reserved Reserved field.
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value 24:22 AUXI AUX Current. This 3 bit field reports auxiliary current requirements by the function to retain PME Context when the main power rail is removed 0x0 - (self) Self Powered...

  • Page 122: Message Signaled Interrupt Capability Structure

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:13 DSCALE Data Scale. The optional data register is not imple- mented. PMES RW1C PME Status. This bit is set if a PME is generated by the FRSticky port even if the PMEE bit is cleared. This bit is not set when the bridge is propagating a PME message but the port is not itself generating a PME.

  • Page 123: Subsystem Id And Subsystem Vendor Id

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction. The PES5T5A assumes that upstream and downstream ports generated MSIs are targeted to the root. Configuring the address contained in a port’s MSIADDR and MSIADDRU...

  • Page 124: Extended Configuration Space Access Registers

    IDT Configuration Registers Notes SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) Field Default Type Description Field Name Value 15:0 SSVID SubSystem Vendor ID. This field identifies the manufac- turer of the add-in card or subsystem. SSVID values are assigned by the PCI-SIG to insure unique- ness.

  • Page 125: Advanced Error Reporting (Aer) Enhanced Capability

    IDT Configuration Registers Advanced Error Reporting (AER) Enhanced Capability Notes AERCAP - AER Capabilities (0x100) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x1 indicates an advanced error reporting capability structure. 19:16 CAPVER Capability Version. The value of 0x1. indicates compatibil- ity with version 1 of the specification.
  • Page 126 IDT Configuration Registers Notes AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specificiation. Reserved Reserved field. DLPERR Data Link Protocol Error Mask. When this bit is set, the Sticky corresponding bit in the AERUES register is masked.
  • Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Mask. When this bit is set, the corresponding bit in Sticky the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 128 IDT Configuration Registers Notes Field Default Type Description Field Name Value UECOMP Unexpected Completion Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported error.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADVISO- RW1C Advisory Non-Fatal Error Status. This bit is set when an RYNF Sticky advisory non-fatal error is detected as described in Section 6.2.3.2.4 of the PCIe base 1.1 specification.
  • Page 130 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRCGE ECRC Generation Enable. When this bit is set, ECRC gen- Sticky eration is enabled. ECRCCC ECRC Check Capable. This bit indicates if the device is capable of checking ECRC.

  • Page 131: Device Serial Number Enhanced Capability

    IDT Configuration Registers Device Serial Number Enhanced Capability Notes SNUMCAP - Serial Number Capabilities (0x180) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x3 indicates a device serial number capability structure. 19:16 CAPVER Capability Version. The value of 0x1. indicates compatibil- ity with version 1 of the specification.
  • Page 132 IDT Configuration Registers Notes Field Default Type Description Field Name Value Reserved Reserved field. LPEVCCNT Low Priority Extended VC Count. The value of 0x0 indi- cates only implementation of the default VC. Reserved Reserved field. REFCLK Reference Clock. Time-based WRR is not implemented.
  • Page 133 IDT Configuration Registers Notes PVCCTL - Port VC Control (0x20C) Field Default Type Description Field Name Value LVCAT Load VC Arbitration Table. This bit, when set, updates the VC arbitration logic from the VC Arbitration Table for the VC resource.
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field. 31:24 PATBLOFF Upstream: Port Arbitration Table Offset. This field contains the offset...
  • Page 135 IDT Configuration Registers Notes Field Default Type Description Field Name Value VCEN VC Enable. This field, when set, enables a virtual channel. Since the PES5T5A implements only a single VC, this field is hardwired to one (enabled). VCR0STS - VC Resource 0 Status (0x218)
  • Page 136 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:24 PHASE6 Phase 6. This field contains the port ID for the corresponding port arbitration period. 31:28 PHASE7 Phase 7. This field contains the port ID for the corresponding port arbitration period.

  • Page 137: Power Budgeting Enhanced Capability

    IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:24 PHASE22 Phase 22. This field contains the port ID for the correspond- ing port arbitration period. 31:28 PHASE23 Phase 23. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 138 IDT Configuration Registers Notes PWRBDSEL - Power Budgeting Data Select (0x284) Field Default Type Description Field Name Value DVSEL Data Value Select. This field selects the Power Budgeting Data Value (PWRBDVx) register whose contents are reported in the Data (DATA) field of the Power Budgeting Data (PWRBD) register.

  • Page 139: Switch Control And Status Registers

    IDT Configuration Registers Switch Control and Status Registers Notes SWSTS - Switch Status (0x328) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. These configuration pins determine the PES5T5A switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization...
  • Page 140 IDT Configuration Registers Notes SWCTL - Switch Control (0x32C) Field Default Type Description Field Name Value FRST Fundamental Reset. Writing a one to this bit initiates a fun- damental reset. Writing a zero has no effect. This field always returns a value of zero when read.
  • Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value 13:9 Reserved Reserved field. CTDIS Disable Cut-Through Routing. When this bit is set, cut Sticky through routing of TLPs is disabled between all ports (i.e., they are routed in a stored and forwarded manner). When this bit is cleared, TLPs are routed in a cut-through manner when possible.
  • Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value IPXILOCKP Invert Polarity of PxILOCKP. When this bit is set, the polar- Sticky ity of the PxILOCKP output is inverted in all ports. IPXP- Invert Polarity of PxPWRGDN. When this bit is set, the...
  • Page 143 IDT Configuration Registers Notes GPIOFUNC - General Purpose I/O Control Function (0x338) Field Default Type Description Field Name Value 15:0 GPIOFUNC GPIO Function. Each bit in this field controls the corre- Sticky sponding GPIO pin. When set to a one, the corresponding GPIO pin operates as the alternate function as defined in Chapter 5, General Purpose Inputs/Outputs.
  • Page 144 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 Reserved Reserved field. EEPROM- Serial EEPROM Initialization Done. When the switch is DONE configured to operate in a mode in which serial EEPROM ini- tialization occurs during a fundamental reset, this bit is set when serial EEPROM initialization completes or when an error is detected.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value ICHECK- Ignore Checksum Errors. When this bit is set, serial Sticky EEPROM initialization checksum errors are ignored (i.e., the checksum always passes). 19:18 SSMB- Slave SMBus Mode. The slave SMBus contains internal...
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value 23:16 DATA EEPROM Data. A write to this field will initiates a serial EEPROM read or write operation, as selected by the OP field, to the address specified in the ADDR field.
  • Page 147 IDT Configuration Registers Notes Field Default Type Description Field Name Value IOEXTM IO Expander Test Mode. Setting this bit puts the I/O expander interface into a test mode. In this test mode, I/O expander output signals generated by the PES5T5A core are ignored and values supplied to the I/O expander corre- spond to value written to the IOEDATA field.
  • Page 148 IDT Configuration Registers Notes IOEXPADDR1 - SMBus I/O Expander Address 1 (0x358) Field Default Type Description Field Name Value Reserved Reserved field. IOE4ADDR I/O Expander 4 Address. This field contains the SMBus Sticky address assigned to I/O expander 4 on the master SMBus interface.

  • Page 149: Internal Switch Error Control And Status Registers

    IDT Configuration Registers Notes GPESTS - General Purpose Event Status (0x360) Field Default Type Description Field Name Value Reserved Reserved field. P2GPES Port 2 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal.
  • Page 150 IDT Configuration Registers Notes Field Default Type Description Field Name Value GBEEP Generate Bad End-to-End Parity. When this bit is set, bad Sticky parity is generated for all double words in TLPs emitted to the switch core from this port (i.e., those received on the ingress port or generated by the port) whose TLP header length field (i.e., bits seven through zero of byte zero of the...
  • Page 151 IDT Configuration Registers Notes SWERRCNT - Switch Internal Error Count (0x4E0) Field Default Type Description Field Name Value EEPEC End-to-End Parity Error Count. This field is incremented Sticky each time an end-to-end parity error is detected at the port until it saturates at its maximum count value (i.e., it does not roll over from 0xFF to 0x00).

  • Page 152: Wakeup Protocol Registers

    IDT Configuration Registers Notes Field Default Type Description Field Name Value CPTLPTO Completion TLP Time-Out Reporting. This field controls Sticky the manner in which completion TLP time-outs are reported. A time-out is reported as specified in this field whenever the corresponding bit in the Switch Time-Out Status (SWTOSTS) register transitions from a zero to a one.
  • Page 153 IDT Configuration Registers Notes Field Default Type Description Field Name Value BCONEN Beacon Enable. This field is used to enable or disable the FRSticky in-band Beacon signaling. 0x0 - (disable) Beacon signaling is disabled 0x1 - (enable) Beacon signaling is enabled...
  • Page 154 IDT Configuration Registers Notes PES5T5 User Manual 9 - 66 January 28, 2011...

  • Page 155: Jtag Boundary Scan

    Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES5T5: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 156: Table 10.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 157: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PE4RN[0] PE4RP[0] PE4TN[0] PE4TP[0] PE5RN[0] PE5RP[0] PE5TN[0] PE5TP[0] PEREFCLKN — PEREFCLKP —...

  • Page 158: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell System Pins APWRDISN CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] — WAKEN EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — Table 10.2 Boundary Scan Chain (Part 2 of 2)
  • Page 159 IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 10.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 10.4. EXTEST To Next Cell...

  • Page 160: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes The output enable cells are also output cells. The simplified logic is shown in Figure 10.5. shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core...

  • Page 161: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 162: Clamp

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x803C This field identifies the silicon as PES5T5. 31:28 Version Version (4 bits) silicon-depen- This field identifies the silicon revision of the PES5T5.

  • Page 163: Usage Considerations

    IDT JTAG Boundary Scan Usage Considerations Notes As previously stated, there are internal pull-ups on JTAG_TRST_N, JTAG_TMS, and JTAG_TDI. However, JTAG_TCK also needs to be driven to a known value. It is best to either drive a zero on the JTAG_TCK pin when it is not being used or to use an external pull-down resistor.
  • Page 164 IDT JTAG Boundary Scan Notes PES5T5 User Manual 10 - 10 January 28, 2011...

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