IDT PowerSpan II Manuals

Manuals and User Guides for IDT PowerSpan II. We have 1 IDT PowerSpan II manual available for free PDF download: Manual

IDT PowerSpan II Manual

IDT PowerSpan II Manual (440 pages)

Brand: IDT | Category: Switch | Size: 1.96 MB

Table of Contents

Table of Contents
3
About this Document
15
Document Conventions
15
Revision History
16
1 Functional Overview

19
- Powerspan II Features
  20
- Figure 1: Powerspan II Block Diagram
  20
- Powerspan II Benefits
  21
- Typical Applications
  22
- Figure 2: Typical Powerspan II Application
  22
- Table 1: Powerspan II Applications
  22
- Powerspan II and Powerspan Differences Summary
  23
- Table 2: Powerspan II Functional Enhancements
  23
- PCI Interface
  24
- Processor Bus Interface
  26
  - Address Decoding
    26
  - Processor Bus Arbitration
    26
- DMA Controller
  26
- I2C / Eeprom
  27
  - Eeprom
    27
  - I2C
    27
- Concurrent Reads
  27
2 PCI Interface

31
3 Processor Bus Interface

83
4 Dma

113
- DMA Register Description
  114
- Direct Mode DMA Operation
  118
  - Initializing a Direct Mode Operation
    118
  - Figure 17: Direct Mode DMA Transfers
    119
- Linked-List Mode DMA Operation
  120
- DMA Interrupts
  124
- DMA Error Handling
  124
  - Table 30: DMA Channel Interrupt Sources and Enables
    124
  - Destination Port Errors
    125
  - PCI Error Bits
    125
  - Processor Bus Error Bit
    125
  - Source Port Errors
    125
  - Command Port Errors
    126
5 I2C/Eeprom

127
- Power-Up Configuration
  128
  - EEPROM Loading
    128
  - Table 31: Power-Up EEPROM Load Sequence
    128
- Bus Master I 2 C Transactions
  135
- PCI Vital Product Data (VPD)
  135
6 Arbitration

137
- PCI Interface Arbitration
  137
- Processor Bus Arbitration
  141
  - Address Bus Arbitration
    142
  - Data Bus Arbitration
    142
  - Address Only Cycles
    143
  - Powerspan II Arbiter and System Boot
    143
  - Table 32: Mx_En Default State
    144
7 Interrupt Handling

145
- Interrupt Sources
  145
  - Interrupts from Normal Operations
    145
  - Interrupts from Transaction Exceptions
    146
- Interrupt Registers
  147
- Interrupt Pins
  153
- DMA Interrupts
  154
  - DMA Interrupt Servicing
    154
- Mailboxes
  154
- Table 39: DMA Channel Interrupt Sources and Enables
  154
- Doorbells
  155
8 Error Handling

157
- PB Interface Errors
  158
- Table 40: PB Interface Errors
  159
- PCI Interface Errors
  162
- Table 41: PCI Interface Errors
  163
- DMA Errors
  166
9 Resets, Clocks and Power-Up Options

167
- Reset
  167
  - Reset Pins
    167
  - Table 42: Powerspan II Reset Pins
    167
  - Table 43: Reset Direction Control Pins
    168
  - Table 44: Powerspan II Reset Response
    168
- Clocks
  170
- Power-Up Options
  171
10 Endian Mapping

177
11 Signals and Pinout

191
- Signal Description
  191
  - Signal Types
    191
  - Table 54: Signal Type Definitions
    191
  - Processor Bus Signals
    192
  - Table 55: Processor Bus Signals
    192
  - Signals
    196
  - Table 56: PCI-1 Signals
    196
  - Signals
    199
  - Table 57: PCI-2 Signals
    199
  - Miscellaneous Signals
    201
  - Table 58: Miscellaneous Signals
    201
  - Test Signals
    203
  - Table 59: Test Signals
    203
- Dual PCI Powerspan II Pinout
  205
  - Dual PCI Powerspan II 480 HSBGA
    205
  - Table 60: Package Characteristics
    205
  - Figure 24: 480 HSBGA
    206
  - 480 HSBGA Pin Information
    207
  - Dual PCI Powerspan II 504 HSBGA
    213
  - Table 61: Package Characteristics
    213
  - Figure 25: 504 HSBGA
    214
  - 504 HSBGA Pin Information
    215
- Single PCI Powerspan II Pin Information
  221
  - Single PCI Powerspan II 420 HSBGA
    221
  - Table 62: Package Characteristics
    221
  - Figure 26: 420 HSBGA
    222
  - 420 HSBGA Pin Information
    223
  - Single PCI Powerspan II 484 HSBGA
    227
  - Table 63: Package Characteristics
    227
  - Figure 27: 484 PBGA
    228
12 Register Descriptions

235
- Register Access
  235
  - Register Map
    235
  - Table 64: Powerspan II Register Map
    235
  - Access from PCI
    244
  - Access from the Processor Bus
    245
  - Access from Multiple Interfaces
    245
- Register Reset
  245
- Configuration and IACK Cycle Generation
  246
  - From PCI-To-PCI
    246
  - From the Processor Bus to PCI
    247
- Bit Ordering and Endian Ordering
  248
- Register Descriptions
  248
- Table 65: Abbreviations Used in Register Descriptions
  248
- Table 66: Read Amount Versus Read Command
  256
- Table 67: Block Size
  271
- Table 68: Setting for MODE and MEM_IO Bits
  272
- Table 69: Read Amount
  273
- Table 70: Arbitration Pin Mapping
  274
- Table 71: PCI-2 AD[31:11] Lines Asserted During Configuration Type 0 Cycles
  277
- Table 72: Parked PCI Master
  285
- Table 73: Block Size
  290
- Table 74: Setting for MODE and MEM_IO Bits
  291
- Table 75: Read Amount
  291
- Table 76: Translation Address Mapping
  293
- Table 77: PCI AD[31:11] Lines Asserted During Configuration Type 0 Cycles
  297
- Table 78: Mx_En Default State
  308
- Table 79: Parked Processor Bus Master
  308
- Table 80: Arbitration Pin Mappings
  320
- Table 81: Mapping Definition
  337
- Table 82: Block Size
  353
- Table 83: Read Amount
  355
- Table 84: Host Outbound Post List Size
  359
- Table 85: I2O FIFO Sizes
  360
13 Electrical and Signal Characteristics

381
14 Package Information

387
- Figure 28: 420 HSBGA
  388
- Dual PCI Powerspan II 480 HSBGA
  389
- Table 92: Package Characteristics
  389
- Figure 29: 480 HSBGA
  390
- Thermal Characteristics
  391
  - Single PCI 420 HSBGA Package
    392
  - Table 93: Thermal Parameters
    392
  - Table 94: 420 HSBGA Package Performance
    392
  - Dual PCI 480 HSBGA Package
    393
  - Table 95: Thermal Parameters
    393
  - Table 96: 480 PBGA Package Performance
    393
15 AC Timing

395
Index

433

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