IDT 89HPES48T12G2 Manuals

Manuals and User Guides for IDT 89HPES48T12G2. We have 1 IDT 89HPES48T12G2 manual available for free PDF download: User Manual

IDT 89HPES48T12G2 User Manual

IDT 89HPES48T12G2 User Manual (276 pages)

PCI Express Switch

Brand: IDT | Category: Switch | Size: 3.54 MB

Table of Contents

About this Manual

3
- Content Summary
  3
- Signal Nomenclature
  4
- Numeric Representations
  4
- Data Units
  4
- Register Terminology
  5
- Use of Hypertext
  6
- Reference Documents
  6
- Revision History
  6
- Table of Contents
  9
PES48T12G2 Device Overview

23
- Introduction
  23
- Features
  23
- Logic Diagram
  27
- System Identification
  28
  - Vendor ID
    28
  - Device ID
    28
  - Revision ID
    28
  - Jtag ID
    28
  - Ssid/Ssvid
    28
  - Device Serial Number Enhanced Capability
    28
  - Table 1.3 PES48T12G2 Revision ID
    28
- Pin Description
  29
- Table 1.4 PCI Express Interface Pins
  29
- Table 1.5 Reference Clock Pins
  30
- Table 1.6 Smbus Interface Pins
  30
- Table 1.7 General Purpose I/O Pins
  31
- Table 1.8 System Pins
  31
- Table 1.9 Test Pins
  33
- Table 1.10 Power, Ground, and Serdes Resistor Pins
  34
- Pin Characteristics
  35
- Table 1.11 Pin Characteristics
  35
Architectural Overview

39
- Introduction
  39
- Logical View
  40
Switch Core

41
- Introduction
  41
- Switch Core Architecture
  41
  - Ingress Buffer
    41
  - Table 3.1 IFB Buffer Sizes
    41
  - Egress Buffer
    42
  - Table 3.2 EFB Buffer Sizes
    42
  - Crossbar Interconnect
    43
  - Datapaths
    43
- Packet Ordering
  43
- Table 3.3 Replay Buffer Storage Limit
  43
- Arbitration
  44
  - Table 3.4 Packet Ordering Rules in the PES48T12G2
    44
  - Port Arbitration
    45
- Cut-Through Routing
  45
- Table 3.5 Conditions for Cut-Through Transfers
  46
- Request Metering
  47
- Internal Errors
  52
Notes

55
Clocking

55
Reset and Initialization

57
- Introduction
  57
- Boot Configuration Vector
  57
- Table 5.1 PES48T12G2 Reset Precedence
  57
- Switch Fundamental Reset
  58
- Table 5.2 Boot Configuration Vector Signals
  58
- Hot Resets
  61
  - Hot Reset
    61
  - Upstream Secondary Bus Reset
    61
  - Downstream Secondary Bus Reset
    62
- Port Merging
  62
Link Operation

65
- Introduction
  65
- Polarity Inversion
  65
- Lane Reversal
  65
- Link Width Negotiation
  69
  - Link Width Negotiation in the Presence of Bad Lanes
    70
- Dynamic Link Width Reconfiguration
  70
- Link Speed Negotiation
  70
  - Link Speed Negotiation in the PES48T12G2
    71
  - Software Management of Link Speed
    73
- Link Retraining
  74
- Link down
  74
- Slot Power Limit Support
  75
  - Upstream Port
    75
  - Downstream Port
    75
- Link States
  75
- Active State Power Management
  76
  - L0S ASPM
    76
  - L1 Aspm
    77
- L1 ASPM Entry Rejection Timer
  78
- Link Status
  78
- De-Emphasis Negotiation
  79
- Crosslink
  79
- Gen1 Compatibility Mode
  80
- Table 6.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
  81
Serdes

83
Theory of Operation

99
Hot-Plug and Hot-Swap

119
- Introduction
  119
- Hot-Plug Signals
  121
- Table 9.1 Port Hot Plug Signals
  121
- Table 9.2 Negated Value of Unused Hot-Plug Output Signals
  121
- Port Reset Outputs
  122
  - Power Enable Controlled Reset Output
    123
  - Power Good Controlled Reset Output
    123
- Hot-Plug Events
  124
- Legacy System Hot-Plug Support
  124
- Hot-Swap
  126
Power Management

127
General Purpose I/O

131
- Introduction
  131
- GPIO Configuration
  131
Smbus Interfaces

133
Multicast

153
- Introduction
  153
- Addressing and Routing
  153
Register Organization

159
- Introduction
  159
- Address Maps
  160
PCI to PCI Bridge and Proprietary Port Specific Registers

175
Switch Configuration and Status Registers

245
- Switch Control and Status Registers
  245
- Internal Switch Timer
  247
- Switch Port Registers
  247
- Serdes Control and Status Registers
  248
- General Purpose I/O Registers
  256
- Hot-Plug and Smbus Interface Registers
  259
JTAG Boundary Scan

267
- Introduction
  267
- Test Access Point
  267
- Signal Definitions
  267
- Figure 17.1 Diagram of the JTAG Logic
  267
- Boundary Scan Chain
  268
- Table 17.1 JTAG Pin Descriptions
  268
- Figure 17.2 State Diagram of the TAP Controller
  268
- Table 17.2 Boundary Scan Chain
  269
- Test Data Register (DR)
  271
- Instruction Register (IR)
  273
  - Figure 17.5 Diagram of Bidirectional Cell
    273
  - Bypass
    274
  - Extest
    274
  - Sample/Preload
    274
  - Table 17.3 Instructions Supported by the JTAG Boundary Scan
    274
  - Clamp
    275
  - Extest_Train
    275
  - Figure 17.6 Device ID Register Format
    275
  - Idcode
    275
  - Table 17.4 System Controller Device Identification Register
    275
  - Validate
    275
  - Extest_Pulse
    276
  - Reserved
    276
  - Usage Considerations
    276

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