IDT 89HPES64H16G2 User Manual page 123

IDT SerDes
Notes
PES64H16G2 User Manual
Transmit Levels
De-
De-
Drive empha-
empha-
Level sized
sis
Level
272 -6.0
225 -6.1
177 -6.2
130 -6.3
Table 8.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis (Part 2 of 2)
When the PHY operates in low-swing mode, de-emphasis is automatically turned off. Therefore, the fine
and coarse de-emphasis controls in the S[x]TXLCTL0 and S[x]TXLCTL1 registers have no effect. In this
mode, the TDVL_LSG1 and TDVL_LSG2 fields in the S[x]TXLCTL1 register control the transmitter voltage
swing for Gen1 and Gen2 modes respectively. Please refer to section Low-Swing Transmitter Voltage Mode
on page 8-13 for further details.
In addition to the SerDes settings described above, the user may apply an amplitude boost to the drive
swing by setting the TX_AMPBOOST field in the S[x]TXLCTL0 register. Amplitude boost may be applied on
a per-lane basis. Amplitude boost may be applied to increase the drive swings above the values shown in
Tables 8.2, 8.3, and 8.4. Refer to the description of the TX_AMPBOOST field for further details.
Programmable De-emphasis Adjustment
The tables shown in the previous section list different settings to control the SerDes drive swing while
keeping the de-emphasis within the allowable range, depending on the PHY operating mode (e.g., Gen1
data rate, Gen2 data rate and -3.5 dB de-emphasis, or Gen2 data rate with -6.0 dB de-emphasis).
It is possible to modify the de-emphasis in fine or coarse increments on a per-lane basis, using the
appropriate fields in the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Table 8.1 shows the register fields that
control fine and coarse de-emphasis for each PHY operating mode.
When using the de-emphasis controls, it is important to understand that the actual deemphasis applied
on the link is a function of the de-emphasis controls, the transmitter equalization control, the transmit drive
swing controls, and the data rate of the SerDes.
The coarse de-emphasis controls should generally be set as shown in Tables 8.2, 8.3, and 8.4. Note that
there are separate coarse de-emphasis and transmit equalization controls per PHY operating mode. The
settings shown in the above tables ensure that the de-emphasis falls within the nominal range mandated by
the PCI Express Specification. The coarse de-emphasis settings shown in the above tables ensure that the
de-emphasis falls within the nominal range mandated by the PCI Express specification 2.0. As shown in the
tables, the coarse de-emphasis setting is dependent on the transmit drive swing setting. Therefore, modi-
fying the transmit drive swing must be done in conjunction with modifying the coarse de-emphasis setting.
The fine de-emphasis registers allow modification of the de-emphasis in fine steps. There is a fine de-
emphasis control per PHY operating mode.
When the PHY operates in Gen1 data rate with -3.5 dB de-emphasis, the fine de-emphasis control
(FDC_FS3DBG1 field in the S[x]TXLCTL1 register) has the effect shown in Figure 8.1. In the figure,
TXLEV[4:0] refers to the TDVL_FS3DBG1 field in the S[x]TXLCTL1 register.
When the PHY operates in Gen2 data rate with -3.5 dB de-emphasis, the fine de-emphasis control
(FDC_FS3DBG2 field in the S[x]TXLCTL1 register) has the effect shown in Figure 8.2. In the figure,
TXLEV[4:0] refers to the TDVL_FS3DBG2 field in the S[x]TXLCTL1 register.
Settings of Relevant Fields in the
S[x]TXLCTL0 & S[x]TXLCTL1 registers
TDVL_ TX_EQ_
FS6DBG2 6DBG2
138 0x03 0x1
113 0x02 0x1
88 0x01 0x1
63 0x00 0x1
8 - 9
CDC_ FDC_ TX_SLEW
FS6DBG2 FS6DBG2
0x1 0x3
0x1 0x3
0x1 0x3
0x1 0x3
April 5, 2013
_G2
0x0
0x0
0x0
0x0