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IDT 89HPES48T12G2 User Manual

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IDT
89HPES48T12G2
®
PCI Express
Switch
User Manual
April 2013
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2013 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89HPES48T12G2

  • Page 1 ® ® 89HPES48T12G2 ® PCI Express Switch User Manual April 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.

  • Page 4: Signal Nomenclature

    Notes Chapter 17, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic TAP controller, signal definitions, a test data register, an instruction register, and usage considerations. Signal Nomenclature To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms assertion and negation are used.

  • Page 5: Register Terminology

    Notes In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double- words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always the most significant bit and bit 0 is the least significant bit.

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read Only Software can only read registers/bits with this attribute. Contents are hardwired to a constant value or are status bits that may be set and cleared by hardware. Writing to a RO location has no effect.
  • Page 7 Notes February 9, 2009: In Chapter 1: Table 1.4, for Port 0 Serial Data Receive/Transmit signals, deleted statement that port 0 is the upstream port; Table 1.8, revised Description for SWMODE[3:0]; Table 1.10, added “3.3V is preferred” for signal V I/O.
  • Page 8 Notes December 14, 2009: Deleted all references to support for Weighted Round Robin arbitration. January 21, 2010: Removed Preliminary from title. February 10, 2010: In Chapter 5, added new Port Merging section. In Table 1.8, added reference to Port Merging section in PxxMERGEN pin description. March 31, 2010: In Chapter 14, Table 14.6, added the following register names and cross-references for ports 8, 9, 12, 13: SWPORTxCTL, SWPORTxSTS, SxCTL, SxTXLCTL0, SxTXLCTL1, SxRXEQLCTL.

  • Page 9: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................2 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 10 IDT Table of Contents Notes Clocking Introduction ............................. 4-1 Port Clocking Mode ........................4-1 Reset and Initialization Introduction ............................. 5-1 Boot Configuration Vector....................... 5-1 Switch Fundamental Reset......................5-2 Hot Resets ............................5-5 Hot Reset..........................5-5 Upstream Secondary Bus Reset .................... 5-5 Downstream Secondary Bus Reset..................
  • Page 11 IDT Table of Contents Notes SerDes Transmitter Control Registers..................7-4 Transmit Margining using the PCI Express Link Control 2 Register..........7-12 Low-Swing Transmitter Voltage Mode..................7-13 Receiver Equalization Controls..................... 7-14 SerDes Power Management......................7-15 Theory of Operation Introduction ............................. 8-1 Transaction Routing........................
  • Page 12 Address Maps..........................14-2 PCI-to-PCI Bridge Registers....................14-2 Capability Structures ......................14-3 IDT Proprietary Port Specific Registers................14-10 Switch Configuration and Status Registers ................ 14-12 PCI to PCI Bridge and Proprietary Port Specific Registers Type 1 Configuration Header Registers ..................15-1 PCI Express Capability Structure ....................
  • Page 13 IDT Table of Contents Notes JTAG Boundary Scan Introduction ........................... 17-1 Test Access Point ......................... 17-1 Signal Definitions .......................... 17-1 Boundary Scan Chain........................17-2 Test Data Register (DR) ....................... 17-5 Boundary Scan Registers..................... 17-5 Instruction Register (IR)........................ 17-7 EXTEST..........................17-8 SAMPLE/PRELOAD......................
  • Page 14 IDT Table of Contents Notes PES48T12G2 User Manual April 5, 2013...
  • Page 15 List of Tables ® Table 1.1 Initial Configuration Register Settings for PES48T12G2 ............. 1-3 Notes Table 1.2 PES48T12G2 Device IDs ....................1-6 Table 1.3 PES48T12G2 Revision ID ....................1-6 Table 1.4 PCI Express Interface Pins....................1-7 Table 1.5 Reference Clock Pins ......................1-8 Table 1.6 SMBus Interface Pins ......................
  • Page 16 IDT List of Tables Notes Table 11.3 GPIO Alternate Function Pins ................... 11-2 Table 12.1 PES48T12G2 Compatible Serial EEPROMs..............12-2 Table 12.2 Serial EEPROM Initialization Errors .................. 12-5 Table 12.3 I/O Expander Function Allocation ..................12-6 Table 12.4 I/O Expander Default Output Signal Value ................ 12-7 Table 12.5...
  • Page 17 List of Figures ® Figure 1.1 PES48T12G2 Block Diagram ....................1-3 Notes Figure 1.2 PES48T12G2 Logic Diagram .....................1-5 Figure 2.1 Transparent PCIe Switch ....................2-2 Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers ..........3-3 Figure 3.2 Architectural Model of Arbitration ..................3-5 Figure 3.3 PCIe Switch Static Rate Mismatch ..................3-8 Figure 3.4...
  • Page 18 IDT List of Figures Notes Figure 12.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled .........................12-18 Figure 12.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ..12-18 Figure 12.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ..12-19 Figure 12.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ..12-19...
  • Page 19 Register List ® ACSCAP - ACS Capability Register (0x324)..................15-49 Notes ACSCTL - ACS Control Register (0x326)..................... 15-50 ACSECAPH - ACS Extended Capability Header (0x320) ..............15-49 ACSECV - ACS Egress Control Vector (0x328)................... 15-51 AERCAP - AER Capabilities (0x100) ....................15-32 AERCEM - AER Correctable Error Mask (0x114) ................
  • Page 20 IDT Register List Notes IOBASE - I/O Base Register (0x01C)......................15-5 IOBASEU - I/O Base Upper Register (0x030)..................15-8 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x0AD8)..............16-20 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) ..............16-20 IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) ..............16-21 IOEXPADDR3 - SMBus I/O Expander Address 3 (0x0AE4) ..............16-21...
  • Page 21 IDT Register List Notes PHYLSTATE0 - Phy Link State 0 (0x540).....................15-67 PHYPRBS - Phy PRBS Seed (0x55C)....................15-68 PLTIMER - Primary Latency Timer (0x00D)....................15-4 PMBASE - Prefetchable Memory Base Register (0x024) ...............15-7 PMBASEU - Prefetchable Memory Base Upper Register (0x028)............15-8 PMCAP - PCI Power Management Capabilities (0x0C0)..............15-27 PMCSR - PCI Power Management Control and Status (0x0C4) ............15-28...
  • Page 22 IDT Register List Notes PES48T12G2 User Manual April 5, 2013...

  • Page 23: Pes48T12G2 Device Overview

    It provides 48 GBps (384 Gbps) of aggregated, full-duplex switching capacity through 48 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0.
  • Page 24 • Round robin • Weighted Round Robin (WRR) – Request metering • IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput – High performance switch core architecture • Combined Input Output Queued (CIOQ) switch architecture with large buffers ...
  • Page 25 IDT PES48T12G2 Device Overview Notes – SECDED ECC protection on all internal RAMs – End-to-end data path parity protection – Checksum Serial EEPROM content protected – Autonomous link reliability (preserves system operation in the presence of faulty links) – Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug ...
  • Page 26 IDT PES48T12G2 Device Overview Notes PCIELCAP Port MAXLNKWDTH Table 1.1 Initial Configuration Register Settings for PES48T12G2 (Part 2 of 2) Note: There are no ports 10 and 11 in the PES48T12G2 device. PES48T12G2 User Manual 1 - 4 April 5, 2013...

  • Page 27: Logic Diagram

    IDT PES48T12G2 Device Overview Logic Diagram GCLKN[1:0] Global GCLKP[1:0] Reference Clocks GCLKFSEL PCI Express Switch PE00RP[3:0] SerDes Input PE00RN[3:0] Port 0 PCI Express PCI Express Switch PE00TP[3:0] Switch SerDes Output PE00TN3:[0] PE01RP[3:0] SerDes Input Port 0 PE01RN[3:0] Port 1 PCI Express...

  • Page 28: System Identification

    IDT PES48T12G2 Device Overview System Identification Notes Vendor ID All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES48T12G2 device ID is shown in Table 1.2. PCIe Device...

  • Page 29: Pin Description

    IDT PES48T12G2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES48T12G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 30: Table 1.5 Reference Clock Pins

    IDT PES48T12G2 Device Overview Notes Signal Type Name/Description PE07TP[3:0] PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- PE07TN[3:0] mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7.

  • Page 31: Table 1.7 General Purpose I/O Pins

    IDT PES48T12G2 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] General Purpose I/O.
  • Page 32 IDT PES48T12G2 Device Overview Notes Signal Type Name/Description P23MERGEN Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 2 is merged with port 3 to form a single x8 port.

  • Page 33: Table 1.9 Test Pins

    IDT PES48T12G2 Device Overview Notes Signal Type Name/Description PERSTN Global Reset. Assertion of this signal resets all logic inside PES48T12G2. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES48T12G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 34: Table 1.10 Power, Ground, And Serdes Resistor Pins

    IDT PES48T12G2 Device Overview Notes Signal Type Name/Description REFRES[13,12,9:0] External Reference Resistors. Provides a reference for the SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from these pins to ground. REFRESPLL PLL External Reference Resistor. Provides a reference for the PLL bias currents and PLL calibration circuitry.

  • Page 35: Pin Characteristics

    IDT PES48T12G2 Device Overview Pin Characteristics Notes Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation.
  • Page 36 IDT PES48T12G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor PCI Express PE08TP[3:0] PCIe Serial Link Interface (Cont.) Differential PE09RN[3:0] PE09RP[3:0] PE09TN[3:0] PE09TP[3:0] PE12RN[3:0] PE12RP[3:0] PE12TN[3:0] PE12TP[3:0] PE13RN[3:0] PE13RP[3:0] PE13TN[3:0] PE13TP[3:0] GCLKN[1:0] HCSL Diff. Clock Refer to Table 9...
  • Page 37 IDT PES48T12G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor SerDes Refer- REFRES00 Analog ence Resistors REFRES01 REFRES02 REFRES03 REFRES04 REFRES05 REFRES06 REFRES07 REFRES08 REFRES09 REFRES12 REFRES13 REFRESPLL Table 1.11 Pin Characteristics (Part 3 of 3) Internal resistor values under typical operating conditions are 92K ...
  • Page 38 IDT PES48T12G2 Device Overview Notes PES48T12G2 User Manual 1 - 16 April 5, 2013...

  • Page 39: Architectural Overview

    Chapter 2 Architectural Overview ® Introduction Notes This section provides a high level architectural overview of the PES48T12G2. An architectural block diagram of the PES48T12G2 is shown in . PCI Express Port s PCI Express Port s SerDes SerDes SerDes SerDes SerDes SerDes...

  • Page 40: Logical View

    IDT Architectural Overview Logical View Notes The logical view of a PCIe switch is shown in Figure 2.1. A PCI switch contains one upstream port and one or more downstream ports. Each port is associated with a PCI-to-PCI bridge. All PCI-to-PCI bridges associated with a PCIe switch are interconnected by a virtual PCI bus.

  • Page 41: Switch Core

    Chapter 3 Switch Core ® Introduction Notes This chapter provides an overview of the PES48T12G2’s Switch Core. As shown in Figure 2.1 in the Architectural Overview chapter, the Switch Core interconnects switch ports. The Switch Core’s main func- tion is to transfer TLPs among these ports efficiently and reliably. In order to do so, the Switch Core provides buffering, ordering, arbitration, and error detection services.

  • Page 42: Egress Buffer

    IDT Switch Core Notes Total Size and Advertised Advertised Port Limitations Data Header Mode Queue (per-port) Credits Credits Posted 12352 Bytes and up to 127 Merged TLPs Non Posted 2048 Bytes and up to 127 TLPs Completion 12352 Bytes and up to 127 TLPs Table 3.1 IFB Buffer Sizes (Part 2 of 2)

  • Page 43: Crossbar Interconnect

    IDT Switch Core Notes Port Replay Buffer Storage Mode Limit 32 TLPs Bifurcated 64 TLPs Merged Table 3.3 Replay Buffer Storage Limit Crossbar Interconnect The crossbar is an 12x12 matrix of pathways, capable of concurrently transferring data between a maximum of 12 port pairs. The crossbar interconnects the port ingress buffers to the egress buffers. It provides two data-interfaces per port, one for the port’s ingress buffers and one for the port’s egress...

  • Page 44: Arbitration

    IDT Switch Core Notes Applying ordering rules at the output of the ingress buffer (i.e., before the crossbar) is done to ensure that packets are ordered regardless of their destination port. This guarantees that the producer/consumer model is met when the data transfer involves any number of peers.

  • Page 45: Port Arbitration

    IDT Switch Core Notes Port 0 IFB VC 0 Port 0 Egress Arbitration VC 0 Arbitration Port VC 0 Port 1 IFB (not Arbitration applicable) VC 0 Port 13 Egress Arbitration VC 0 Arbitration Port VC 0 (not Arbitration applicable)

  • Page 46: Table 3.5 Conditions For Cut-Through Transfers

    IDT Switch Core Notes The ingress and egress link bandwidth is determined by the negotiated speed and width of the links. Table 3.5 shows the conditions under which cut-through and adaptive-cut-through occur. When the condi- tions are met, cut-through is performed across the IFB, crossbar , and EFB.

  • Page 47: Request Metering

    IDT Switch Core Notes Ingress Ingress Egress Egress Conditions for Cut- Link Link Link Link Through Speed Width Speed Width 5.0 Gbps x8, x4, x2, x1 Always x8, x4, x2, x1 Always x8, x4, x2, x1 Always At least 50% of packet is in IFB...
  • Page 48 IDT Switch Core Notes If read requests are injected sporadically or at a low rate, then buffering within the switch may be used to accommodate short lived contention and allow completions to endpoints to proceed without interfering. If read requests are injected at a high rate, then no amount of buffering in the switch will prevent completions from interfering.

  • Page 49: Operation

    IDT Switch Core Notes The request metering implementation in the PES48T12G2 makes a number of simplifying assumptions that may or may not be true in all systems. Therefore, it should be expected that some amount of parameter tuning may be required to achieve optimum performance.

  • Page 50: Table 3.6 Request Metering Decrement Value

    IDT Switch Core Notes The Decrement Value Adjustment (DVADJ) field represents a sign-magnitude fixed point 0:4:11 number (i.e., a positive fixed-point number with 4 integer bits and 11 fractional bits). – DVADJ field provides fine grain programmable adjustment of the value by which the counter is decremented.

  • Page 51: Completion Size Estimation

    IDT Switch Core Notes tmp = RequestMeteringCounter RequestMeteringCounter (DecrementValue[LinkSpeed,LinkWidth] RMCTL.DVADJ) if (tmp < RequestMeteringCounter) { RequestMeteringCounter = 0 Figure 3.7 Request Metering Counter Decrement Operation Completion Size Estimation This section describes the value that is loaded into the request metering counter when a request is transferred into the switch core.

  • Page 52: Internal Errors

    PCI Express interface itself or on behalf of trans- actions initiated on PCI Express. The PES48T12G2 classifies the following IDT proprietary switch errors as internal errors. – Switch core time-outs –...

  • Page 53: Memory Secded Ecc Protection

    IDT Switch Core Switch Time-Outs Notes The switch core discards any TLP that reaches the head of an IFB or EFB queue and is more than 64 seconds old. This includes posted, non-posted, completion and inserted TLPs. If during processing of a TLP with broadcast routing a switch core time-out occurs, then the switch core will abort processing of the TLP.
  • Page 54 IDT Switch Core Notes an LCRC is computed. If the TLP is parity error free, then the LCRC and TLP contents are known to be correct and the LCRC is used to protect the packet through the lower portion of the DL layer, PHY layer, and link transmission.

  • Page 55: Notes

    Chapter 4 Clocking ® Introduction Notes Figure 4.1 provides a logical representation of the PES48T12G2 clocking architecture. The PES48T12G2 has a single differential global reference clock input (GCLK). Port 0 Port 1 Port 13 Port 9 Port 12 SerDes SerDes SerDes SerDes SerDes...

  • Page 56: Table 4.1 Initial Port Clocking Mode And Slot Clock Configuration State

    IDT Clocking Notes The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot configuration vector as shown in Table 4.1. This field determines the initial value of the Slot Clock Configu- ration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register.

  • Page 57: Reset And Initialization

    Chapter 5 Reset and Initialization ® Introduction Notes This chapter describes the PES48T12G2 reset and initialization. When multiple resets are initiated concurrently, the precedence shown in Table 6.1 is used to determine which one is acted upon. – Reset types and causes are described in detail in the following sections. •...

  • Page 58: Switch Fundamental Reset

    IDT Reset and Initialization Notes As noted in Table 5.2, some of the initial values specified by the boot configuration vector may be over- ridden by software, serial EEPROM, or an external SMBus device. The state of all of the boot configuration signals in Table 5.2 sampled during a switch fundamental reset may be determined from the Boot Configu-...
  • Page 59 IDT Reset and Initialization Notes A switch fundamental reset may be initiated by any of the following conditions. – A cold switch fundamental reset initiated by application of power (i.e., a power-on) followed by assertion of the global reset (PERSTN) signal.
  • Page 60 IDT Reset and Initialization Notes second after Conventional Reset of a device. The reset sequence above guarantees that the switch will be ready to respond successfully to configuration requests within the 1.0 second period as long as the serial EEPROM initialization process completes within 200 ms.

  • Page 61: Hot Resets

    IDT Reset and Initialization Hot Resets Notes Hot resets may be subdivided into three subcategories: switch hot reset, upstream secondary bus reset, and downstream secondary bus reset. These subcategories correspond to resets defined by the PCI Express architecture. – A fundamental reset logically causes all logic associated with the switch to take on its initial state.

  • Page 62: Downstream Secondary Bus Reset

    IDT Reset and Initialization Notes 3. All TLPs received from downstream ports and queued in the switch are discarded. 4. Logic in the stack and switch core associated with the downstream ports are gracefully reset. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge Control Register (BCTL).
  • Page 63 IDT Reset and Initialization Notes • The state of the following hot-plug input signals is ignored: PxAPN, PxMRLN, PxPDN, PxPFN, and PxPWRGDN. – The port is not associated with a PCI Express link. PCI Express configuration requests targeting the port are not possible and the port is not part of the PCI Express hierarchy.
  • Page 64 IDT Reset and Initialization Notes PES48T12G2 User Manual 5 - 8 April 5, 2013...

  • Page 65: Link Operation

    Chapter 6 Link Operation ® Introduction Notes Link operation in the PES48T12G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 GT/s and 5.0 GT/s. The PES48T12G2 contains sixteen x4 ports which may be merged in pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port.
  • Page 66 IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES48T12G2 PES48T12G2 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal...
  • Page 67 IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES48T12G2 PES48T12G2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal...
  • Page 68 IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES48T12G2 PES48T12G2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal...

  • Page 69: Link Width Negotiation

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES48T12G2 PES48T12G2 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5]...

  • Page 70: Link Width Negotiation In The Presence Of Bad Lanes

    IDT Link Operation Notes The actual link width is determined dynamically during link training. Ports limited to a maximum link width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The current negotiated width of a link may be determined from the Negotiated Link Width (NLW) field in the corresponding port’s PCI Express...

  • Page 71: Link Speed Negotiation In The Pes48T12G2

    IDT Link Operation Notes A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2 training sets transmitted to its link partner during link training. The PCIe spec permits a component to change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds without necessarily changing the link speed, via the Recovery LTSSM state.
  • Page 72 IDT Link Operation Notes The current link speed of each port is reported via the Current Link Speed (CLS) field of the port’s Link Status Register (PCIELSTS). The above behavior applies after full link retrain (i.e., when the LTSSM transi- tions through the ‘Detect’...

  • Page 73: Software Management Of Link Speed

    IDT Link Operation Notes – When software sets the Link Retrain (LRET) bit in the PCIELCTL register and the PES48T12G2 port has recorded support for the higher speed by its link partner. When operating at 5.0 GT/s, a PES48T12G2 port initiates a link speed downgrade in the following cases: –...

  • Page 74: Link Retraining

    IDT Link Operation Notes Notification of link speed changes if provided through the link bandwidth notification mechanism described in the PCIe specification. This mechanism is enabled by setting the Link Bandwidth Management Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports. For downstream...

  • Page 75: Slot Power Limit Support

    IDT Link Operation Notes – The port handles all TLPs that target the port’s function(s) normally. • It is possible to perform configuration read and write operations to port. When a link comes up, flow control credits for the configured size of the port’s IFB queues are adver- tised.

  • Page 76: Active State Power Management

    IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 6.6 PES48T12G2 ASPM Link Sate Transitions Active State Power Management The operation of link Active State Power Management (ASPM) is orthogonal to device power manage- ment. Once ASPM is enabled, ASPM link state transitions are initiated by hardware without software involvement.

  • Page 77: L1 Aspm

    IDT Link Operation Notes L0s Exit Conditions The transmit side L0s exit conditions depend on the port’s operational state. A port configured in ‘Upstream Switch Port’ mode initiates exit from L0s when any of the conditions listed below are met: –...

  • Page 78: L1 Aspm Entry Rejection Timer

    IDT Link Operation L1 ASPM Entry Rejection Timer Notes When enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, PES48T12G2 downstream ports respond to link partner requests to enter the L1 ASPM state. In order to enter the L1 ASPM link state, a downstream device (i.e., endpoint) sends continuous PM_Active_State_Request_L1...

  • Page 79: De-Emphasis Negotiation

    IDT Link Operation De-emphasis Negotiation Notes The PCI Express 2.0 specification requires that components support the following levels of de- emphasis, depending on the link data rate: – 2.5 GT/s (Gen1): De-emphasis = -3.5dB – 5.0 GT/s (Gen2): De-emphasis = -3.5dB or -6.0dB When operating at 5.0 GT/s, the de-emphasis is selected by programming the Selectable De-emphasis...

  • Page 80: Hot Reset Operation On A Crosslink

    IDT Link Operation Notes Note that when a PES48T12G2 upstream port is crosslinked to a link-partner’s upstream port, neither port may automatically initiate a link speed change to Gen 2, thereby resulting in a Gen 1 link. It is possible to overcome this by setting the ILSCC bit in the PES48T12G2 upstream port’s PHYLCFG0 register.

  • Page 81: Table 6.2 Gen1 Compatibility Mode: Bits Cleared In Training Sets

    IDT Link Operation Notes A PES48T12G2 port is placed in Gen1 Compatibility Mode by setting the Gen1 Compatibility Mode Enable (G1CME) bit in the PHYLCFG0 register and fully retraining the link (i.e., via the FLRET bit the PHYLSTATE0 register). When a PES48T12G2 port operates in Gen1 Compatibility Mode, the PHY does not set the following bits in Table 6.2 in the training sets that it transmits...
  • Page 82 IDT Link Operation Notes PES48T12G2 User Manual 6 - 18 April 5, 2013...

  • Page 83: Serdes

    Chapter 7 SerDes ® Introduction Notes This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with each PES48T12G2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI Express lanes (i.e., a SerDes “quad”), plus a central block that controls the quad as a whole. This central block is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each lane, initialization of the quad, etc.

  • Page 84: De-Emphasis

    IDT SerDes Notes In addition to this, the PES48T12G2 offers proprietary fine grain controllability of the SerDes transmitter voltage level, across a wide range of settings. The PES48T12G2 places no restrictions on the time at which these settings can be modified (e.g., they can be modified during normal operation of the link or while the link is being tested).

  • Page 85: Receiver Equalization

    Programming of SerDes Controls The SerDes controls described above may be programmed by accessing IDT proprietary registers within the PES48T12G2 switch. The registers may be programmed via any of the mechanisms allowed by the PES48T12G2 (i.e., via PCI Express configuration accesses from a root, via EEPROM loading at boot- time, or via the PES48T12G2’s SMBus slave interface).

  • Page 86: Serdes Transmitter Control Registers

    IDT SerDes Notes When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to ‘Normal Operating Range’, the transmitter voltage level for each SerDes lane of the port is controlled via the S[x]TXLCTL0 and S[x]TXLCTL1 registers. Otherwise, the TM field controls the SerDes voltage directly for all SerDes lanes of the port.

  • Page 87: Table 7.1 Serdes Transmit Level Controls In The S[X]Txlctl0 And S[X]Txlctl1 Registers

    IDT SerDes Notes Relevant fields in Relevant fields in PHY Operation Mode S[x]TXLCTL0 S[x]TXLCTL1 Coarse De- emphasis Slew Rate Voltage Data Drive Level / Fine-De- Control & Control Swing Rate emphasis emphasis Control Transmitter (Course & Fine) Equalization Full-Swing 2.5 GT/s -3.5 dB...

  • Page 88: Table 7.2 Serdes Transmit Driver Settings In Gen1 Mode

    IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS3DBG1 3DBG1 FS3DBG1 FS3DBG1 Level -3.6 0x1C -3.6 0x1B -3.6 0x1A -3.6 0x19 -3.6 0x18 -3.5...

  • Page 89: Table 7.3 Serdes Transmit Driver Settings In Gen2 Mode With -3.5Db De-Emphasis

    IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive emphas TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW emphas Level ized FS3DBG2 3DBG2 FS3DBG2 FS3DBG2 Level -3.5 0x1C -3.5 0x1B -3.5 0x1A -3.6 0x19 -3.6 0x18 -3.6...

  • Page 90: Table 7.4 Serdes Transmit Driver Settings In Gen2 Mode With -6.0Db De-Emphasis

    IDT SerDes Notes Table 7.4 shows a number of possible settings for the drive, de-emphasis, and slew rate controls in Gen2 mode with -6.0dB de-emphasis . The default setting is highlighted. As mentioned above, the PCI Express 2.0 spec allows an error of up to +/- 0.5dB on the de-emphasis. All settings listed in the table ensure that the de-emphasis is kept within the allowable range.
  • Page 91 IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS6DBG2 6DBG2 FS6DBG2 FS6DBG2 Level -6.0 0x03 -6.1 0x02 -6.2 0x01 -6.3 0x00 Table 7.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis (Part 2 of 2) When the PHY operates in low-swing mode, de-emphasis is automatically turned off.
  • Page 92 IDT SerDes Notes When the PHY operates in Gen2 data rate with -6.0 dB de-emphasis, the fine de-emphasis control (FDC_FS6DBG2 field in the S[x]TXLCTL1 register) has the effect shown in Figure 7.3. In the figure, TXLEV[4:0] refers to the TDVL_FS6DBG2 field in the S[x]TXLCTL1 register.

  • Page 93: Table 7.5 Transmitter Slew Rate Settings

    IDT SerDes Notes Figure 7.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB Nominal de-emphasis Finally, note that it is possible to turn off de-emphasis (i.e., 0 dB de-emphasis) for a given PHY operating mode by setting the corresponding transmitter equalization control to 0x0, the coarse de-emphasis control to a value of 0x3, and the fine de-emphasis control to a value of 0x7.

  • Page 94: Table 7.6 Pci Express Transmit Margining Levels Supported By The Pes48T12G2

    IDT SerDes Notes Table 7.5 Transmitter Slew Rate Settings (Part 2 of 2) Transmit Margining using the PCI Express Link Control 2 Register When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to a value other than ‘Normal Operating Range’, the transmitter voltage levels are controlled by hardware based on the setting of...

  • Page 95: Low-Swing Transmitter Voltage Mode

    IDT SerDes Notes Finally, when the TM field is modified, the newly selected value is not applied until the PHY LTSSM tran- sitions through the states in which it is allowed to modify the transmit margin setting on the line (e.g., Recovery.RcvrLock).

  • Page 96: Receiver Equalization Controls

    IDT SerDes Notes Drive Level TDVL_LSG2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Table 7.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following occurs: –...

  • Page 97: Serdes Power Management

    IDT SerDes SerDes Power Management Notes In order to maximize power savings in the SerDes, the PES48T122G2 adheres to the following guide- lines. For SerDes quads that are used, their power state depends on the state of the port(s) associated with the SerDes, as described below.
  • Page 98 IDT SerDes Notes PES48T12G2 User Manual 7 - 16 April 5, 2013...

  • Page 99: Theory Of Operation

    Chapter 8 Theory of Operation ® Introduction Notes This chapter describes the PES48T12G2-specific architectural behavior of the PCI Express switch. Transaction Routing The switch supports routing of all transaction types defined in PCI Express Base Specification Revision 2.0. This includes routing of specification defined transactions as well as those that may be used in vendor defined messages and in future revisions of the PCI Express specification.

  • Page 100: Downstream Port Interrupts

    IDT Theory of Operation Notes EN bit in INTXD bit Unmasked MSICAP in PCICMD Action Interrupt Register Register Asserted MSI message generated Assert_INTA message request generated to switch core None Negated None Deassert_INTA message request generated to switch core None Table 8.2 Downstream Port Interrupts...

  • Page 101: Access Control Services

    When a ACS causes a TLP to be re-directed, the re-direction is implemented such that TLPs received by a port that are ACS re-directed follow the ordering rules (for more information, contact ssdhelp@idt.com). Specifically, non-relaxed-ordered completion TLPs that are re-directed towards the root- complex can’t pass previously received posted TLPs re-directed in the same direction.
  • Page 102 IDT Theory of Operation Notes Upstream Port TLP route Completion with Bridge completer-abort status Virtual PCI Bus ACS Source Validation (TLP is dropped at this point) Bridge Bridge Downstream Ports Figure 8.1 ACS Source Validation Example Figure 8.2 shows an example of ACS peer-to-peer request re-direct at a downstream port. In this case, the offending TLP received by the downstream port is re-directed towards the root-complex.

  • Page 103: Table 8.4 Prioritization Of Acs Checks For Request Tlps

    IDT Theory of Operation Notes Upstream Port Intended TLP Route ACS Re-directed Route Bridge Virtual PCI Bus ACS Upstream Forwarding Bridge Bridge Downstream Ports Figure 8.3 ACS Upstream Forwarding Example When multiple ACS checks are enabled, they are prioritized as described below. Table 8.4 shows the prioritization for ACS checks associated with the reception of request TLPs.

  • Page 104: Error Detection And Handling

    IDT Theory of Operation Notes ACS Check Priority Comment ACS Upstream For- 2 (Highest) Applicable to request or completion TLPs warding received by the downstream port on its ingress link that target the port’s egress link. This is not considered a peer-to-peer transfer.

  • Page 105: Physical Layer Errors

    IDT Theory of Operation Notes A PCI-to-PCI Bridge function claims a TLP in the following cases: – Address Routed TLPs: If received on the primary side of the bridge, the TLPs address falls within the address space range(s) programmed in the base/limit registers. If received on the secondary side of the bridge, always.

  • Page 106: Transaction Layer Errors

    IDT Theory of Operation Notes A DL protocol error occurs when an ACK or NAK DLLP is received and the sequence number specified by AckNak_Seq does not correspond to an unacknowledged TLP or to the value in ACKD_SEQ Transaction Layer Errors Table 8.9 lists non-ACS error checks associated with a PCI-to-PCI bridge function and the action taken...

  • Page 107: Table 8.9 Transaction Layer Errors Associated With The Pci-To-Pci Bridge Function

    IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Poisoned TLP 2.7.2.2 Advisory when Detected Parity Error (DPE) bit in the received the correspond- PCISTS or SECSTS register set appro- ing error is con- priately.
  • Page 108 IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Unexpected com- 2.3.2 Yes if a func- Advisory when Non-advisory cases: uncorrectable pletion received tion claims the correspond- error processing.

  • Page 109: Table 8.10 Conditions Handled As Unsupported Requests (Ur) By The Pci-To-Pci Bridge Function

    IDT Theory of Operation Notes PCIe Specifica- Conditions handled as UR Description tion Section Routing Errors Refer to section Routing Errors on page 8-16. Numerous Vendor Defined Type 0 message recep- Vendor Defined Type 0 message which targets the 2.2.8.6 tion PCI-to-PCI bridge function.

  • Page 110: Table 8.12 Egress Malformed Tlp Error Checks

    IDT Theory of Operation Notes TLP Type Error Check Message Requests TC = 0 interrupt message Power management message Error signalling message Unlock message Set power limit message TLPs with Route to Root Complex routing. May only be received on downstream ports...

  • Page 111: Table 8.13 Acs Violations For Ports Operating In Downstream Switch Port Mode

    IDT Theory of Operation Notes Role Based Express (Advisory) ACS Check Specifica- Error Action Taken tion Reporting Section Condition ACS Source Validation 6.12.1.1 Advisory when If TLP is a non-posted request, a completion the correspond- with ‘completer abort’ status is generated. Note...

  • Page 112: Table 8.14 Prioritization Of Transaction Layer Errors

    IDT Theory of Operation Notes In addition, the Detected Parity Error bit (DPE) in the PCISTS and SECSTS registers is not subject to error pollution rules and is therefore set when the PCI-to-PCI bridge receives a poisoned TLP on its primary or secondary side respectively, even if error pollution rules indicate that the poisoned TLP received error is superseded by a higher priority error.

  • Page 113: Table 11.3 Table

    IDT Theory of Operation Notes TLP Received by Done Function Handle per Table 12.9 Receiver Overflow Error? Handle per Table 12.9 ECRC TLP Dropped? Error? If ECRC error detected, handle per Table 12.9 but do not log Malformed error; Else, Malformed TLP? handle per Table 12.9...

  • Page 114: Routing Errors

    IDT Theory of Operation Notes Note the following: – Except for ECRC and Poisoned TLP errors, all other errors detected on the received TLP cause the detecting function to consume, drop, or nullify the TLP. – Receiver overflow errors are only checked and logged.

  • Page 115: Bus Locking

    IDT Theory of Operation Notes Address Routed TLPs TLPs received by an upstream port that match the upstream port’s address range but which do not match a downstream port’s address range (i.e., TLPs that do not route through the switch).
  • Page 116 IDT Theory of Operation Notes A locked transaction sequence is requested by the root complex by issuing a Memory Read Request - Locked (MRdLk) transaction. A lock is established when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock is released with an Unlock message (Msg) sent by the root complex.
  • Page 117 IDT Theory of Operation Notes Note that when a TLP received by port is blocked from being forwarded due to a bus-locked switch, the TLP is delayed until the switch is unlocked. If the switch is locked for an extended period, this may cause TLPs to be discarded due to switch time-outs.
  • Page 118 IDT Theory of Operation Notes PES48T12G2 User Manual 8 - 20 April 5, 2013...

  • Page 119: Hot-Plug And Hot-Swap

    Chapter 9 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 9.1 through 9.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 9.1 illustrates the use of PES48T12G2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
  • Page 120 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES48T12G2 Port x Port y PCI Express PCI Express Device Device Figure 9.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES48T12G2 Master SMBus...

  • Page 121: Hot-Plug Signals

    IDT Hot-Plug and Hot-Swap Notes Associated with all PES48T12G2 ports is a hot-plug controller. However, hot-plug is only supported when a port is configured to operate in downstream switch port mode. In a port configured to operate in downstream switch port mode, the hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP) register associated with that port.

  • Page 122: Port Reset Outputs

    IDT Hot-Plug and Hot-Swap Notes PES48T12G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 12-5 for details on the operation of the I/O expanders and for the mapping of hot-plug signals to I/O expander inputs and outputs.

  • Page 123: Power Enable Controlled Reset Output

    IDT Hot-Plug and Hot-Swap Notes In addition to a port reset output being asserted as determined by the Reset Mode (RSTMODE) field, a port reset output is also asserted under the following circumstances. – When the switch experiences a fundamental reset.

  • Page 124: Hot-Plug Events

    IDT Hot-Plug and Hot-Swap Notes The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that when power is enabled, the negation of the corresponding port reset output occurs as a result of and after assertion of the slot’s Power Good (PxPWRGDN) signal is observed.
  • Page 125 IDT Hot-Plug and Hot-Swap Notes GPEN is a GPIO alternate function. The GPIO pin will not be asserted when GPEN is asserted unless it is configured to operate as an alternate function. Whenever a port signals a hot-plug event through asser- tion of the GPEN signal, the corresponding port’s status bit in the General Purpose Event Status (GPESTS)

  • Page 126: Hot-Swap

    IDT Hot-Plug and Hot-Swap Hot-Swap Notes PES48T12G2 is hot-swap capable and meets the following requirements – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.) – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

  • Page 127: Power Management

    Chapter 10 Power Management ® Introduction Notes Located in configuration space of each Function in the PES48T12G2 (i.e., PCI-to-PCI Bridge Function) is a power management capability structure. PES48T12G2 Functions support the following device power management states: – D0 (D0 and D0 uninitialized active –...

  • Page 128: Table 10.1 Pes48T12G2 Power Management State Transition Diagram

    IDT Power Management Notes Reset Uninitialized Active cold Figure 10.1 PES48T12G2 Power Management State Transition Diagram From State To State Description D0 Uninitialized Switch reset (any type). D0 Uninitialized D0 Active Function configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power...

  • Page 129: Pme Messages

    IDT Power Management Notes • This requires transitioning the link to the L0 state when the completion needs to be transmitted on the link by the bridge Function and the link is not in L0. – All request TLPs received on the secondary interface are treated as unsupported requests (UR).

  • Page 130: Power Budgeting Capability

    IDT Power Management Power Budgeting Capability Notes PES48T12G2 contains the mechanisms necessary to implement the PCI-Express power budgeting enhanced capability. However, by default, these mechanisms are not enabled. To enable the power budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to the power budgeting capability.

  • Page 131: General Purpose I/O

    Chapter 11 General Purpose I/O ® Introduction Notes The PES48T12G2 has 9 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function [1:0] (GPIOFUNCx), General Purpose I/O Configuration [1:0] (GPIOCFGx), General Purpose I/O Data [1:0] (GPIODx), and General Purpose I/O Alternate Function Select [1:0] (GPIO- AFSELx) registers.

  • Page 132: Table 11.2 General Purpose I/O Pin Alternate Function

    IDT General Purpose I/O Notes GPIO Pin Alternate Function 0 Alternate Function 1 — P0LINKUPN GPEN P0ACTIVEN IOEXPINTN — Table 11.2 General Purpose I/O Pin Alternate Function Alternate function signals are described in Table 11.3. Signal Type Name/Description General Purpose Event. Hot-plug general purpose event output IOEXPINTN I/O Expander x Interrupt Input.

  • Page 133: Smbus Interfaces

    Chapter 12 SMBus Interfaces ® Introduction Notes PES48T12G2 has two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers, allowing every register in the device to be read or written by an external SMBus master. The slave SMBus may also be used to program the serial EEPROM used for initialization.

  • Page 134: Initialization From Serial Eeprom

    IDT SMBus Interfaces Initialization from Serial EEPROM Notes During initialization from the optional serial EEPROM, the master SMBus interface reads configuration blocks from the serial EEPROM and updates corresponding registers in PES48T12G2. Any software visible register in the device may be initialized with values stored in the serial EEPROM.
  • Page 135 IDT SMBus Interfaces Notes TYPE Reserved Byte 0 (must be zero) Byte 1 SYSADDR[9:2] Byte 2 SYSADDR[18:10] Byte 3 DATA[7:0] Byte 4 DATA[15:8] Byte 5 DATA[23:16] Byte 6 DATA[31:24] Figure 12.2 Single Double Word Initialization Sequence Format The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.
  • Page 136 IDT SMBus Interfaces Notes The final type of configuration block is the configuration done sequence which is used to signify the end of a serial EEPROM initialization sequence. If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a configuration space (i.e., not defined in Chapter 14), then the Unmapped Register Initialization Attempt (URIA) bit is set in the SMBUSSTS register and the write is ignored.

  • Page 137: Programming The Serial Eeprom

    IDT SMBus Interfaces Notes Error Action Taken Configuration Done Sequence checksum mis- - Set RSTHALT bit in SWCTL register match with that computed - ICSERR bit is set in the SMBUSSTS register - Abort initialization, set DONE bit in the SMBUSSTS register...

  • Page 138: Table 12.3 I/O Expander Function Allocation

    IDT SMBus Interfaces Notes PES48T12G2 supports up to 14 external I/O expanders. Table 12.3 summarizes the allocation of func- tions to I/O expanders. I/O expander signals associated with LED control (i.e., link status and activity) are active low (i.e., driven low when an LED should be turned on). I/O expander signals associated with hot- plug signals are not inverted.

  • Page 139: Table 12.4 I/O Expander Default Output Signal Value

    IDT SMBus Interfaces Notes Outputs for ports that are disabled, mapped to GPIO alternate functions, or are not implemented in that configuration, are set to their negated value (e.g., the power indicator is turned off, the link is down, there is no activity, etc.).
  • Page 140 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by PES48T12G2 to I/O expanders 12 and 13 (i.e., the one that contains link up and link activity status). – Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 141 IDT SMBus Interfaces Notes The following are system design recommendations: – I/O expander addresses and default output values may be configured during serial EEPROM initialization. If I/O expander addresses are configured via the serial EEPROM, then PES48T12G2 will initialize the I/O expanders when normal device operation begins following the completion of the fundamental reset sequence.

  • Page 142: Table 12.7 Pin Mapping I/O Expander 9

    IDT SMBus Interfaces Notes I/O Expander 8 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P0MRLN Port 0 manually operated retention latch (MRL) input 1 (I/O-0.1) P1MRLN Port 1 manually operated retention latch (MRL) input 2 (I/O-0.2) P2MRLN Port 2 manually operated retention latch (MRL) input 3 (I/O-0.3)
  • Page 143 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 3 (I/O-0.3) P3ILOCKST Port 3 electromechanical interlock state input 4 (I/O-0.4) P4ILOCKST Port 4 electromechanical interlock state input 5 (I/O-0.5) P5ILOCKST Port 5 electromechanical interlock state input 6 (I/O-0.6) P6ILOCKST Port 6 electromechanical interlock state input 7 (I/O-0.7)

  • Page 144: Table 12.9 I/O Expander 12 - Link Up Status

    IDT SMBus Interfaces Notes I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y. I/O Expander 12 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P0LINKUPN Port 0 link up status output 1 (I/O-0.1) P1LINKUPN Port 1 link up status output 2 (I/O-0.2)

  • Page 145: Slave Smbus Interface

    IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 10 (I/O-1.2) Unused 11 (I/O-1.3) Unused 12 (I/O-1.4) P12ACTIVEN Port 12 Link active status output 13 (I/O-1.5) P13ACTIVEN Port 13 Link active status output 14 (I/O-1.6) Unused 15 (I/O-1.7) Unused Table 12.10 I/O Expander 13 - Link Activity Status (Part 2 of 2)

  • Page 146: Table 12.12 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Notes SIZE FUNCTION START Figure 12.5 Slave SMBus Command Code Format Name Description Field End of transaction indicator. Setting both START and END signi- fies a single transaction sequence 0 - Current transaction is not the last read or write sequence.

  • Page 147: Table 12.13 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Description Position Name CCODE Command Code. Slave Command Code field described in Table 12.12. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field.

  • Page 148: Table 12.14 Csr Register Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Name Type Description Field BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the data word is enabled. BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8] of the data word is enabled.

  • Page 149: Table 12.16 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Byte Field Description Position Name EEADDR Serial EEPROM Address. This field specifies the address of the Serial EEPROM on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be zero and thus the 7-bit address must be left justified.

  • Page 150: Figure 12.9 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec

    IDT SMBus Interfaces Notes Sample Slave SMBus Operation This section illustrates sample Slave SMBus operations. Shaded items are driven by PES48T12G2’s slave SMBus interface and non-shaded items are driven by an SMBus host. PES48T12G2 Slave CCODE BYTCNT=3 CMD=read ADDRL ADDRU...

  • Page 151: Figure 12.11 Serial Eeprom Write Using Smbus Block Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES48T12G2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 12.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES48T12G2 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 12.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled...
  • Page 152 IDT SMBus Interfaces Notes PES48T12G2 User Manual 12 - 20 April 5, 2013...

  • Page 153: Multicast

    Introduction Notes This IDT PCIe Switch implements multicast as defined by the PCI-SIG Multicast ECN. The multicast capability enables a single TLP to be forwarded to multiple destinations. The destinations to which a multi- cast TLP is forwarded are referred to as a multicast group.

  • Page 154: Figure 13.1 Multicast Group Address Ranges

    IDT Multicast Notes Only posted memory write TLPs and address routed message TLPs can be multicast TLPs. The primary determinant of whether or not a memory write or address routed message TLP is a multicast TLP is its address and the address associated with multicast address regions. A multicast address region may overlap a non-multicast address region.

  • Page 155: Figure 13.2 Multicast Group Address Region Determination

    IDT Multicast Notes The starting address of the region associated multicast group zero is equal to the multicast base address defined by the Multicast Base Address Low (MCBARL) field in the MCBARL register and the Multi- cast Base Address High (MCBARH) field in the Multicast Base Address High (MCBARH) register.

  • Page 156: Multicast Tlp Routing

    IDT Multicast Notes Note that the “block all” and “block untranslated” functions are performed at the ingress port on which the multicast TLP was received. A received multicast TLP without errors is forwarded to egress ports as described in the next section.
  • Page 157 IDT Multicast Notes A side-effect of modifying the address due to multicast overlay processing is that the ECRC associated with the original TLP may not be correct for the new modified TLP. Therefore, functions perform the following ECRC processing: – If multicast overlay processing is disabled, then no ECRC processing is performed as part of multi- cast egress processing.
  • Page 158 IDT Multicast Notes PES48T12G2 User Manual 13 - 6 April 5, 2013...

  • Page 159: Register Organization

    Chapter 14 Register Organization ® Introduction Notes All software visible registers in the PES48T12G2 are contained in a 256 KB global address space. The address of a register in this address range is referred to as the system address of the register. –...

  • Page 160: Partial-Byte Access To Word And Dword Registers

    IDT Register Organization Notes The entire PES48T12G2 global address space may be accessed using PCI configuration requests from any PES48T12G2 PCI function. – Located in each PCI function is a Global Address Space Access Address (GASAADDR) and Global Address Space Access Data (GASADATA) register.

  • Page 161: Capability Structures

    – Registers with offsets between 0x400 and 0xFFF are associated with PCI Express extended configuration space but are used to hold IDT proprietary port specific registers. In order to facilitate access to the PCI Express extended configuration space by legacy PCI software, the PCI-to-PCI bridge configuration space contains the Extended Configuration Space Access Address and Data registers (ECFGADDR and ECFGDATA).

  • Page 162: Table 14.3 Default Pci Express Capability List Linkage

    IDT Register Organization Notes Default Value of PCI Capability Structure Next Pointer Field (NXTPTR) Offset in Name Configuration Space PCI Power Management Capability (PMCAP) 0x0C0 0x0D0 Message Signaled Interrupt Capability (MSICAP) 0x0D0 Subsystem ID and Subsystem Vendor Capability 0x0F0 (SSIDSSVIDCAP) Table 14.2 Default PCI Capability List Linkage (Part 2 of 2)

  • Page 163: Figure 14.1 Pci-To-Pci Bridge Configuration Space Organization

    IDT Register Organization Notes 0x000 PCI Configuration Space (64 Dwords) 0x000 0x100 Type 1 Advanced Error Reporting Configuration header Enhanced Capability 0x180 Device Serial Number 0x040 Enhanced Capability PCI Express Capability Structure 0x200 PCIe Virtual Channel Enhanced Capability 0x280 Power Budging...

  • Page 164: Table 14.4 Pci-To-Pci Bridge Configuration Space Registers

    IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word VID - Vendor Identification Register (0x000) on page 15-1 0x002 Word DID - Device Identification Register (0x002) on page 15-1 0x004 Word PCICMD PCICMD - PCI Command Register (0x004) on page 15-1...
  • Page 165 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x044 DWord PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 15-11 0x048 Word PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 15-13 0x04A Word PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 15-14...
  • Page 166 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x10C Dword AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 15-36 0x110 Dword AERCES AERCES - AER Correctable Error Status (0x110) on page 15-37 0x114 Dword AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 15-38...
  • Page 167 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x308 Dword PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 15-48 0x30C Dword PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on...

  • Page 168: Idt Proprietary Port Specific Registers

    This section outlines the address range 0x400 through 0xFFF in the PCI-to-PCI bridge address space. This address range contains IDT proprietary registers that are port specific. Registers in this address range may be accessed using PCI configuration requests to the corresponding PCI-to-PCI bridge function 0 header, global address space access registers, SMBus, or serial EEPROM.

  • Page 169: Table 14.5 Proprietary Port Specific Registers

    IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x420 Dword PCIESCTLIV PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) on page 15-56 0x480 DWord IERRORCTL IERRORCTL - Internal Error Reporting Control (0x480) on page 15- 0x484...

  • Page 170: Switch Configuration And Status Registers

    IDT Register Organization Switch Configuration and Status Registers Notes This section outlines switch configuration and status registers. These registers are accessible using global address space access registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM. Figure 14.3 shows the organization of the address space. Registers in this address range are referenced as REGNAME where REGNAME represents the register name in Table 14.6.

  • Page 171: Table 14.6 Switch Configuration And Status

    IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0000 DWord SWCTL SWCTL - Switch Control (0x0000) on page 16-1 0x0004 DWord BCVSTS BCVSTS - Boot Configuration Vector Status (0x0004) on page 16-2 USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C)
  • Page 172 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0824 DWord S1TXLCTL0 S[13:12, 9:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 16-6 0x0828 DWord S1TXLCTL1 S[13:12, 9:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 on page 16-9...
  • Page 173 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x08E4 DWord S7TXLCTL0 S[13:12, 9:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 16-6 0x08E8 DWord S7TXLCTL1 S[13:12, 9:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 on page 16-9...
  • Page 174 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0AAC DWord GPIOCFG1 GPIOCFG1 - General Purpose I/O Configuration 1 (0x0AAC) on page 16-14 0x0AB0 DWord GPIOD0 GPIOD0 - General Purpose I/O Data 0 (0x0AB0) on page 16-14 0x0AB4...

  • Page 175: Pci To Pci Bridge And Proprietary Port Specific Registers

    DID - Device Identification Register (0x002) Field Default Type Description Field Name Value 15:0 Device Identification. This field contains the 16-bit device ID assigned by IDT to this bridge. PCICMD - PCI Command Register (0x004) Field Default Type Description Field Name Value IOAE I/O Access Enable.
  • Page 176 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VGAS VGA Palette Snoop. Not applicable. PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the PCI Status (PCISTS) register.
  • Page 177 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error Detected. This bit is set by the bridge function if the PERRE bit in the PCI Command register (PCICMD)
  • Page 178 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s function- ality but may be read and written by software.
  • Page 179 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is connected.
  • Page 180 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
  • Page 181 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MBASE - Memory Base Register (0x020) Field Default Type Description Field Name Value Reserved Reserved field. 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable transactions between the primary and secondary interfaces of the bridge.
  • Page 182 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:4 PMLIMIT Prefetchable Memory Address Limit. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forward- ing of prefetchable transactions between the primary and second- ary interfaces of the bridge.
  • Page 183 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CAPPTR - Capabilities Pointer Register (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. This field specifies a pointer to the head of the capabilities structure. EROMBASE - Expansion ROM Base Address Register (0x038)
  • Page 184 IDT PCI to PCI Bridge and Proprietary Port Specific Registers BCTL - Bridge Control Register (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the Secondary Status (SECSTS) register.

  • Page 185: Pci Express Capability Structure

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Capability Structure PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure.
  • Page 186 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to tran- sition from the L0s state to the L0 state.
  • Page 187 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCTL - PCI Express Device Control (0x048) Field Default Type Description Field Name Value CEREN Correctable Error Reporting Enable. This bit controls reporting of correctable errors. NFEREN Non-Fatal Error Reporting Enable. This bit controls reporting of non-fatal errors.
  • Page 188 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDSTS - PCI Express Device Status (0x04A) Field Default Type Description Field Name Value RW1C Correctable Error Detected. This bit indicates the status of cor- rectable errors. Errors are logged in this register regardless of whether error reporting is enabled or not.
  • Page 189 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum link width WDTH of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
  • Page 190 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indi- cates support for the link bandwidth notification status and interrupt mechanisms. The switch downstream ports support the capability.
  • Page 191 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCLK Common Clock Configuration. When set, this bit indicates that this port and the port at the opposite end of the link are operating with a distributed common reference clock.
  • Page 192 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Negotiated Link Width. This field indicates the negotiated width of the link. 00 0001b - x1 00 0010b - x2 00 0100b - x4...
  • Page 193 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value LABWSTS RW1C Link Autonomous Bandwidth Status. This bit is set to indicate that either that the PHY has autonomously changed link speed or width for reasons other than to attempt to correct unreliable link operation.
  • Page 194 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power supplied by the slot.
  • Page 195 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PFDE HWINIT Power Fault Detected Enable. This bit when set enables the gen- eration of a Hot-Plug interrupt or wake-up event on a power fault event.
  • Page 196 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Power Indicator Control. When read, this register returns the cur- rent state of the Power Indicator. Writing to this register sets the indicator.
  • Page 197 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MRLSC RW1C MRL Sensor Changed. Set when an MRL Sensor state change is detected. RW1C Presence Detected Changed. Set when a Presence Detected change is detected.
  • Page 198 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value Reserved Reserved field. ARIFS ARI Forwarding Supported. This bit is set to indicate that the switch supports ARI Forwarding.
  • Page 199 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELCTL2 - PCI Express Link Control 2 (0x070) Field Default Type Description Field Name Value Target Link Speed. For downstream ports, this field sets an upper Sticky limit on the link operational speed by restricting the values adver- tised by the upstream component in its training sequences.
  • Page 200 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Transmit Margin. This field controls the value of the non de- Sticky emphasized voltage level at the transmitter pins. This field is reset to 0x0 on entry to the LTSSM Polling.Configuration substate.

  • Page 201: Power Management Capability Structure

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value Current De-emphasis. The value of this bit indicates the current de-emphasis level when the link operates in 5.0 Gbps.
  • Page 202 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 18:16 Power Management Capability Version. This field indicates compliance with version two of the specification. Complies with version the PCI Bus Power Management Interface Specification, Revision 1.2.

  • Page 203: Message Signaled Interrupt Capability Structure

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PMEE PME Enable. When this bit is set, PME message generation is Sticky enabled for the port. If a hot plug wake-up event is desired when exiting the D3...
  • Page 204 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MSIADDR - Message Signaled Interrupt Address (0x0D4) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction.

  • Page 205: Subsystem Id And Subsystem Vendor Id

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Subsystem ID and Subsystem Vendor ID SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0xD identifies this capability as a SSID/ SSVID capability structure.

  • Page 206: Advanced Error Reporting (Aer) Enhanced Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 11:8 EREG Extended Register Number. This field selects the extended con- figuration register number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev. 2.0.
  • Page 207 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. DLPERR RW1C Data Link Protocol Error Status. This bit is set when a data link Sticky layer protocol error is detected.
  • Page 208 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the specifi- Sticky cation.
  • Page 209 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value UECOMP Unexpected Completion Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is...
  • Page 210 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Uncorrectable Internal Error Mask. When this bit is set, the cor- Sticky responding bit in the AERUES register is masked. When a bit is...
  • Page 211 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value COMPTO Completion Timeout Severity. A switch port does not initiate non- posted requests on its own behalf. Therefore, this field is hardwired to zero.
  • Page 212 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADTLP RW1C Bad TLP Status. This bit is set when a bad TLP is detected. Sticky BADDLLP RW1C Bad DLLP Status. This bit is set when a bad DLLP is detected.
  • Page 213 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit in the Sticky AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root com- plex.
  • Page 214 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERCTL - AER Control (0x118) Field Default Type Description Field Name Value FEPTR First Error Pointer. This field contains a pointer to the bit in the Sticky AERUES register that resulted in the first reported error. This field is valid only when the bit in the AERUES register pointed to by this field is set.

  • Page 215: Device Serial Number Enhanced Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 4th doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error.

  • Page 216: Pci Express Virtual Channel Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Virtual Channel Capability PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capa- bility structure.
  • Page 217 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. Not applicable (only the default VC 0 is implemented). PVCCTL - Port VC Control (0x20C) Field Default...
  • Page 218 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0CTL- VC Resource 0 Control (0x214) Field Default Type Description Field Name Value TCVCMAP bit 0: 0xFF TC/VC Map. This field indicates the TCs that are mapped to the VC resource.
  • Page 219 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VCNEG VC Negotiation Pending. This bit is not applicable for VC0 and is therefore hardwired to 0x0. 31:18 Reserved Reserved field. VCR0TBL0 - VC Resource 0 Port Arbitration Table Entry 0 (0x240)
  • Page 220 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL1 - VC Resource 0 Port Arbitration Table Entry 1 (0x244) Field Default Type Description Field Name Value PHASE8 Phase 8. This field contains the port ID for the corresponding port arbitration period.

  • Page 221: Power Budgeting Enhanced Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL3 - VC Resource 0 Port Arbitration Table Entry 3 (0x24C) Field Default Type Description Field Name Value PHASE24 Phase 24. This field contains the port ID for the corresponding port arbitration period.
  • Page 222 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PWRBDSEL - Power Budgeting Data Select (0x284) Field Default Type Description Field Name Value DVSEL Data Value Select. This field selects the Power Budgeting Data Value (PWRBDVx) register whose contents are reported in the Data (DATA) field of the Power Budgeting Data (PWRBD) register.

  • Page 223: Acs Extended Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACS Extended Capability ACSECAPH - ACS Extended Capability Header (0x320) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0xD indicates an ACS extended capa- bility structure.
  • Page 224 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstream Upstream ACS Upstream Forwarding. If set, indicates the port implements Port: Port: ACS Upstream Forwarding. Down- Downstream stream Port: Port: Upstream Upstream ACS P2P Egress Control.
  • Page 225 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstream Port: ACS P2P Completion Redirect Enable. When set, the port per- forms ACS Peer-to-Peer Completion Redirect. Downstream NOTE: This field remains read-write (RW) for downstream ports, Port: even if the corresponding bit in the ACSCAP register is cleared.

  • Page 226: Multicast Extended Capability

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Multicast Extended Capability MCCAPH - Multicast Enhanced Capability Header (0x330) Field Default Type Description Field Name Value 15:0 CAPID 0x12 Capability ID. The value of 0x12 indicates a multicast capability structure.
  • Page 227 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBARL- Multicast Base Address Low (0x338) Field Default Type Description Field Name Value INDEXPOS Index Position. When multicast is enabled, this field specifies the least significant bit of the multicast group number within a TLP address.
  • Page 228 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCRCVH- Multicast Receive High (0x344) Field Default Type Description Field Name Value 31:0 MCRCV Multicast Receive. Each bit in this field corresponds to one of the upper 32 multicast groups (e.g., bit 0 corresponds to multicast group 32, bit 1 corresponds to multicast group 33, and so on).
  • Page 229 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBLKUTL- Multicast Block Untranslated Low (0x350) Field Default Type Description Field Name Value 31:0 MCBLKUT Multicast Block Untranslated. Each bit in this field corresponds to one of the lower 32 multicast groups (e.g., bit 0 corresponds to multicast group 0, bit 1 corresponds to multicast group 1, and so on).

  • Page 230: Proprietary Port Specific Registers

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Proprietary Port Specific Registers Port Control and Status Registers PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable.
  • Page 231 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCIE Command Complete Interrupt Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.

  • Page 232: Internal Error Control And Status Registers

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. DLLLASCE Data Link Layer Link Active State Change Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.
  • Page 233 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE RW1C IFB Data Double Bit Error. This bit is set when a double bit ECC SWSticky error is detected in the IFB data RAM.
  • Page 234 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBPTLPTO EFB Posted TLP Time-Out. When this bit is set, the correspond- SWSticky ing error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
  • Page 235 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBCTLDBE EFB Control Double Bit Error. When this bit is set, the corre- SWSticky sponding error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
  • Page 236 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBPTLPTO EFB Posted TLP Time-Out. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
  • Page 237 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBDATDBE EFB Data Double Bit Error. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
  • Page 238 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IERRORTST - Internal Error Reporting Test (0x490) Field Default Type Description Field Name Value IFBPTLPTO IFB Posted TLP Time-Out. Writing a one to this bit sets the corre- sponding bit in the IERRORSTS register. This bit always returns a value of zero when read.

  • Page 239: Physical Layer Control And Status Registers

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Unreliable Link Detected. Writing a one to this bit sets the corre- sponding bit in the IERRORSTS register. This bit always returns a...
  • Page 240 IDT PCI to PCI Bridge and Proprietary Port Specific Registers LANESTS0 - Lane Status 0 (0x51C) Field Default Type Description Field Name Value RW1C Phy Disparity Error. Each bit in this field corresponds to a SerDes lane associated with the port. A bit is set when an 8B10B coding violation has resulted in a running disparity error in the received data stream.
  • Page 241 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PHYLCFG0 - Phy Link Configuration 0 (0x530) Field Default Type Description Field Name Value Reserved Reserved field. G1CME Gen1 Compatibility Mode Enable. When this bit is set, the PHY SWSticky operates in Gen1 Compatibility mode.

  • Page 242: Power Management Control And Status Registers

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers PHYPRBS - Phy PRBS Seed (0x55C) Field Default Type Description Field Name Value 15:0 SEED 0xFFFF Phy PRBS Seed Value. This field contains the PHY PRBS seed SWSticky value used for crosslink operation.

  • Page 243: Request Metering

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Request Metering RMCTL - Requester Metering Control (0x880) Field Default Type Description Field Name Value Enable. When this bit is set, request metering is enabled on the SWSticky corresponding input port. Refer to section Request Metering on page 3-7.

  • Page 244: Global Address Space Access Registers

    IDT PCI to PCI Bridge and Proprietary Port Specific Registers Global Address Space Access Registers GASAADDR - Global Address Space Access Address (0xFF8) Field Default Type Description Field Name Value Reserved Reserved field. 18:2 GADDR Global Address. This field selects the system address of the reg- ister to be accessed via the GASADATA register.

  • Page 245: Switch Configuration And Status Registers

    Chapter 16 Switch Configuration and Status Registers ® Switch Control and Status Registers SWCTL - Switch Control (0x0000) Field Default Type Description Field Name Value Reserved Reserved field. RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except the SWSticky SMBus interface remains in a quasi-reset state.
  • Page 246 This field is present for backwards compatibility with earlier IDT switches that implement a proprietary version of ARI forwarding. The setting of 0x1 corresponds to the operation dictated by the PCI Express base specification.

  • Page 247: Internal Switch Timer

    IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value P01MERGEN HWINIT Port 0 and 1 Merge. Boot configuration vector value sampled dur- ing a switch fundamental reset. P23MERGEN HWINIT Port 2 and 3 Merge. Boot configuration vector value sampled dur- ing a switch fundamental reset.

  • Page 248: Serdes Control And Status Registers

    IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 17:16 Operating Mode Change Action. This field specifies the action SWSticky taken when a modification is made to the operating mode of a port. 0x0 - (noaction) No action - preserve state...
  • Page 249 IDT Switch Configuration and Status Registers S[13:12, 9:0]CTL - SerDes x Control Field Default Type Description Field Name Value LANESEL 0x10 Lane Select. This field selects the lane on which the SerDes lane SWSticky control registers (S[x]TXLCTL0, S[x]TXLCTL1, S[x]RXLCTL, and S[x]RXEQLCTL) operate when written.
  • Page 250 IDT Switch Configuration and Status Registers S[13:12, 9:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 Field Default Type Description Field Name Value CDC_FS3DBG1 Transmit Driver Coarse De-Emphasis Control for Full Swing SWSticky mode in Gen1. This field provides coarse level control of the trans- mit driver de-emphasis level in full-swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
  • Page 251 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 11:10 TX_EQ_3DBG2 Transmit Equalization for Full Swing Mode with -3.5dB in SWSticky Gen2. This field controls the transmit equalization in Gen 2 data rate, when the SDE field in the associated port’s PCIELCTL2 regis- ter is set to -3.5 dB de-emphasis.
  • Page 252 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 25:23 TX_FSLEW_G2 Transmit Driver Fine Slew Adjustment in Gen2. This field allows SWSticky fine adjustment of the output driver’s slew rate at Gen 2 data-rate, for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL) register.
  • Page 253 IDT Switch Configuration and Status Registers S[13:12, 9:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 Field Default Type Description Field Name Value TDVL_FS3DBG1 0x11 Transmit Driver Voltage Level for Full-Swing Mode with -3.5dB SWSticky De-emphasis in Gen1. This field controls the SerDes transmit driver voltage level in full- swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
  • Page 254 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 15:13 FDC_FS3DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -3.5dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -3.5dB de-emphasis.
  • Page 255 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 23:21 FDC_FS6DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -6.0dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -6.0dB de-emphasis.

  • Page 256: General Purpose I/O Registers

    IDT Switch Configuration and Status Registers S[13:12, 9:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control Field Default Type Description Field Name Value RXEQZ Receiver Equalization Zero. Amplifies the high-frequency gain of SWSticky the equalizer. A value of 0x0 results in the smallest amount of high frequency gain.
  • Page 257 IDT Switch Configuration and Status Registers GPIOFUNC1 - General Purpose I/O Function 1 (0x0A94) Field Default Type Description Field Name Value 21:0 GPIOFUNC GPIO Function. Each bit in this field controls the corresponding SWSticky GPIO pin. When set, the corresponding GPIO pin operates as the selected alternate function.
  • Page 258 IDT Switch Configuration and Status Registers GPIOCFG0 - General Purpose I/O Configuration 0 (0x0AA8) Field Default Type Description Field Name Value 31:0 GPIOCFG GPIO Configuration. Each bit in this field controls the correspond- SWSticky ing GPIO pin. When a bit is configured as a general purpose I/O pin and the corresponding bit in this field is set, then the pin is con- figured as a GPIO output.

  • Page 259: Hot-Plug And Smbus Interface Registers

    IDT Switch Configuration and Status Registers GPIOD1 - General Purpose I/O Data 1 (0x0AB4) Field Default Type Description Field Name Value 21:0 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding GPIO SWSticky pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
  • Page 260 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 24:20 HP4GPIOPRT 0x1F Hot-Plug GPIO 4 Port Map. This field selects the switch port SWSticky whose hot-plug signals are mapped to GPIO alternate function HP4 signals. A value of all ones (i.e., 0x1F) indicates that no port is mapped to HPx GPIO alternate function signals.
  • Page 261 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value MRLPWROFF MRL Automatic Power Off. When this bit is set and the Manual SWSticky Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automat- ically turned off when the MRL sensor indicates that the MRL is open.
  • Page 262 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value BLANK RW1C Blank Serial EEPROM. When the switch is configured to operate in a mode in which serial EEPROM initialization occurs during a Switch Fundamental Reset, this bit is set when a blank serial EEPROM is detected.
  • Page 263 IDT Switch Configuration and Status Registers SMBUSCTL - SMBus Control (0x0ACC) Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock pres- SWSticky calar value used during master SMBus transactions. The prescalar clock period is equal to 32 ns multiplied by the value in this field.
  • Page 264 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value EEPROM Operation Select. This field selects the type of EEPROM operation to be performed when the DATA field is writ- 0x0 - (write) serial EEPROM write 0x1 - (read) serial EEPROM read...
  • Page 265 IDT Switch Configuration and Status Registers IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) Field Default Type Description Field Name Value Reserved Reserved field. IOE8ADDR I/O Expander 8 Address. This field contains the SMBus address SWSticky assigned to I/O expander 8 on the master SMBus interface.
  • Page 266 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value IGPE Invert General Purpose Event Enable Signal Polarity. When SWSticky this bit is set, the polarity of all General Purpose Event (GPEN) sig- nals is inverted. 0x0 - (normal) GPEN signals are active low...

  • Page 267: Jtag Boundary Scan

    DC values from being driven between a driver and receiver. AC Boundary Scan methodology described in IEEE 1149.6, is available to provide a time-varying signal to pass through the AC-coupling when in AC test mode. The IDT device supports both of these standards. Test Access Point The system logic utilizes a 16-state, TAP controller, a six-bit instruction register, and five dedicated pins to perform a variety of functions.

  • Page 268: Boundary Scan Chain

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 269: Table 17.2 Boundary Scan Chain

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PCI Express Interface PE00RN[3:0] PE00RP[3:0] PE00TN[3:0] PE00TP[3:0] PE01RN[3:0] PE01RP[3:0] PE01TN[3:0] PE01TP[3:0] PE02RN[3:0] PE02RP[3:0] PE02TN[3:0] PE02TP[3:0] PE03RN[3:0] PE03RP[3:0] PE03TN[3:0] PE03TP[3:0] PE04RN[3:0] PE04RP[3:0] PE04TN[3:0] PE04TP[3:0] PE05RN[3:0] PE05RP[3:0] PE05TN[3:0] PE05TP[3:0] PE06RN[3:0] PE06RP[3:0]...
  • Page 270 IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell PE12RN[3:0] PE12RP[3:0] PE12TN[3:0] PE12TP[3:0] PE13RN[3:0] PE13RP[3:0] PE13TN[3:0] PE13TP[3:0] GCLKN[1:0] — GCLKP[1:0] SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] System Pins CLKMODE[1:0] GCLKFSEL P01MERGEN P23MERGEN P45MERGEN P67MERGEN...

  • Page 271: Test Data Register (Dr)

    IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell SerDes Reference Resis- REFRES00 — tors REFRES01 — REFRES02 — REFRES03 — REFRES04 — REFRES05 — REFRES06 — REFRES07 — REFRES08 — REFRES09 — REFRES12 — REFRES13 — REFRESPLL —...

  • Page 272: Figure 17.3 Diagram Of Observe-Only Input Cell

    IDT JTAG Boundary Scan Notes Input To core logic To next cell From previous cell shift_dr clock_dr Figure 17.3 Diagram of Observe-only Input Cell The simplified logic configuration of the output cells is shown in Figure 17.4. EXTEST To Next Cell...

  • Page 273: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 17.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.

  • Page 274: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 275: Clamp

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x807B This field identifies the silicon. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES48T12G2.

  • Page 276: Extest_Pulse

    IDT JTAG Boundary Scan Notes If the Run-Test/Idle state is not entered, the output of the AC pins is not distinguishable from the output of the DC EXTEST instruction. EXTEST_PULSE EXTEST_PULSE is an instruction listed in IEEE 1149.6 JTAG specification and is used to test AC pins during boundary scan by shifting data from TDI to TDO within the Shift-DR-TAP controller State.

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