IDT 89HPES12N3 Manuals

Manuals and User Guides for IDT 89HPES12N3. We have 1 IDT 89HPES12N3 manual available for free PDF download: User Manual

IDT 89HPES12N3 User Manual

IDT 89HPES12N3 User Manual (158 pages)

PCI Express Switch

Brand: IDT | Category: Switch | Size: 1.65 MB

Table of Contents

About this Manual

3
- Finding Additional Information
  3
- Content Summary
  3
- Signal Nomenclature
  3
- Numeric Representations
  4
- Data Units
  4
- Revision History
  6
- Table of Contents
  7
1 PES12N3 Device Overview

17
- Introduction
  18
- Features
  19
- System Identification
  20
  - Vendor ID
    20
  - Device ID
    20
  - Revision ID
    21
  - Jtag ID
    21
- Logic Diagram
  22
- Figure 1.3 PES12N3 Logic Diagram
  22
- Pin Description
  23
- Table 1.3 PCI Express Interface Pins
  23
- Table 1.4 Smbus Interface Pins
  24
- Table 1.5 General Purpose I/O Pins
  24
- Table 1.6 System Pins
  25
- Table 1.7 Test Pins
  26
- Table 1.8 Power and Ground Pins
  26
- Pin Characteristics
  27
- Table 1.9 Pin Characteristics
  28
2 Clocking, Reset, and Initialization

29
3 Link Operation

37
- Introduction
  37
- Polarity Inversion
  37
- Link Width Negotiation
  37
- Lane Reversal
  37
- Figure 3.1 Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth[1:0]=0X2)
  38
- Figure 3.2 Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth[1:0]=0X1)
  38
- Link Retraining
  39
- Link down
  39
- Slot Power Limit Support
  39
- Notes
  41
4 Switch Operation

41
- Introduction
  41
- Figure 4.1 PES12N3 Switch Data Flow and Buffering
  41
- Table 4.1 PES12N3 Buffer Sizes
  42
- Routing
  43
- Table 4.2 PES12N3 Advertised Flow Control Credits
  43
- Data Integrity
  44
- Table 4.3 Switch Routing Methods
  44
- Switch Time-Outs
  45
- Locking
  45
- Interrupts
  47
- Table 4.4 PCI Compatible Intx Aggregation
  47
- Switch Core Errors
  48
- Table 4.5 PES12N3 Upstream Port Bridge Interrupt Mapping
  48
5 Power Management

51
6 Hot-Plug and Hot-Swap

55
- Introduction
  55
- Hot-Swap
  61
7 Smbus Interfaces

63
8 General Purpose I/O

79
9 Transparent Mode Operation

81
10 Test and Debug

143
- Device Test Modes
  143
- Serdes Test Clock
  147
11 JTAG Boundary Scan

149
- Introduction
  149
- Test Access Point
  149
- Signal Definitions
  149
- Figure 11.1 Diagram of the JTAG Logic
  149
- Table 11.1 JTAG Pin Descriptions
  150
- Figure 11.2 State Diagram of Pes12N3'S TAP Controller
  150
- Boundary Scan Chain
  151
- Table 11.2 Boundary Scan Chain
  151
- Test Data Register (DR)
  152
- Instruction Register (IR)
  154
  - Figure 11.6 Diagram of Bidirectional Cell
    154
  - Table 11.3 Instructions Supported by Pes12N3'S JTAG Boundary Scan
    154
  - Bypass
    155
  - Extest
    155
  - Sample/Preload
    155
  - Clamp
    156
  - Deviceid
    156
  - Figure 11.7 Device ID Register Format
    156
  - Reserved
    156
  - Unused
    156
  - Validate
    156
- Usage Considerations
  157

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