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IDT CPS-1848 User Manual

Central packet switch
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CPS-1848
User Manual
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Central Packet Switch
Formal Status
June 2, 2014

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Summary of Contents for IDT CPS-1848

  • Page 1 Titl ® CPS-1848 User Manual ™ Central Packet Switch Formal Status June 2, 2014...
  • Page 2 IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT.

  • Page 3: Table Of Contents

    Packet Generation and Capture ................................57 2.10.1 Packet Generation and Capture Mode Overview ........................58 2.10.2 Packet Generation and Capture Mode Programming Model....................59 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 4 Store-and-Forward or Cut-Through Mode ..........................98 5.3.3 Transmitter-Controlled or Receiver-Controlled Flow Control Mode..................98 Port-to-Port Performance Characteristics..............................99 5.4.1 Packet Latency Performance ..............................99 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 5 JTAG 1149.1 Events (Revision A/B Only) ..........................168 6.5.6 Configuration Block Events ..............................168 6.5.7 Trace, Filter, and PGC Events..............................169 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 6 Signaling in Slave Mode ................................. 177 7.4.2 Connecting to Standard-, Fast-, and Hs-Mode Devices as a Slave ..................180 7.4.3 CPS-1848 Memory Access through I2C as a Slave....................... 180 JTAG and Boundary Scan......................183 Overview........................................ 183 JTAG and AC Extest Compliance ................................183 Test Instructions.....................................
  • Page 7 10.7.14 Port {0..17} Capture 2 CSR ..............................260 10.7.15 Port {0..17} Capture 3 CSR ..............................261 10.7.16 Port {0..17} Error Rate CSR ..............................262 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 8 10.11.3 Port {0..17} Packet Generation and Capture Mode Data Register ..................304 10.12 IDT Specific Routing Table Registers ..............................305 10.12.1 Base Addresses for IDT Specific Routing Table Registers..................... 305 10.12.2 Broadcast Device Route Table Register {0..255} ........................306 10.12.3 Broadcast Domain Route Table Register {0..255} ........................307 10.12.4 Port {0..17} Device Route Table Register {0..255}........................
  • Page 9 10.13.57 Broadcast Trace 1 Mask 0 Register ............................338 10.13.58 Broadcast Trace 1 Mask 1 Register ............................339 10.13.59 Broadcast Trace 1 Mask 2 Register ............................339 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 10 10.16.3 Port {0..17} Implementation Specific Error Detect Register....................376 10.16.4 Port {0..17} Implementation Specific Error Rate Enable Register ..................379 10.16.5 Port {0..17} VC0 Acknowledgements Transmitted Counter Register ..................382 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 11 10.20.6 Lane {0..47} Error Rate Enable Register ..........................426 10.20.7 Lane {0..47} Attributes Capture Register..........................428 10.20.8 Lane {0..47} Data Capture 0 Register ............................ 429 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 12 10.21 Error Management Broadcast Registers..............................445 10.21.1 Broadcast Port Error Detect Register ............................. 445 10.21.2 Broadcast Port Error Rate Enable Register..........................447 11. References..........................449 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 13 List of Figures Figure 1: CPS-1848 Block Diagram ................................... 25 Figure 2: CPS-1848 Interconnect Diagram ................................26 Figure 3: Wireless Application....................................26 Figure 4: Military Open VPX System Application ............................... 27 Figure 5: Video and Imaging Application ................................... 27 Figure 6: S-RIO Port Diagram....................................
  • Page 14 Figure 45: JTAG Register Access – Write Timing Diagram ............................190 Figure 46: JTAG Register Access – Read Timing Diagram ............................190 Figure 47: JTAG Clock Constraints.................................... 191 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 15 Changing Lane Speed on Port 5 – Example 2............................74 Table 24: Configuring Bit Error Measurement ................................81 Table 25: Programming Model for CPS-1848 Data Generation, Link Partner Checking .................... 85 Table 26: Input Buffer Allocation Mode..................................89 Table 27: Crosspoint Buffer Allocation Mode................................
  • Page 16 Port-Write Programming Model Registers and Fields..........................148 Table 55: Standard (Type 1) Port-Write Format................................ 149 Table 56: IDT (Type 2) Port-Write Format ................................151 Table 57: Error Log Event Notification Examples ..............................153 Table 58: Standard Event Isolation Behaviors................................154 Table 59: Additional Packet Discard Isolation Trigger Functions..........................

  • Page 17: About This Document

    Additional Resources In addition to this user manual, which explains the functionality of the CPS-1848 and how to use the device, and the device’s datasheet which covers all electrical specifications, there are many additional resources available. For more information, contact IDT technical support at srio@idt.com.

  • Page 18: Device Revision Information

    This symbol indicates procedures or operating levels that may result in misuse or damage to the device. Device Revision Information This document supports all device revisions of the CPS-1848. Features that are applicable to a specific revision of the device are highlighted throughout the document (for more information, see Device Information CAR).
  • Page 19 Table 8 (Preparation For Hot Extraction on Port Y) • Added a section on Packet Transfer Validation and Debug CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 20 • Updated MINOR_REV and JTAG_REV in Device Information CAR • Updated MAX_DESTID and MCAST_MASK in Switch Multicast Information CAR CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 21 • Added a note to COUNT in each Counter register in Port Function Registers • Added a note to Port {0..17} Error and Status CSR[OUTPUT_DROP] CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 22 • Added the VC Register Block Header Register into the registers chapter; however, this register is not supported by the CPS-1848. • Added a new section called Port Reconfiguration Operations CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 23: Device Overview

    1). The switch is ideal for interconnecting Gen1 and Gen2 RapidIO endpoints, including microprocessors, DSPs, FPGAs, ASICs, and bridges. The CPS-1848 supports port widths of 1x, 2x, and 4x, and lane speeds of 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud. The switch supports the RapidIO long run specification (100 cm of FR4 with two connectors), so it is ideal for backplane and interchassis switching applications, as well as on-board interconnect.
  • Page 24 • Supervision, Fault Management, Congestion Management — Compliant with RapidIO Specification (Rev. 2.1), Part 8: Error Management Extensions Specification — IDT-specific Error Handling including error event history logging and interrupt generation — Event detect, count, watermark, threshold, data capture, and host notification capabilities —...

  • Page 25: Block Diagrams

    Figure 1 shows a high-level overview of the device. Conceptually, the CPS-1848 consists of four quadrants numbered 0 to 3. Each quadrant consists of 12 lanes that can be mapped to four or five ports. Each quadrant can have combinations of 1x, 2x,...

  • Page 26: Typical Applications

    IRQ_N Typical Applications The CPS-1848, in tandem with other RapidIO ecosystem switches and endpoints, enables next-generation compute density and power efficiency. This significantly increases channel capacity for 3G to 4G wireless infrastructure, media gateways, video conferencing, and military and medical imaging systems. Full peer-to-peer networking makes systems of arbitrary topology possible.

  • Page 27: Defense And Aerospace Application Benefits

    RapidIO Switch DSP S-RIO 2 x4 S-RIO DSP S-RIO 2 IDT Clock x4 S-RIO 156.25 DSP S-RIO 2 x4 S-RIO CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 28: Rapidio Ports

    Packet Transfer Validation and Debug Overview Each CPS-1848 S-RIO port is compliant to the RapidIO Specification (Rev. 2.1). Each port provides the S-RIO defined Physical Coding Sublayer (PCS) functionality and the packet exchange protocol management. Each port also connects to the...

  • Page 29: Key Features

    • Packet transmission cancellation • Link error detection and recovery • Packet forwarding • IDT-specific packet trace and filtering This functionality is compliant to the following S-RIO specifications: • RapidIO Specification (Rev. 2.1), Part 1: Input/Output Logical Specification • RapidIO Specification (Rev. 2.1), Part 2: Message Passing Logical Specification...

  • Page 30: Packet Routing

    Port n 0xDF or Invalid DEVICE ROUTE Use destID[7:0] to Port n Index Local Routing Table Multicast Multicast Mask (0x40-0x67) CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 31: Unicast Programming Model

    0xDF No Route 0xE0–FF Reserved 2.3.2 Unicast Programming Model The CPS-1848 supports the RapidIO standard programming model through the following registers: • Standard Route Table Entries Configuration destID Select CSR • Standard Route Table Entry Configuration Port Select CSR •...
  • Page 32 Per-Port Routing Tables The CPS-1848 has a routing table for each port. This allows packets with the same destID to be routed differently depending on which port they are received. This can be used to partition the switch, or to create virtual networks.

  • Page 33: Multicast Programming Model

    – This register controls whether or not a destID is routed according to a multicast mask. The CPS-1848 handles 8-bit destIDs, and 16-bit destIDs that start with 0x00, as the same. Forming an association for an 8-bit destID 0xXX forms an association with the 16-bit destID 0x00XX. The TYPE bit...

  • Page 34: Programming Examples

    This allows one multicast mask to be shared among many endpoints that do not want to receive the data they have sent. In some applications, it is useful to receive a message that has been multicast. This capability is supported by the CPS-1848 on a per-port basis through the use of the SELF_MCAST_EN bit in the Port {0..17} Operations...
  • Page 35 Standard Route Table Entries Configuration 0x70 destID Select CSR Standard Route Table Entry Configuration Port 0x74 Read Select CSR CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 36: Table 3: Unicast Programming Examples - Direct Programming

    0x88. Read Port 3 Routing Table entry for destID Port {0..17} Device Route Table Register 0xE13264 Read 0x99. {0..255} CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 37: Table 4: Multicast Programming Examples - Indirect Programming Model

    0x000000DD Select CSR 1. When a multicast mask is disassociated from a destID, the destID routing table value is 0xDF (drop packets). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 38: Flow Control

    Transmitter- and receiver-controlled flow control decide which packets to send based on a packet’s priority. The CPS-1848 supports the four standard RapidIO priorities numbered 0 to 3 where 3 is the highest priority. The CPS-1848 also supports the Critical Request Flow (CRF) bit which extends the number of priorities supported from four to eight.

  • Page 39: Multicast Event Control Symbols

    Multicast Event Control Symbols (MECS) distribute events with low latency and little variability in distribution delays throughout a RapidIO system. An MECS can be received by a CPS-1848 port, or can be triggered by the MCAST pin on the device. Once an MECS event has been received/triggered, the MECSs are transmitted by each port with the MCAST_CS field set to one in Port {0..17} Control 1...

  • Page 40: Disabling Idle2 Operation

    A RapidIO device can be reset using a RapidIO reset request. This type of reset request consists of four reset request control symbols received with no intervening control symbols, except status control symbols. The CPS-1848 can handle a RapidIO reset request in one of two ways, based on the value of the PORT_RST_CTL field of the Device Control 1 Register.
  • Page 41 Final Buffer, including maintenance packet responses. To recover, the port must send a Link-Request/Input Status control symbol and receive a response. This will clear the PORT_ERR and packet drop condition. The CPS-1848 will send a Link-Request/Input Status control symbol when either of the following occurs: •...

  • Page 42: Port Disable/Enable

    The following sections use the phrase “hot-swap link partner” (HS-LP) to identify the entity that is the subject of the hot extraction/insertion or reset. The HS-LP can be the link partner of the CPS-1848, or can be the CPS-1848 itself.

  • Page 43: Hot Extraction

    For these reasons, it is assumed that the system should not have transactions flowing in either direction through the CPS-1848 port when preparing for a hot extraction or link partner reset. The act of removing/resetting the HS-LP will cause errors to be detected on the link. Additionally, since the link partner is no longer present, events unrelated to hot swap/reset should be suppressed.

  • Page 44: Table 8: Preparation For Hot Extraction On Port Y

    Configure the port’s routing table to discard all packets received by this port, as described in Packet Routing. received from the HS-LP. This should stop requests from being issued by the HS-LP. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 45: Table 9: Preparation For Hot Insertion On Port Y

    A port-write or interrupt indicating an OUTPUT_FAIL or PORT_ERR standard event acts as confirmation that the HS-LP has been removed or reset. Once this confirmation is received, the system can prepare the CPS-1848 port to bring the HS-LP back into the system.
  • Page 46 Removal/Reset. An unexpected extraction cannot be distinguished from link re-initialization. This implies that if a link re-initializes, the system will react as if the link partner has been removed and re-inserted. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 47: Table 10: Preparation Of Port That Can Be Subjected To Unexpected Hot Extraction Event

    Table 9 should be performed to ensure that all packets in flight to/from the HS-LP are discarded, and that system software is informed when the HS-LP reappears in the system. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 48: Link Partner Insertion

    When the Recovery Controller resides on the CPS-1848 side of the link connected to the HS-LP, it is assumed that the HS-LP has been reset. To guarantee that this is the case, IDT recommends that the Recovery Controller reset the HS-LP as part of this procedure.

  • Page 49: Table 11: System Recovery Controller Operation, Hs-Lp On Port Y

    Table 11: System Recovery Controller Operation, HS-LP on Port Y Step Register Offset Value Description 1. Establish routing Configure routing tables to allow maintenance access to CPS-1848 port and the HS-LP. The procedures are to/from the HS-LP. described in Packet Routing. 2. Disable event Port {0..17} Error...

  • Page 50: Table 12: Hs-Lp Recovery Controller

    Note that the procedure assumes that the HS-LP is another CPS-1848, or a device with a compatible programming model. If the HS-LP is not a CPS-1848 then HS-LP implementation-specific register accesses may be necessary. Register references made with address computations are for the CPS-1848.
  • Page 51 Reset HS-LP (Local) port n. Register port is not known, skip Control Register HS-LP (Local) values are given assuming that the HS-LP step 6 and proceed to (Local) is a CPS-1848 (Remote). If the Implementation step 7. HS-LP (Local) is not a CPS-1848 Implementation Specific...
  • Page 52 Implementation (Remote), the register address and value Specific written are implementation specific. Clear error status bits on HS-LP (Local) and CPS-1848 (Remote). Packet exchange can now resume. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 53: Packet Trace And Filtering

    ..................bit Comparison Mask ................X n<160 X = don’t care The Trace Criteria architecture is displayed in Figure CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 54: Figure 9: Trace Function Within A Port

    In the case where there is a trace match and the packet’s destID references the output port configured as the trace port, the packet will be forwarded only once regardless of the packet type. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 55 • To change the packet trace comparison values of any port. Note that the packet trace function at the port must be disabled to make this change • To enable/disable any/all trace comparison values of any port CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 56 The STOP_EM bit of the Error Log Control 2 Register disables all IDT maintenance packet port-writes generated by the device. This bit also applies to port-writes that are generated as a result of trace matches. Trace match based port-writes are enabled via TRACE_PW_EN in the Port {0..17} Operations...

  • Page 57: Packet Filtering

    PGC mode is normally controlled using debug tools connected directly to the CPS-1848’s I2C or JTAG interfaces when no other control entity exists in the system. It is also possible to use PGC mode during the normal operation of a system.

  • Page 58: Packet Generation And Capture Mode Overview

    (see also Port Loopback Mode). The response packet from the link partner is then routed to the End Port. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 59: Packet Generation And Capture Mode Programming Model

    The Start port will send packets as if they Capture Mode were priority 0 with the CRF bit set. Configuration Register CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 60 Check that RX_DONE bit (0x00008000) is set before continuing. Note: 0x00006004 must be written to offset 0x100140 before each read from offset 0x100144. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 61 Check that SOP is 0, and EOP bit is 1. 0x00006004 Enable read access to final buffer priority 1 queue. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 62: Packet Transfer Validation And Debug

    2. RapidIO Ports > Packet Transfer Validation and Debug The Start Port can revert to normal operation without resetting the CPS-1848. The End Port, however, cannot revert to normal operation until a software or hardware device reset. The End Port can receive only the first 25 packets.

  • Page 63: Successful Packet Transfer

    It may also indicate that the switch is unable to send packets to the destination (for more information, see Switch Cannot Transmit Packets). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 64: Table 16: Configuration And Status Values To Check - Switch Cannot Accept Packets

    PORT_OK If this bit is set to 0, the link is not connected to the link partner. For more information, see the Debugging IDT S-RIO Gen2 Switches Using RapidFET JTAG. PORT_ERR If this bit is set to 1, the standard hardware error recovery has failed.

  • Page 65: Switch Is Not Routing Packets Correctly

    If the registers in Table 17 are set correctly, then each route must be verified individually (for more information, see Packet Routing). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 66: Switch Cannot Transmit Packets

    Check Port {0..17} Control 1 CSR[ERR_CHK_DIS] on all input ports. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 67: Table 19: Configuration And Status Values To Check - Switch Cannot Transmit Packets

    OUTPUT_PORT_EN This bit must be set to allow the port to transmit non-maintenance packets. For Revision C of the CPS-1848, the reset value for this bit is 1; for Revision A/B, the reset value is 0. PORT_LOCKOUT This bit must be cleared to transmit any packets.

  • Page 68: Requesting Debug Assistance

    Requesting Debug Assistance If you are unable to resolve issues in your system using the information in this document, please contact IDT RapidIO support. As part of the request, please submit the following register values for all ports on the device. This is the first step in resolving the issue.

  • Page 69: Rapidio Lanes

    RapidIO Lanes The CPS-1848 S-RIO lane blocks include the Serializer/Deserializer (SerDes), as well as the logic to convert between the SerDes interface and the port interface. Topics discussed include the following: • Lane to Port Mapping • Lane and Port Speeds •...

  • Page 70: Lane To Port Mapping

    20, each S-RIO port can be comprised of one, two, or four lanes (this is called port width). After a device reset, the CPS-1848’s port width settings and lane to port mapping are configured based on the setting of the QCFG[7:0] pins (for more information, see the CPS-1848 Datasheet).
  • Page 71 20–23 36–37 38–39 4–5 20–23 36–39 Quadrant 2 / QCFG[5:4] 8–11 24–27 40–43 14 (Unused) 8–9 10–11 24–27 40–43 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 72: Table 21: Pwidth_Ovrd Examples

    Register, IDT recommends resetting each port as described in Table 2. After a device reset, the value of QCFG[7:0] determines the CPS-1848’s quadrant configurations. Software can also control the quadrant configurations based on the value of QUADx_CFG in the Quadrant Configuration Register.

  • Page 73: Lane And Port Speeds

    Lane and Port Speeds Each S-RIO port can support all lane rates. CPS-1848 ports that are connected to the same group of four lanes have restrictions on their possible lane rates. Ports can operate in either of two lane-speed groups: 1.

  • Page 74: Table 22: Changing Lane Speed Group On Ports 0 And 12 - Example 1

    Register 0xFF9700 0xXXXXX14 Set TX_RATE and RX_RATE fields to 0b01. Set LANE_DIS field to 0. Lane {0..47} Control Register CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 75: Lane, Pll, And Port Power-Down

    Port {0..17} Lane Synchronization Register. 2. IDLE sequence negotiation. The CPS-1848 attempts to use the RapidIO Gen2 IDLE2 sequence for all lane speeds. If the CPS-1848 detects that the link partner is using the RapidIO Gen1 IDLE1 sequence, it selects the IDLE1 sequence.

  • Page 76: Signal Quality Optimization

    7. The link-level flow control mode (transmitter or receiver controlled) is negotiated as part of the exchange of status control symbols. The CPS-1848 always attempts to use transmitter-controlled flow control, and reverts to receiver-controlled flow control if the link partner does not support the transmitter method.
  • Page 77 The CPS-1848 supports lane lengths up to those specified by the RapidIO medium-run PHY standard without link partner transmit emphasis or DFE. The transmit emphasis settings of the CPS-1848 and the link partner may need to be adjusted for channels longer than medium run. Depending on the electrical characteristics of the channel, CPS-1848 receiver DFE may also be necessary for channels longer than medium run.
  • Page 78 The following figure shows the effects on the waveform for the POS1_TAP settings of zero (top), 30 (middle) and 63 (bottom). The NEG1_TAP is set to 0 and the TX_AMP_CTL value is set to 52 (default). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 79 The dB value is calculated as: 20log (step amplitude / first bit amplitude). The following figure shows the effects on the waveform for the TX_AMP_CTL settings of zero (top), 30 (middle), and 60 (bottom). The NEG1_TAP and POS1_TAP controls are set to 0. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 80 Register.TAP_4_CFG The “select” control bit must be set to 1 in order for the associated tap value field to have any effect. IDT recommends that Tap 4 should be half the value of Tap 3, Tap 3 should be half the value of Tap 2, and Tap 2 should be half the value of Tap 1. Note that the signed Tap values should all be positive.

  • Page 81: Table 24: Configuring Bit Error Measurement

    To monitor errors on an lane-by-lane basis, use the ERR_8B10B field of the Lane {0..47} Status 0 CSR. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 82: Loopback Capabilities

    3. RapidIO Lanes > Loopback Capabilities Loopback Capabilities The CPS-1848 supports several lane and port loopback points that can be used for test and fault isolation purposes. These loopback points are displayed in Figure 14 and are discussed in the following sections.

  • Page 83: Lane Loopback Modes

    Each S-RIO port can route packets back out the port they were received on. This mode is supported by the routing tables (for more information, see Packet Routing). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 84: Bit Error Rate Testing

    The first 10 bits of this register is used for one seed and the next 10 bits for the other. 3.6.2 User-Defined Patterns In addition to random bit sequences, the CPS-1848 also supports patterns that are deterministic. There are three pattern options. The pattern value is the least significant 10 bits (22–31) of the Lane {0..47} PRBS Generator Seed Register: 1.

  • Page 85: Prbs Pattern Generator

    PRBS Pattern Generator The CPS-1848 BER generator sources data that is checked by the link partner. In the following example, the CPS-1848 is responsible only for transmitting data and PRBS is configured on lane 12 to use the polynomial x...
  • Page 86 4. Set Lane {0..47} Control Register[PRBS_EN] to 1. 3.6.4.2 PRBS Checking To configure the CPS-1848 to check a received PRBS sequence without 8b/10b encoding, perform the following steps: 1. Set Lane {0..47} PRBS Generator Seed Register[PRBS_SEED] as required. 2. Set Lane {0..47} Control...

  • Page 87: Switch Fabric

    • Can multicast and broadcast a received packet to multiple output ports • Supports cut-through and store-and-forward packet forwarding modes • Supports an optional queue aging function to ensure fairness across priorities CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 88: Switch Fabric Architecture

    Transactions handling block, and a separate path from the Maintenance Transactions block to each Final Buffer. More information about buffer sizing, arbitration, and controls for buffers and transaction arbitration are discussed in the following sections. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 89: Input Buffer

    Input Buffer to Crosspoint Buffer Transfers The CPS-1848 can wait until the entire packet has been received, or can start to forward the packet to a Crosspoint Buffer as soon as possible. Once a packet’s destID information has been received, the CPS-1848 can determine what output port to send the packet to.

  • Page 90: Voq Fairness/Starvation Avoidance

    To correct this behavior if it occurs, the CPS-1848 uses a fairness mechanism based on Oldest Queue First scheduling. The fairness mechanism limits the maximum latency for low priority packets. This scheduler mode is enabled...

  • Page 91: Crosspoint Buffer To Final Buffer Transfers

    If the maintenance packet does not have a hop count of 0, the CPS-1848 decrements the hop count, recomputes the CRC, and forwards the packet. The packet is routed according to the routing table and multicast configuration of the port that received the maintenance packet.

  • Page 92: Final Buffer

    Register.BUF_ALLOC also controls buffer allocation for the Input Buffers and Crosspoint Buffers. The CPS-1848 supports an additional option for Final Buffer allocation. If BUF_ALLOC in the Switch Parameters 1 Register 0, then FB_ALLOC in the same register provides additional options for the number of buffers free when packets of a specific priority are no longer accepted.

  • Page 93: Performance

    Latency is measured as the time interval between the first bit of the Start-of-Packet arriving at the ingress of the CPS-1848 and that same bit leaving the device.

  • Page 94: Latency Variation

    5.1.3 Latency Variation In the CPS-1848, packets can experience an extra one or two clock cycles of delay over the minimum latency when crossing from one clock domain to another clock domain. Another factor which contributes to latency variation is when the transmitted packet experiences errors on the link. If transmitter-controlled flow control mode is used between the CPS-1848 and the destination port, the CPS-1848 will not send the first bit if the destination has no available buffers.

  • Page 95: Traffic Efficiency

    5. Performance > Performance Monitoring Each S-RIO port in the CPS-1848 has a copy of the performance monitoring registers. Table 29 lists the statistic parameters that are available from the Inbound and Outbound registers, as part of each port’s performance monitoring capabilities.

  • Page 96: Performance Measurements

    5.3.1 Buffer Management Settings There are three stages of buffering in the CPS-1848: Input buffer, Crosspoint buffer, and Final Buffer. The Input Buffer can accept up to 12 packets. Each Crosspoint Buffer can accept up to 9 packets. The final buffer can accept up to 34 packets.
  • Page 97 (2 maximum sized packets) should provide more proportional fairness. For mixed sized packets, a value somewhere in between should produce more optimal results. When using 17 or 18 ports of the CPS-1848, software must set the default credit count to be less than 455 for all ports using Switch Parameters 1 Register[OUTPUT_CREDIT_RSVN].

  • Page 98: Store-And-Forward Or Cut-Through Mode

    5.3.2 Store-and-Forward or Cut-Through Mode The CPS-1848 supports two buffer management modes: Store-and-Forward and Cut-Through. Store-and-Forward mode ensures an incoming packet is completely received before it is forwarded, while the use of Cut-Through mode forwards the incoming packet as soon as possible.

  • Page 99: Port-To-Port Performance Characteristics

    The performance numbers in this section use a simple measurement consisting of a port-to-port traffic model to characterize the maximum throughput and minimum latency performance of the CPS-1848. In this case, all traffic is of the same size and priority. Due to the simple type of traffic, the throughput and latency performance numbers do not change with the priority of the packets.

  • Page 100: Packet Throughput Performance

    5.4.2 Packet Throughput Performance Packet throughput varies from the packet type, availability of resources within the CPS-1848, ability for source and destination of traffic to generate or receive packets, retries of packet, and actual data rates. A bubble is a control symbol inserted by an egress port into a packet to maintain the baud rate of the port. The appearance of a bubble indicates that the egress port is under-utilized.
  • Page 101 This is true for any payload size and different priorities. The arbitration scheme within the CPS-1848 allocates sufficient bandwidth for each ingress port. When the total of the ingress line rates exceeds that of the egress port, retries occur at one or more of the ingress ports if the packet density exceeds the capacity of the egress port.

  • Page 102: Multicast Latency Performance

    243.6 264.6 1. Due to the asynchronous ability of the clock frequencies within the CPS-1848, the latency numbers can vary as much as two 312.5 MHz clock period and two reference clock (REF_CLK) period. 2. Under no contention, the minimum variation is 0 ns.

  • Page 103: Multicast-Event Control Symbol (Mecs) Latency

    98.6 130.8 166.0 84.2 103.4 3.125 157.2 192.4 98.6 117.8 174.8 210.0 108.2 127.4 1.25 262.8 298.0 156.2 175.4 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 104: Event Management

    The CPS-1848 can detect a large number of events. Many events related to RapidIO protocol errors are always detected. Other events are detected only when the CPS-1848 is configured to do so. Detected events may cause the capture of related information.

  • Page 105: Figure 17: Event Management Overview (Revision A/B)

    JTAG_PW_EN JTAG_INT_EN JTAG_LOG_EN Config Event Detected Config Event Enables CFG_PW_EN CFG_INT_EN CFG_LOG_EN Filter Event Detected Filter Err Log Enable CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 106: Figure 18: Event Management Overview (Revision C)

    Revision C. I2C_LOG_EN Config Event Detected Config Event Enables CFG_PW_EN CFG_INT_EN CFG_LOG_EN Filter Event Detected Filter Err Log Enable CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 107: Table 34: Event Management Enable Bits

    1. JTAG Event Management is applicable to Revision A/B only. The CPS-1848 has two functions for notifying a software entity that it has detected an event: a port-write and an interrupt signal. A RapidIO port-write packet is a type of maintenance packet “in band” notification of an event. These packets are sent at the recommended highest priority and can always make forward progress through the CPS-1848.

  • Page 108: Logical/Transport Layer Events Overview

    6. Event Management > Event Management Overview Some events indicate that the CPS-1848’s link partner cannot accept packets. Packets routed to the failed link partner will therefore cause congestion in the CPS-1848, and may eventually lead to system failure. Depending on the system’s fault tolerance strategy, the CPS-1848 can be configured to retain packets, discard packets on transmission errors, or discard all packets sent to the failed link partner.

  • Page 109: Physical Layer Error Management Overview

    Physical Layer Error Management Overview The CPS-1848 can detect many types of physical layer errors. Physical layer errors are grouped into “Standard” physical layer errors, which are defined by the RapidIO Interconnect Specification (Revision 2.1), Part 8 Error Management Specification, and “Implementation Specific”...

  • Page 110: Figure 21: Implementation Specific Physical Layer Error Management Programming Model Flow Chart

    Interrupts from other Layers, Functions and Error Logging Error Logging PORT_n_OPS[PORT_LOG_EN] PORT: 0xF40004 + P# * 0x100 BCST: 0xF4FF04 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 111: Lane Error Management Overview

    6. Event Management > Event Management Overview 6.1.3 Lane Error Management Overview Each CPS-1848 port is connected to 1, 2, or 4 lanes. Each lane can detect and report errors. Errors detected at the lane level are indicated in the Lane {0..47} Error Detect Register.

  • Page 112: I2C Error Management Overview

    0xF20050 Interrupts from other JTAG_CTL[JTAG_INT_EN] Layers, Functions, and Error Logging 0xF2005C Error Logging AUX_PORT_ERR_RPT_EN 0xF200018 I2C: I2C_LOG_EN JTAG: JTAG_LOG_EN CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 113: Configuration Error Management Overview

    [CFG_INT_EN] 0xF200014 Interrupts from other Layers, Functions and Error Logging Error Logging CFG_BLK_ERR_RPT[CFG_LOG_EN] 0xF200014 Event Detection The CPS-1848 detects the following types of events: • Logical and Transport Layer Events • Physical Layer Events • Lane Events • I2C Events •...

  • Page 114: Table 35: Logical/Transport Layer Event Enable And Information Capture Summary

    6. Event Management > Event Detection The CPS-1848 detects transport layer events (that is, ILL_TRAN) for all packets. The device detects logical layer events for maintenance packets only when they have a hop count of 0. For more information on these events, see the...

  • Page 115: Physical Layer Events

    Note that information is located only in the Port {0..17} Capture 1 CSR if IDLE2/long control symbols are active. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 116 One data character is captured for the event. This information is in the following registers: Port {0..17} Attributes Capture CSR Port {0..17} Capture 0 CSR[24:31] contains the data character. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 117: Table 37: Physical Layer "Leaky Bucket" Events And Information Capture Summary

    Port Link Timeout Control Port {0..17} Error Rate Enable AckID CSR.TIME_OUT_VAL <> 0 CSR.LINK_TIMEOUT_EN = 1 Port {0..17} Error Detect CSR.LINK_TIMEOUT CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 118 Specific Error Detect Port {0..17} Implementation Register.UNSOL_LR Specific Error Rate Enable Port {0..17} Error Detect Register.UNSOL_LR_EN = 1 CSR.PRTCL_ERR CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 119 Port {0..17} Implementation Register.RTE_ISSUE Specific Error Rate Enable Port {0..17} Error and Status Register.RTE_ISSUE_EN = 1 CSR.PORT_ERR = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 120 CSR.IMP_SPEC_ERR_EN = 1 packet Port {0..17} Implementation Port {0..17} Implementation Specific Error Detect Specific Error Rate Enable Register.SHORT Register.SHORT_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 121 CSR.IMP_SPEC_ERR_EN = 1 Port {0..17} Implementation Specific Error Detect Port {0..17} Implementation Register.RX_STOMP Specific Error Rate Enable Register.RX_STOMP_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 122 CSR.IMP_SPEC_ERR_EN = 1 Port {0..17} Implementation Specific Error Detect Port {0..17} Implementation Register.PORT_WIDTH Specific Error Rate Enable Register.PORT_WIDTH_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 123 CSR.TTL, the following actions are taken: • The packet is discarded • Port {0..17} Error and Status CSR.OUTPUT_DROP is set CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 124: Lane Events

    When a CPS-1848 port's link partner re-initializes or is extracted from the system, packets may be discarded due to TTL. Depending on the timing of the extraction, it may not be possible for the switch port to resume transmission without software intervention.

  • Page 125: Table 39: Lane Event Enable And Information Capture Summary

    Received an illegal or invalid Always Detected Lane {0..47} Error Rate Enable Character character Register.BAD_CHAR_EN Lane {0..47} Error Detect Register.BAD_CHAR CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 126: I2C Events

    Enable Information Captured JTAG incomplete write Always Detected Aux Port Error Capture Enable Aux Port Error Detect Register.JTAG_ERR_EN Register.JTAG_ERR CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 127: Configuration Block Events

    Configuration Block Events Register accesses to the CPS-1848 can cause the detection of a number of events which indicate illegal register programming has occurred. No additional information is captured for configuration block events, other than the fact that the event occurred.

  • Page 128: Figure 25: Error Management Block Architecture

    Error Log Event Source Encoding Each functional block that supports the error reporting function is defined as an “Event Source”. The CPS-1848 allows the user to enable and disable the error reporting functionality of each of these sources. Regardless of whether or not reporting is enabled, all errors that are received by the Error Management Block are stored in the Error Log.
  • Page 129 0x61 Lane 34 0x62 Lane 35 0x63 Lane 36 0x64 Lane 37 0x65 Lane 38 0x66 Lane 39 0x67 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 130 0x24 LT Layer 0x1E Configuration 0x00 JTAG 0x00 0x00 1. JTAG event source is applicable to Revision A/B only. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 131: Table 44: Error Codes For Implementation Specific Lt Errors

    Error Log. The Error Management Block records all of the errors up to the speed of arbitration between all the sources (for more information, see Performance). The CPS-1848 provides an Error Log Data Register for reading out the first error from the Error Log.

  • Page 132: Table 46: Error Log Implementation Specific Port Error Encoding

    IMP_SPEC SET_ACKID Discarded a non-maintenance 0x73 IMP_SPEC TX_DROP packet to be transmitted IDLE character in packet 0x74 IMP_SPEC IDLE_IN_PKT CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 133 Received a packet with an invalid 0x91 IMP_SPEC BAD_TT Received NACK other than lack 0x92 IMP_SPEC of resources CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 134 RX retry count triggered 0xAA IMP_SPEC MANY_RETRY congestion event CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 135: Table 47: Error Log Lane Level Encoding

    6.2.9.3.2 C Error Codes The I C errors displayed in the following table can be detected by the CPS-1848. If I C error reporting is enabled each error can be sent to the Error Log when detected. Table 48: I...

  • Page 136: Table 49: Jtag Errors And Codes (Revision A/B Only)

    6.2.9.3.3 JTAG Error Encoding (Revision A/B Only) The JTAG error displayed in the following table is detectable by the CPS-1848. If JTAG error reporting is enabled the error can be sent to the Error Log when detected. Table 49: JTAG Errors and Codes (Revision A/B Only)

  • Page 137: Event Notification

    Additionally, all events can be sent to the IDT-specific Error Log function. The Error Log function consists of the following: • A 256 entry buffer that captures all events in the order in which they occurred globally in the switch •...

  • Page 138: Table 52: Logical/Transport Layer Event Notification Control

    6. Event Management > Event Notification To generate an IDT port-write for logical/transport layer events, see Error Log Events. Table 52: Logical/Transport Layer Event Notification Control Event Standard Port-Write Reporting Interrupt Reporting Error Log Reporting Illegal transaction decode Logical/Transport Layer Error...

  • Page 139: Physical Layer Events Notification

    The CPS-1848 exceeds the RapidIO specification required notifications to allow individual physical layer events to trigger interrupt or Standard port-write notification. Additionally, the Error Log allows IDT port-write notification for selected events, as...

  • Page 140: Table 53: Physical Layer Event Notification Control

    Register.LR_ACKID_ILL_EN = 1 Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 141 Register.CRC_EVENT_EN = 1 Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 142 Register.RTE_ISSUE_EN = 1 Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 143 Register.BAD_TT_EN = 1 and Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 144 Register.RX_STOMP_EN = 1 Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 145 Register.IDLE_IN_PKT_EN = 1 Port {0..17} Operations Port {0..17} Operations Port {0..17} Operations Register.PORT_PW_EN = 1 Register.PORT_INT_EN = 1 Register.PORT_LOG_EN = 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 146: Lane Event Notification

    C events that are enabled as described in I2C Events will be reported to the Error Log. For more information on how the Error Log can assert interrupts and send IDT port-writes, see Error Log Event Notification Programming Model. CPS-1848 User Manual...

  • Page 147: Jtag 1149.1 Event Notification (Revision A/B Only)

    Trace and Filter Event Notification When a packet matches at least one of the trace filters in a port, this event can cause an IDT port-write to be sent immediately. To cause an IDT port-write to be sent whenever there is a TRACE_MATCH_OCCURRED event, configure the following register bits: •...

  • Page 148: Port-Write Formats, Programming Model, And Generation

    RapidIO Specification (Rev. 2.1), Part 8, or as detected and captured using the IDT implementation-specific definition for errors that are not defined in Part 8 (such as lane-level errors). Two types of port-write packets can be generated by the CPS-1848: •...

  • Page 149: Figure 26: Type 1 Port-Write Packet Data Payload Format

    (for example if an LT error occurred simultaneously with a Configuration Block error, then the LT error should be reported first). The Error source column lists the potential sources of CPS-1848 errors. All other columns represent the values that are stored in the various fields in the port-write command definition.
  • Page 150 The “Implementation Specific” field represents a single lane-level error in the IDT specific error source and error code format, which is used in the Type 2 port-write packet payload associated with error logging. Bits [7:0] of the implementation specific...

  • Page 151: Table 56: Idt (Type 2) Port-Write Format

    50. The most significant byte of the “Implementation Specific” field is always 0. 6.3.9.3 IDT (Type 2) Port-Write Format IDT port-writes are sent by the Error Log. For more information on how the Error Log can generate interrupt and port-write notifications for events, see Error Log Event Notification Programming Model.

  • Page 152: Interrupt Notification

    Error Log Events Register (for more information, see Error Counter). • STOP_EN – Stop accepting more event reports into the Error Log, and optionally send an IDT port-write (for more information, see Error Management Stop). The CPS-1848 interrupt line is an active-low signal (for more information, see the CPS-1848 Datasheet).

  • Page 153: Table 57: Error Log Event Notification Examples

    Error Log Notification Examples The examples in Table 57 demonstrate how to trigger IDT port-writes and interrupts under various scenarios. This assumes that the events have been configured to be reported to the Error Log as described in Event Notification.

  • Page 154: Event Isolation

    OUTPUT_FAIL condition. These events are restricted to those documented in Extraction/Insertion. Use of any other events requires a device reset to recover the CPS-1848 after an OUTPUT_FAIL condition is detected. For more information on device resets, see Resets after Power-Up.

  • Page 155: Table 59: Additional Packet Discard Isolation Trigger Functions

    6. Event Management > Event Isolation The CPS-1848 supports additional packet discard isolation functions to reduce the congestion impact of error events (see Table 59). They are discussed in subsequent sections Table 59: Additional Packet Discard Isolation Trigger Functions Event...

  • Page 156: Fatal Link Response Timeout Isolation

    In the event of errors, the standard RapidIO error recovery function attempts to recover communication. If no response is received from the link partner, or if the CPS-1848 detects that ackID synchronization has been lost through reception of a link-response control symbol with an invalid ackID, then it is certain that communication cannot be re-established without software intervention.

  • Page 157: Received Retry Count Trigger Congestion Isolation

    Transmit Packet Dropped via CRC Retransmit Limit Isolation A packet can become corrupted as it passes through the CPS-1848 under rare circumstances. The packet’s corruption is detected by the link partner, which prevents the packet from being successfully transmitted by the CPS-1848.

  • Page 158: Software Controlled Isolation Functions

    • Packet received that references no route and is dropped These isolation functions enable software to prevent a CPS-1848 link partner from accessing all or part of the system, and to ensure that unauthorized access to a CPS-1848 link partner cannot occur.

  • Page 159: Physical Layer Events Clearing And Handling

    Port {0..17} Error Detect Transmission error - hardware error recovery. See Loss of AckID ackID CSR.PKT_ILL_ACKID = 0 Synchronization. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 160 If the packet latched is a request that requires a response, or a response packet, an endpoint should report a related logical layer response timeout either before or after this event has occurred. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 161 Register.RTE_ISSUE = 0, then error. Port {0..17} Error Detect CSR.IMP_SPEC_ERR = 0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 162 Register.BAD_TT = 0, then extremely rare transmission error. Port {0..17} Error Detect CSR.IMP_SPEC_ERR = 0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 163 Port {0..17} Error Detect Ignore the link request and continue normal operation. No CSR.IMP_SPEC_ERR = 0 hardware error recovery is used. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 164 Note that no packets are lost, and link state is retained. Register.LOA = 0, then Port {0..17} Error Detect CSR.IMP_SPEC_ERR = 0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 165 Port {0..17} Link Maintenance Response CSR This register is read-only and contains the information contained in the most recently received Link-Response by the specific port. When read, it returns this data. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 166 Device Reset and Control Register. 5. Clear up any error conditions resulting from the per-port reset (see HS-LP Controlled Recovery). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 167: Lane Event Clearing And Handling

    EEPROM checksum verification. I2C unexpected start/stop Aux Port Error Detect C slave was the target of an aborted transaction. Register.UNEXP_START_STOP CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 168: Jtag 1149.1 Events (Revision A/B Only)

    Register.BAD_PORT = 0 Multicast mask configuration error Configuration Block Error Detect Software or debug tool operation error. Register.BAD_MASK = 0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 169: Trace, Filter, And Pgc Events

    Register. This will clear the event. For more information on Packet Generation and Capture mode, see Packet Generation and Capture. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 170: I2C Interface

    C port can be thought of primarily as a control plane access point for the CPS-1848. An external device such as a host processor can use it to access the CPS-1848’s registers. The port can also be used by the CPS-1848 to load registers.

  • Page 171: Obtaining Configuration In Master Mode

    Obtaining Configuration in Master Mode If the Master mode signal, MM_N, is tied to GND, the CPS-1848 will attempt to load its configuration registers after the device reset sequence has completed. The CPS-1848 uses a 7-bit address of 1010[ID2][ID1][ID0] as the slave address of the device from which it will obtain its configuration.

  • Page 172: Table 67: Eeprom Register Address Map

    10.The last two bytes of the register map represent the CRC for the image (for more information, see Calculation). A tabular view of this definition is displayed below. When a port or lane configuration operation occurs within the EEPROM load, IDT recommends a subsequent port re-initialization or reset (for more information, see Port Reconfiguration Operations).

  • Page 173: Crc Calculation

    CPS-1848 to calculate the CRC differs from standard CRC algorithms in that the standard CRC algorithm normally pads the data by the width of the CRC as a final 16 bits of data to shift through the algorithm. The CPS-1848 does not do that, therefore, the standard CRC-16 algorithm will not generate a correct CRC.
  • Page 174 } else { crc[i] = crc[i-1]; bit_Pos_Mask >>= 1; for (i=15; i>=0; i--) { remainder |= (crc[i] << i); return (remainder); CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 175: Register Map Example

    Address = 0x15C >> 2 = 0x57 0x0008 0x00 Data for block 1 = 0x00600000 0x0009 0x60 0x000A 0x00 0x000B 0x00 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 176: I2C Master Mode Validation Debug

    C Master operation is controlled by configuration pins and device registers. For more information on I C Master configuration pins, see the CPS-1848 Datasheet. The CPS-1848 detects when an I C EEPROM image has an invalid CRC and sets the CHKSUM_FAIL bit of the I2C Master Status and Control Register.

  • Page 177: Slave Mode

    Slave Mode When the CPS-1848 is configured as a slave, its physical device address is defined by 10 external pins, ID[9:0]. The device can operate as either a 10-bit or 7-bit addressable device, as defined by an additional external pin called ADS. If the ADS pin is tied to V (3.3V), then the device operates as a 10-bit addressable device using ID[9:0].

  • Page 178: Figure 27: Bit Transfer On The I2C Bus

    Figure 27: Bit Transfer on the I C Bus Figure 28: START and STOP Signaling Figure 29: Data Transfer Figure 30: Acknowledgment CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 179: Figure 31: Master Addressing A Slave With A 7-Bit Address (Transfer Direction Is Not Changed)

    Figure 34: Master Addresses a Slave-Receiver with 10-bit Address Figure 35: Master Addresses a Slave Transmitter with 10-bit Address Figure 36: Combined Format – Master Addresses a Slave with 10-bit Address CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 180: Connecting To Standard-, Fast-, And Hs-Mode Devices As A Slave

    Note that the device address can be configured to any arbitrary value using the external address select pins. A slave address should also be used that is unique to each device on the bus. IDT also recommends to avoid using reserved addresses as specified in the I C Specification, such as CBUS addresses.

  • Page 181: Figure 38: Write Protocol With 10-Bit Slave Address (Ads Is 1)

    Address [17:10] Address [9:2] DATA DATA DATA DATA Input Data Input Data Input Data Input Data [31:24] [23:16] [15:8] [7:0] CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 182: Figure 41: Read Protocol With 7-Bit Slave Address (Ads Is 0)

    DATA DATA DATA DATA Device Output Data Output Data Output Data Output Data Address [6:0] [31:24] [23:16] [15:8] [7:0] CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 183: Jtag And Boundary Scan

    The chapter consists of two sections that describe Configuration Register Access: one for Revision A/B devices, and the other for Revision C. All other content is applicable to all revisions of the CPS-1848. For the full specifications, see the CPS-1848 Datasheet.

  • Page 184: Test Instructions

    Implemented per IEEE 1149.1-2001 Ex_Test Pulse Implemented per IEEE 1149.6 Ex_Test Train Implemented per IEEE 1149.6 Reserved Reserved Reserved Configuration Register IDT-specific Read and Write Access to Configuration Register space Access Reserved Reserved Reserved Reserved Bypass Implemented per IEEE 1149.1-2001 Device ID Register The JTAG Device ID register length is 32 bits wide.

  • Page 185: Initialization And Reset

    The CPS-1848’s JTAG functionality does not support register access when it is part of a chain of JTAG devices. The CPS-1848 must be the only device on the JTAG bus when its registers are accessed using JTAG.

  • Page 186: Configuration Register Access - Writes

    The CPS-1848 can report an unexpected termination of a register write using JTAG, and that JTAG sourced write data is not on a 32-bit boundary – this applies to writes to configuration registers. The error code for this report is defined in...

  • Page 187: Configuration Register Access (Revision C)

    8. JTAG and Boundary Scan > Configuration Register Access (Revision C) Configuration Register Access (Revision C) The system reset sequence for the CPS-1848 must be completed before a JTAG Configuration Register Access operation is started. In addition to the S-RIO and I C ports, the TAP Controller provides another interface to access any of the CPS-1848’s...

  • Page 188: Inter-Command Delay

    44. This figure shows the standard JTAG state machine that is implemented in the CPS-1848’s TAP Controller. Each inter-state arc is annotated with the TMS input value needed to traverse that arc. The CPS-1848 JTAG register access mechanism allows only one command to be in progress at a time (see Figure 44).

  • Page 189: Figure 44: Inter-Command Delay

    Table 74: Minimum Inter-Command Delay Minimum Inter-command Delay in Core Clock Rate (MHz) Run-Test/Idle (Microseconds) 312.5 156.25 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 190: Configuration Register Access - Writes

    ERROR, and Read data) State Read cmd Time Read cmd starts Read data and status of Read cmd captured Read cmd finishes CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 191: Jtag Clock Constraints

    All external I/Os support Boundary Scan testing as defined in IEEE 1149.1 and 1149.6. All input / output possibilities are tested including support for leakage testing, and providing users easy debugging by isolating the CPS-1848 from other devices on a PCB board.

  • Page 192: Reset And Initialization

    Power-Up Reset When power is applied to the CPS-1848, it is expected that the RST_N and TRST_N signals are asserted. This ensures that the RapidIO functionality, and the test port functionality, of the CPS-1848 have a deterministic state after reset.

  • Page 193: Initialization

    I C port, the JTAG port, or the default S-RIO port by a host processor. Any S-RIO link partner can also reset the CPS-1848 by sending a RapidIO reset request. For more information about RapidIO reset requests, see Reset Control Symbol Processing.

  • Page 194: Register Initialization

    9.2.3 Register Initialization To initialize the CPS-1848’s registers, complete the following steps in the order indicated: Steps 1a, 4d, and 5 are not required if register initialization is taking place through an EEPROM. 1. Disable a port using one of the following steps: a.

  • Page 195: Computing Timeout Values

    Each RapidIO device has a standard register that defines the response timeout for the physical level protocol, such as receipt of a link response control symbol after sending a link request. In the CPS-1848, this standard register is known as the...
  • Page 196 CPS-1848’s Final Buffer. It ensures both the request and response packets associated with a transaction that has timed out no longer exist in the system. Depending on the system traffic patterns, this can be much longer than what is defined in the...

  • Page 197: Registers

    RapidIO Specification (Rev. 2.1), Part 7: System and Device Interoperability Specification. This requirement suggests support for a number of RapidIO-specific registers. The CPS-1848 supports each of these registers except for the “Destination Operations CAR”. The RapidIO Specification (Rev. 2.1), Part 1: Input/Output Logical Specification defines this register as being applicable to switches only.

  • Page 198: Interpretation Of Reserved Register Bits

    Interpretation of Reserved Register Bits The CPS-1848 uses the S-RIO definition for the management of reserved register bits. This treatment is defined in Table 3-2 of the RapidIO Specification (Rev. 2.1), Part 3. Under the “Target Behavior” column, the expected return of the reserved bits of a register read is 0 for all S-RIO defined reserved registers.
  • Page 199 Port 7 – Starting Address 0x000240 Port 8 – Starting Address 0x000260 Port 9 – Starting Address 0x000280 Port 10 – Starting Address CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 200 Port 2 – Starting Address 0x001100 Port 3 – Starting Address 0x001140 Port 4 – Starting Address 0x001180 Port 5 – Starting Address CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 201 Lane {0..47} Status 3 CSR LANE_0_STATUS_3_CSR 0x002020 Lane {0..47} Status 4 CSR LANE_0_STATUS_4_CSR Lanes 1–47 For address offsets, see Lane {0..47} Status Base Addresses. IDT Specific Miscellaneous Registers 0x010070 Route Port Select Register RTE_PORT_SEL 0x010080 Multicast Route Select Register MCAST_RTE_SEL Per Port Registers 0x011000 Port {0..17} Watermarks Register...
  • Page 202 Port {0..17} Watermarks Register PORT_16_WM 0x011110 Port {0..17} Watermarks Register PORT_17_WM 0x01F000 Broadcast Watermarks Register BCAST_WM IDT Specific Event Notification Control Registers 0x020000 Aux Port Error Capture Enable Register AUX_PORT_ERR_CAPT_EN 0x020004 Aux Port Error Detect Register AUX_PORT_ERR_DET 0x020008 Configuration Block Error Capture Enable Register...
  • Page 203 Port 13 – Starting Address 0x1001E0 Port 14 – Starting Address 0x1001F0 Port 15 – Starting Address 0x100200 Port 16 – Starting Address CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 204 PORT_0_DEV_RTE_TABLE_{0..255} 0xE10400–E107FC Port {0..17} Domain Routing Table Register {0..255} PORT_0_DOM_RTE_TABLE_{0..255} Ports 1–17 For address offsets, see Base Addresses for IDT Specific Routing Table Registers Trace Comparison Values and Masks 0xE40000 Port {0..17} Trace 0 Value 0 Register PORT_0_TRACE_0_VAL_{0..4} 0xE40004 Port {0..17} Trace 0 Value 1 Register 0xE40008 Port {0..17} Trace 0 Value 2 Register...
  • Page 205 Port 14 – Starting Address 0xE40F00 Port 15 – Starting Address 0xE41000 Port 16 – Starting Address 0xE41100 Port 17 – Starting Address CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 206 Broadcast Trace 2 Mask 2 Register 0xE4F070 Broadcast Trace 2 Mask 3 Register 0xE4F074 Broadcast Trace 2 Mask 4 Register CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 207 Port {0..17} Multicast Mask Register {0..39} PORT_0_MCAST_MASK_0 Ports 1–17 For address offsets, see Implementation Specific Multicast Mask Base Addresses. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 208 Port {0..17} VC0 Received Packets Dropped Counter PORT_0_VC0_PKT_DROP_RX_CNTR Register 0xF40068 Port {0..17} VC0 Transmitted Packets Dropped Counter PORT_0_VC0_PKT_DROP_TX_CNTR Register CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 209 Error Log Match Register {0..7} LOG_MATCH_0 0xFD000C Error Log Match Register {0..7} LOG_MATCH_1 0xFD0010 Error Log Match Register {0..7} LOG_MATCH_2 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 210 Lane {0..47} Data Capture 0 Register LANE_0_DATA_CAPT_0 0xFF801C Lane {0..47} Data Capture 1 Register LANE_0_DATA_CAPT_1 0xFF8028 Lane {0..47} DFE 1 Register LANE_0_DFE_1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 211 Error Management Broadcast Registers 0xFFFF40 Broadcast Port Error Detect Register BCAST_PORT_ERR_DET 0xFFFF44 Broadcast Port Error Rate Enable Register BCAST_PORT_ERR_RATE_EN CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 212: Rapidio Capability Registers (Cars)

    0x0374 device. 16:31 VENDOR Device Vendor Identifier. This value is assigned by the RapidIO 0x0038 Trade Association for IDT. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 213: Device Information Car

    Device Revision Level. Same as the Version Level in the JTAG 0b010 deviceID register. 0b000 = Revision A/B 0b010 = Revision C CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 214: Assembly Identity Car

    Extended features pointer. This value points to the first entry in 0x0100 the extended features list, Port Maintenance Block Header Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 215: Processing Element Features Car

    1 = Device supports multiple external S-RIO ports 5:19 Reserved Reserved FLOW_ARB Flow arbitration support 0 = Not supported 1 = Supported CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 216 0b101 = 66 and 34-bit addresses 0b011 = 50 and 34-bit addresses 0b001 = 34-bit addresses All other values are reserved. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 217: Switch Port Information Car

    Reserved Reserved 16:23 TOTAL The total number of S-RIO ports that can be configured through 0x12 the CPS-1848’s registers. 24:31 PORT The port number from which the maintenance read operation 0x00 accessed this register. Note: When accessed through the DEVICE’s I2C or JTAG interface, the port number is not a predictable value.

  • Page 218: Source Operations Car

    Device supports an atomic increment operation 0 = Not supported ATOMIC_DECR Device supports an atomic decrement operation 0 = Not supported CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 219: Switch Multicast Support Car

    Bits Name Description Type Value SIMPLE Device supports the simple multicast model 0 = Not supported 1:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 220: Switch Route Table Entries Table Limit Car

    0:15 Reserved Reserved 16:31 MAX_DESTID The maximum number of configurable destIDs that are supported 0x00FF per port is 256. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 221: Switch Multicast Information Car

    40, or 0x0028. For Revision A/B, the reset value is based on 40 masks x 18 ports = 720 masks, or 0x02D0. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 222: Rapidio Control And Status Registers (Csrs)

    Component Tag for this device. This field is written by software. It is used for labeling and identifying port-write transactions to the host. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 223: Standard Route Table Entries Configuration Destid Select Csr

    Configuration Port Select CSR. 24:31 DESTID_LSB Defines the destID used to select an entry in the switch routing table. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 224: Standard Route Table Entry Configuration Port Select Csr

    Standard Route Table Entry Default Port CSR 0xDF = No Route, discard packets All other values are reserved and result in packet discard. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 225: Standard Route Table Entry Default Port Csr

    Value 0:23 Reserved Reserved 24:31 DEFAULT_PORT This defines the device’s default output port (for more information, see Packet Routing). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 226: Multicast Mask Port Csr

    Write_to_Verify command. 0 = Port not enabled in the multicast mask 1 = Port is enabled in the multicast mask CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 227: Multicast Association Selection Csr

    8:15 DESTID_LSB Selects a destID for an association operation 16:31 MASK Selects the multicast mask number for an association CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 228: Multicast Association Operations Csr

    STATUS Contains the result of the last write to verify command 0 = No association 1 = Association present CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 229: Lp-Serial Extended Features Registers With Software Assisted Error Recovery

    Extended features pointer. This value points to the next entry in 0x0600 the extended features list, VC Register Block Header Register. 16:31 EF_ID Hard Wired Extended Features ID 0x0009 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 230: Port Link Timeout Control Csr

    Name Description Type Value Reserved Reserved DISCV 0 = Device not discovered 1 = Device discovered 3:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 231: Port {0

    Address 0x000140 0x000160 0x000180 0x0001A0 0x0001C0 0x0001E0 0x000200 0x000220 0x000240 0x000260 0x000280 0x0002A0 0x0002C0 0x0002E0 0x000300 0x000320 0x000340 0x000360 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 232: Port {0

    Note (Revision A/B only): The Port {0..17} Error and Status CSR[OUTPUT_FAIL] bit must be clear and remain clear before any link request can be sent. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 233: Port {0

    Link status field from the Link-Response control symbol 0b00000 0b00010 = Error 0b00100 = Retry-stopped 0b00101 = Error-stopped 0b10000 = OK All others are Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 234: Port {0

    Note: Bit 26 is available only when IDLE2 is in use on the link. Note: This field is cleared when PORT_DIS is set to 1 in the Port {0..17} Control 1 CSR. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 235: Port {0

    1 = IDLE2 (RapidIO Gen2) is active Reserved Reserved. Bit 4 is defined as FLOW_CTL_MODE in the RapidIO Specification (Rev. 2.1). For more information on the CPS-1848’s implementation of this bit, see RX_FC in the Port {0..17} Status and Control Register.
  • Page 236 Port-Write. Once set, this bit remains set until written with a 1 to clear. PORT_UNAVL 0 = This port is always available CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 237 Final Buffer, including maintenance packet responses. To recover, the port must send a link-request/input status control symbol and receive a response. This will clear the PORT_ERR and packet drop condition. The CPS-1848 will send a link-request/input-status control symbol when either of the following occurs:...

  • Page 238: Port {0

    0b011 = 2x lane port All others are reserved Note: 1x with redundancy is not considered a 2x port – it is a 1x port. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 239 Control symbols are not affected and are handled normally. 1 = Port is enabled to respond to any packets CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 240 This bit is used with the STOP_ON_PORT_FAIL_ENC_EN bit to force certain behavior when the Error Rate Failed Threshold has been met (for more information, see Table 58). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 241 PORT_TYPE This indicates the port type 1 = Serial port CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 242: Port {0

    CS field marker and handle commands carried in the CS field as if they were active lanes. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 243 • Quadrant 0 / QCFG[1:0] = 0b11: Should modify offsets Port 0, 12, and 16 of Port {0..17} Control 2 CSR 30:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 244: Virtual Channel Extended Features Block Registers

    16:31 EF_ID Hard Wired Extended Features ID 0x000A a. This register is not supported by the CPS-1848; however, the EF_PTR value is valid for the device. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 245: Error Management Extensions Block Registers

    Extended features pointer. This value points to the next entry in 0x2000 the extended features list, Lane Status Block Header Register. 16:31 EF_ID Hard Wired Extended Features ID 0x0007 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 246: Logical/Transport Layer Error Detect Csr

    1 = Received an unsupported transaction. Received a port-write with hop count of 0. 10:30 Reserved Reserved IMP_SPEC_ERR 1 = Detected an IDT implementation-specific error (see also Logical/Transport Layer Control Capture CSR) CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 247: Logical/Transport Layer Error Enable Csr

    UNSUP_TRAN_EN 1 = Enable the capture of unsupported transactions (port-writes with a hop count of 0). 10:30 Reserved Reserved IMP_SPEC_ERR_ 1 = Enable capture of IDT implementation-specific errors (see also Logical/Transport Layer Control Capture CSR) CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 248: Logical/Transport Layer Deviceid Capture Csr

    SOURCEID_MSB Most significant byte of the sourceID associated with the error. 24:31 SOURCEID The sourceID associated with the error. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 249: Logical/Transport Layer Control Capture Csr

    • A maintenance payload size does not match the configured size (for example, a payload size of 64 bytes requires 64 bytes of payload). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 250 (0b0000) or a write request (0b0001). All other values Reserved a. Errors are detected in Maintenance packets with a hop count of 0. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 251: Port-Write Target Deviceid Csr

    Large transport. deviceID size to use for a port-write: 0 = Small transport 1 = Large transport 17:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 252: Packet Time To Live Csr

    Final Buffer. TTL is disabled if this field is 0. To set a TTL value use the following formula: TTL x 1.6 us. 16:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 253: Port Error Management Register Base Addresses

    Address 0x001040 0x001080 0x0010C0 0x001100 0x001140 0x001180 0x0011C0 0x001200 0x001240 0x001280 0x0012C0 0x001300 0x001340 0x001380 0x0013C0 0x001400 0x001440 0x001480 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 254: Port {0

    10. Registers > Error Management Extensions Block Registers 10.7.9 Port {0..17} Error Detect CSR This register indicates Standard physical layer errors except IMP_SPEC_ERR, which indicates IDT implementation specific errors. The broadcast version of this register is Broadcast Port Error Detect Register, which will write the same value to all ports.
  • Page 255 1 = Detected an an unexpected packet or retry control symbol. Note: This does not include packet-not-accept control symbols. LINK_TIMEOUT 1 = Detected a link timeout error CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 256: Port {0

    1 = Enable the capture and counting of the corresponding error in the Port {0..17} Error Detect CSR. 17:25 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 257 LINK_TIMEOUT_EN 1 = Enable the capture and counting of the corresponding error in the Port {0..17} Error Detect CSR. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 258: Port {0

    1 = The Capture registers contain valid information. For information on what is captured for which event, see Physical Layer Events. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 259: Port {0

    Bit 22 indicates the type of timeout error: 0 = Package Acknowledge timeout 1 = Link-Response timeout CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 260: Port {0

    CAPT_2 16:23 CAPT_2 24:31 CAPT_2 Reset Bits Name Description Type Value 0:31 CAPT_2 Bytes 8:11 of the Packet Header CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 261: Port {0

    CAPT_3 16:23 CAPT_3 24:31 CAPT_3 Reset Bits Name Description Type Value 0:31 CAPT_3 Bytes 12:15 of the Packet Header CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 262: Port {0

    PEAK_ERR_RATE The peak value attained by the error rate counter. The primary intention for the writes is to clear the register (a write value of 0x00). This value does not clear on read. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 263 Note: IDT encourages caution when writing to this counter since the error threshold function is driven by it (if enabled). The primary intention for the writes is to clear the register (a write value of 0x00).

  • Page 264: Port {0

    0x01 = Threshold value of 1 0x02 = Threshold value of 2 0xFF = Threshold value of 255 16:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 265: Lane Status Registers

    0x002110 0x002130 0x002150 0x002170 0x002190 0x0021B0 0x0021D0 0x0021F0 0x002210 0x002230 0x002250 0x002270 0x002290 0x0022B0 0x0022D0 0x0022F0 0x002310 0x002330 0x002350 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 266 0x0023B0 0x0023D0 0x0023F0 0x002410 0x002430 0x002450 0x002470 0x002490 0x0024B0 0x0024D0 0x0024F0 0x002510 0x002530 0x002550 0x002570 0x002590 0x0025B0 0x0025D0 0x0025F0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 267: Lane Status Block Header Register

    A value of 0x0000 indicates that this is the last entry. 16:31 EF_ID Hard Wired Extended Features ID 0x000D CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 268: Lane {0

    0 = Receiver input not inverted 1 = Receiver input inverted RX_TRAINED 0 = Receiver not trained 1 = Receiver trained CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 269 0b100 = Lane status CSRs 2:5 are implemented 0b101 = Lane status CSRs 2:6 are implemented 0b110 = Lane status CSRs 2:7 are implemented 0b111 = Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 270: Lane {0

    1 = Values have changed LP_RX_TYPE Link Partner Receiver Type 0 = Short run 1 = Medium or long run CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 271 0b11 = Tap at intermediate emphasis LP_SCRAM Link Partner Scrambling/Descrambling 0 = Disable 1 = Enable 17:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 272: Lane {0

    26:31 POS1_ON_RST Value to set the +1 (post) tap to when a reset pre-emphasis command in an IDLE2 sequence is received. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 273: Lane {0

    1 = Supported GBAUD_6p25 0 = Not supported 1 = Supported GBAUD_1p25_EN 0 = Not supported 1 = Supported CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 274 Local Transmitter Pre-emphasis Tap Control. Current value of the -1 (pre) tap 26:31 POS1_TAP Local Transmitter Post Tap Control. Current value of the +1 (post) CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 275: Lane {0

    RESH reception of a valid RR sequence. The default value is 5000 character groups. Note: Do not write 0 to this field. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 276: Idt Specific Miscellaneous Registers

    10. Registers > IDT Specific Miscellaneous Registers 10.9 IDT Specific Miscellaneous Registers 10.9.1 Route Port Select Register Register Name: RTE_PORT_SEL Register Offset: 0x010070 Reset Value: 0x0000_0000 Bits 00:07 Reserved 08:15 Reserved 16:23 Reserved 24:31 Reserved PORT Reset Bits Name Description...

  • Page 277: Multicast Route Select Register

    10. Registers > IDT Specific Miscellaneous Registers 10.9.2 Multicast Route Select Register Register Name: MCAST_RTE_SEL Register Offset: 0x010080 Reset Value: 0x0000_0000 Bits 00:07 Reserved 08:15 Reserved 16:23 Reserved 24:31 Reserved PORT Reset Bits Name Description Type Value 0:26 Reserved Reserved...

  • Page 278: Port N Watermarks Base Addresses

    10. Registers > IDT Specific Miscellaneous Registers 10.9.3 Port n Watermarks Base Addresses Port Offset from Base 0x011000 0x011010 0x011020 0x011030 0x011040 0x011050 0x011060 0x011070 0x011080 0x011090 0x0110A0 0x0110B0 0x0110C0 0x0110D0 0x0110E0 0x0110F0 0x011100 0x011110 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 279: Port {0

    10. Registers > IDT Specific Miscellaneous Registers 10.9.4 Port {0..17} Watermarks Register The watermark values in this register should be set based on the buffer size of the link partner and the required traffic characteristics for packets of each priority. For more information, see...

  • Page 280: Broadcast Watermarks Register

    10. Registers > IDT Specific Miscellaneous Registers 10.9.5 Broadcast Watermarks Register The per-port version of this register is Port {0..17} Watermarks Register. Register Name: BCAST_WM Register Offset: 0x01F000 Reset Value: 0x0000_0000 Bits 00:07 Reserved 08:15 Reserved PRIO_2 16:23 PRIO_2 PRIO_1...

  • Page 281: Idt Specific Event Notification Control Registers

    The CPS-1848 supports a number of RapidIO related implementation-specific event detection/notification functions, as well as event detection/notification for the JTAG (CPS-1848 Revision A/B only) and I2C interfaces on the device. These registers report the status of and contain control values for this functionality.

  • Page 282: Aux Port Error Detect Register

    0 = No error 1 = An unexpected termination of write data to registers was detected if serial data input is not 32-bit aligned. Note: This bit is applicable to CPS-1848 Revision A/B only. I2C_CHKSUM_ERR 0 = No error 1 = In Master mode, at the end of a configuration image update, the checksum value in the image did not match the calculated value.

  • Page 283: Configuration Block Error Capture Enable Register

    10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value I2C_ACK_ERR 0 = No error 1 = An acknowledgement was expected but not received. This error can occur in Master or Slave mode. If the error occurs in Master mode, the data transfer will be terminated and the error will be captured.

  • Page 284: Configuration Block Error Detect Register

    This is also triggered when the Multicast Mask Port CSR is written to that contains an invalid egress port number. An attempt has been made to configure the CPS-1848 to use an invalid trace port. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 285 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value BAD_MASK 0 = No error 1 = A direct write to a route table has been attempted with an invalid mask number. A NO_RTE will be written into the route table instead.

  • Page 286: Impl. Specific Logical/Transport Layer Address Capture Register

    10. Registers > IDT Specific Event Notification Control Registers 10.10.5 Impl. Specific Logical/Transport Layer Address Capture Register The contents of this register are unlocked simultaneously with the values in the Logical/Transport Layer Error Detect CSR. Register Name: IMPL_SPEC_LT_ADDR_CAPT Register Offset: 0x021014...

  • Page 287: Logical/Transport Layer Error Report Enable Register

    10. Registers > IDT Specific Event Notification Control Registers 10.10.6 Logical/Transport Layer Error Report Enable Register The same settings should be used in the Logical/Transport Layer Error Enable CSR and this register; otherwise, detected events may not be reported, or port-writes/interrupts may be sent/asserted with no indication of the cause.

  • Page 288: Port {0

    10. Registers > IDT Specific Event Notification Control Registers 10.10.7 Port {0..17} Error Report Enable Base Addresses Port Base Address 0x031044 0x031084 0x0310C4 0x031104 0x031144 0x031184 0x0311C4 0x031204 0x031244 0x031284 0x0312C4 0x031304 0x031344 0x031384 0x0313C4 0x031404 0x031444 0x031484 CPS-1848 User Manual...

  • Page 289: Port {0

    10. Registers > IDT Specific Event Notification Control Registers 10.10.8 Port {0..17} Error Report Enable Register Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log. The broadcast version of this register is Broadcast Port Error Report Enable Register.
  • Page 290 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value IDLE1_ERR_EN 1 = Enable the reporting of the corresponding error in the Port {0..17} Error Detect CSR. 17:25 Reserved Reserved LR_ACKID_ILL_EN 1 = Enable the reporting of the corresponding error in the Port {0..17} Error Detect...

  • Page 291: Port {0

    10. Registers > IDT Specific Event Notification Control Registers 10.10.9 Port {0..17} Implementation Specific Error Report Enable Register This register allows the user to define when an implementation specific error is captured at a finer granularity. Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log.
  • Page 292 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value TX_DROP_EN 1 = Enable reporting of the corresponding error in the Port {0..17} Implementation Specific Error Detect Register MANY_RETRY_EN 1 = Enable reporting of the corresponding error in the Port {0..17}...
  • Page 293 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value IDLE_IN_PKT_EN 1 = Enable reporting of the corresponding error in the Port {0..17} Implementation Specific Error Detect Register LOA_EN 1 = Enable reporting of the corresponding error in the Port {0..17}...

  • Page 294: Broadcast Port Error Report Enable Register

    10. Registers > IDT Specific Event Notification Control Registers 10.10.10 Broadcast Port Error Report Enable Register Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log. The per-port version of this register is Port {0..17} Error Report Enable...
  • Page 295 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value LR_ACKID_ILL_EN 1 = Enable the reporting of errors to the corresponding bit in the Port {0..17} Error Detect CSR. PRTCL_ERR_EN 1 = Enable the reporting of errors to the corresponding bit in the Port {0..17} Error Detect...

  • Page 296: Broadcast Port Implementation Specific Error Report Enable Register

    10. Registers > IDT Specific Event Notification Control Registers 10.10.11 Broadcast Port Implementation Specific Error Report Enable Register Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log. The per-port version of this register is Port {0..17} Implementation Specific Error Report Enable...
  • Page 297 10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value MANY_RETRY_EN 1 = Enable reporting of the corresponding error in the Broadcast Port Implementation Specific Error Detect Register RX_DROP_EN 1 = Enable reporting of the corresponding error in the...

  • Page 298: Lane N Error Report Enable Base Addresses

    10. Registers > IDT Specific Event Notification Control Registers (Continued) Reset Bits Name Description Type Value BAD_CTL_EN 1 = Enable reporting of the corresponding error in the Broadcast Port Implementation Specific Error Detect Register REORDER_EN 1 = Enable reporting of the corresponding error in the...
  • Page 299 10. Registers > IDT Specific Event Notification Control Registers Lane Base Address 0x039910 0x039A10 0x039B10 0x039C10 0x039D10 0x039E10 0x039F10 0x03A010 0x03A110 0x03A210 0x03A310 0x03A410 0x03A510 0x03A610 0x03A710 0x03A810 0x03A910 0x03AA10 0x03AB10 0x03AC10 0x03AD10 0x03AE10 0x03AF10 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 300: Lane {0

    10. Registers > IDT Specific Event Notification Control Registers 10.10.13 Lane {0..47} Error Report Enable Register Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log. For base address information, see Lane n Error Report Enable Base Addresses.

  • Page 301: Broadcast Lane Error Report Enable Register

    10. Registers > IDT Specific Event Notification Control Registers 10.10.14 Broadcast Lane Error Report Enable Register Each bit in this register can enable/disable reporting of an error type using interrupt, port-write, and error log. The per-port version of this register is Lane {0..47} Error Report Enable...

  • Page 302: Packet Generation And Capture Registers

    Address 0x100100 0x100110 0x100120 0x100130 0x100140 0x100150 0x100160 0x100170 0x100180 0x100190 0x1001A0 0x1001B0 0x1001C0 0x1001D0 0x1001E0 0x1001F0 0x100200 0x100210 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 303: Port {0

    0b0000010000 = VC0 PRI 2 CRF 0 0b0000100000 = VC0 PRI 2 CRF 1 0b0001000000 = VC0 PRI 3 CRF 0 0b0010000000 = VC0 PRI 3 CRF 1 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 304: Port {0

    This field is used to write packets to the Start port, and to retrieve packets from the End port. For more information, see Packet Generation and Capture. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 305: Idt Specific Routing Table Registers

    10. Registers > IDT Specific Routing Table Registers 10.12 IDT Specific Routing Table Registers The CPS-1848 supports a memory-mapped model for routing table registers. The “broadcast” versions of these registers update routing tables for all ports. The “per-port” versions of these registers are port specific.

  • Page 306: Broadcast Device Route Table Register {0

    10. Registers > IDT Specific Routing Table Registers 10.12.2 Broadcast Device Route Table Register {0..255} This is the broadcast device routing register for destID 0–255. The per-port version of this register is Port {0..17} Device Route Table Register {0..255}. Register Name: BCAST_DEV_RTE_TABLE_{0..255}...

  • Page 307: Broadcast Domain Route Table Register {0

    10. Registers > IDT Specific Routing Table Registers 10.12.3 Broadcast Domain Route Table Register {0..255} This is the broadcast domain routing register for destID 0–255. The per-port version of this register is Port {0..17} Domain Routing Table Register {0..255}. Register Name: BCAST_DOM_RTE_TABLE_{0..255}...

  • Page 308: Port {0

    10. Registers > IDT Specific Routing Table Registers 10.12.4 Port {0..17} Device Route Table Register {0..255} This is the port-specific device routing register for destID 0–255. The broadcast version of this register is Broadcast Device Route Table Register {0..255} Register Name: Register Offset: PORT_{0..17}_DEV_RTE_TABLE_{0..255}...

  • Page 309: Port {0

    10. Registers > IDT Specific Routing Table Registers 10.12.5 Port {0..17} Domain Routing Table Register {0..255} This is the port-specific domain routing register for destID 0–255. The broadcast version of this register is Port {0..17} Domain Routing Table Register {0..255}...

  • Page 310: Trace Comparison Values And Masks Registers

    Offset Address 0xE40000 0xE40100 0xE40200 0xE40300 0xE40400 0xE40500 0xE40600 0xE40700 0xE40800 0xE40900 0xE40A00 0xE40B00 0xE40C00 0xE40D00 0xE40E00 0xE40F00 0xE41000 0xE41100 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 311: Port {0

    Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 312: Port {0

    Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 313: Port {0

    Bit 0 is a mask for the first comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 314: Port {0

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 315: Port {0

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 316: Port {0

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 317: Port {0

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 318: Port {0

    Bit 0 is a mask for the first comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 319: Port {0

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 320: Port {0

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 321: Port {0

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 322: Port {0

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 323: Port {0

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 324: Port {0

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 325: Port {0

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 326: Port {0

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 327: Port {0

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 0 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 328: Port {0

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 329: Port {0

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 330: Port {0

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 331: Broadcast Trace 0 Value 0 Register

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 332: Broadcast Trace 0 Value 2 Register

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 333: Broadcast Trace 0 Value 4 Register

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 334: Broadcast Trace 0 Mask 1 Register

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 335: Broadcast Trace 0 Mask 3 Register

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 336: Broadcast Trace 1 Value 0 Register

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 337: Broadcast Trace 1 Value 2 Register

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 338: Broadcast Trace 1 Value 4 Register

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 339: Broadcast Trace 1 Mask 1 Register

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 340: Broadcast Trace 1 Mask 3 Register

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 341: Broadcast Trace 2 Value 0 Register

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 342: Broadcast Trace 2 Value 2 Register

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 343: Broadcast Trace 2 Value 4 Register

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 344: Broadcast Trace 2 Mask 1 Register

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 345: Broadcast Trace 2 Mask 3 Register

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 346: Broadcast Trace 3 Value 0 Register

    32 bits received in the packet. Bit 0 is compared to the 33rd packet bit Bit 31 is compared to the 64th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 347: Broadcast Trace 3 Value 2 Register

    32 bits received in the packet. Bit 0 is compared to the 97th packet bit Bit 31 is compared to the 128th packet bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 348: Broadcast Trace 3 Value 4 Register

    Bit 0 is a mask for the 1st comparison value bit Bit 31 is a mask for the 32nd comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 349: Broadcast Trace 3 Mask 1 Register

    Bit 0 is a mask for the 65th comparison bit Bit 31 is a mask for the 96th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 350: Broadcast Trace 3 Mask 3 Register

    Bit 0 is a mask for the 129th comparison bit Bit 31 is a mask for the 160th comparison bit CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 351: Global Device Configuration Registers

    Generate a port-write if a RapidIO Specification (Rev. 2.1), Part 8 Logical/Transport error is detected 0 = Do not generate 1 = Generate 7:14 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 352 Defines action when an S-RIO reset request is received 0 = Reset device 1 = Reset the port that received the reset request CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 353: Configuration Block Error Report Register

    0 = Disable error reporting to Error Log due to Configuration Block error 1 = Enable error reporting to Error Log due to Configuration Block error CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 354: Aux Port Error Report Enable Register

    JTAG_LOG_EN JTAG Error Logging/Reporting to the Error Log 0 = Disable 1 = Enable Note: This bit is applicable to CPS-1848 Revision A/B only. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 355: Rapidio Domain Register

    10. Registers > Global Device Configuration Registers 10.14.4 RapidIO Domain Register This register defines the CPS-1848’s domain. Register Name: RIO_DOMAIN Register Offset: 0xF20020 Reset Value: 0x0000_0000 Bits 00:07 Reserved 08:15 Reserved 16:23 Reserved 24:31 DOMAIN Reset Bits Name Description Type...

  • Page 356: Port-Write Control Register

    0b11. S-RIO Critical Request Flow information to be used for port-writes. The recommended setting is 1. 19:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 357: Rapidio Assembly Identification Car Override

    Value 0:15 Reserved Reserved 16:31 ASSY_REV This value is assigned to the ASSY_REV field of the Assembly Information CAR. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 358: Device Soft Reset Register

    1 = The I2C Block has encountered a condition that required it to initiate a port-write. Once set, this bit remains set until written with a 1 to clear. Valid only if I2C port-writes are enabled. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 359 I2C address to use for the EEPROM for commanded master mode. Note: The initial value of this field is determined by the setting of the ID[9:0] external pins. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 360: I2C Master Status And Control Register

    1 = Initiate the start of an I2C EEPROM read. 16:31 EPROM_START_A EEPROM address offset where I2C Master read operation should occur CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 361: Jtag Control Register (Revision A/B)

    10. Registers > Global Device Configuration Registers 10.14.11 JTAG Control Register (Revision A/B) This register is applicable to CPS-1848 Revision A/B only. Register Name: JTAG_CTL Register Offset: 0xF2005C Reset Value: 0x0000_0000 Bits 00:07 Reserved 08:15 Reserved 16:23 Reserved 24:31 Reserved...

  • Page 362: External Mces Trigger Counter Register

    0 that have been dropped by the maintenance block. Note: For Revision C, maintenance packets that are dropped due to “no route” are not counted by this register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 363: Switch Parameters 1 Register

    1 = Single buffer reservation mode. Minimum of one page is allocated to each priority (1, 2, 3) in input, crosspoint and final buffers. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 364 2000 (0x7D0). The default value of these fields is 1000 (0x3E8). 27:31 INPUT_STARV_LI Threshold value for Input Scheduler Starvation Prevention. 0x1F CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 365: Switch Parameters 2 Register

    16:31 OUTPUT_CREDIT Maximum output scheduler credit value. Reset if reached. 0x3E8 _MAX Note: This is a positive credit value. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 366: Quadrant Configuration Register

    10.14.16 Quadrant Configuration Register This register configures the port width and lane to port mapping of the CPS-1848’s quadrants. The following register table shows the port width configuration based on the value of the QUADx_CFG field. For lane to port mapping based on the value...
  • Page 367 0b11 = 2 by 4x, 1 by 2x, 2 by 1x ports Note: The initial value of this field is determined by the setting of the QCFG[1:0] external pins. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 368: Device Reset And Control Register

    JTAG logic. PORT_SEL is not active for this reset, but PLL_SEL indicates that PLL resets can also be triggered with this reset. Note: This reset requires the CPS-1848 to be quiescent (it is not transmitting or receiving packets). 2:13...

  • Page 369: Implementation Specific Multicast Mask Registers

    0xF30000 0xF38000 0xF38100 0xF38200 0xF38300 0xF38400 0xF38500 0xF38600 0xF38700 0xF38800 0xF38900 0xF38A00 0xF38B00 0xF38C00 0xF38D00 0xF38E00 0xF38F00 0xF39000 0xF39100 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 370: Broadcast Multicast Mask Register {0

    0 = Port is not included in Multicast Mask Number m for port_num n 1 = Port is included in Multicast Mask Number m for port_num n CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 371: Port {0

    0 = Port is not included in Multicast Mask Number m for port_num n 1 = Port is included in Multicast Mask Number m for port_num n CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 372: Port Function Registers

    Offset Address 0xF40000 0xF40100 0xF40200 0xF40300 0xF40400 0xF40500 0xF40600 0xF40700 0xF40800 0xF40900 0xF40A00 0xF40B00 0xF40C00 0xF40D00 0xF40E00 0xF40F00 0xF41000 0xF41100 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 373: Port {0

    Reserved FORCE_REINIT 1 = Force the initialization state machine back to the silent state. This causes the loss of the link. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 374 0 = Do not generate a port-write on a trace match 1 = Generate a port-write on a trace match Note: This bit is active only if PORT_LOG_EN is set to 1. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 375 CRC_RETX_LIMIT 0b000 = No CRC retransmission limit 0b000 0b001–0b111 = The number of CRC retransmissions allowed before packet is dropped. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 376: Port {0

    UNSOL_LR 1 = Received an unsolicited Link-Response UNEXP_ACKID 1 = Received an acknowledge control symbol with an unexpected ackID CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 377 STOMP_TO 1 = Transmitted a STOMP control symbol but the link partner did not reply with a packet retry (or a packet NACK) CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 378 REORDER 1 = The port detected that lanes were reordered during port initialization because of information in IDLE2 sequence. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 379: Port {0

    PNA_RETRY_EN 1 = Enable the capture of the corresponding error in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 380 UNEXP_EOP_EN 1 = Enable the capture of the corresponding error in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 381 REORDER_EN 1 = Enable the capture of the corresponding error in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 382: Port {0

    A saturating count of packet not acknowledgements (NACKs) transmitted by the port. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 383: Port {0

    (includes retransmissions) for VC0 packets. Counted on EOP. Excludes partially transmitted packets. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 384: Port {0

    Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 385: Port {0

    Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 386: Port {0

    Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 387: Port {0

    Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 388: Port {0

    A saturating count of packet not acknowledgements received by the port for all VCs. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 389: Port {0

    Crosspoint buffers in a switch port column. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 390: Port {0

    8–21 of the packet. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 391: Port {0

    0 = Generation of maintenance port-write packets (for trace matches only) is enabled 1 = Generation of maintenance port-write packets (for trace matches only) is disabled CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 392: Port {0

    Note: For link speeds of 5 Gbaud or higher, 0b001 or higher should be used as recommended by the RapidIO Specification (Rev. 2.1). CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 393: Port {0

    0s. For more information, see Multicast Programming Model. Note: This counter works only when the CPS-1848 is configured in Store-and-forward mode (CUT_THRU_EN is set to 0 in Device Control 1 Register).

  • Page 394: Port {0

    A saturating count of VC0 packets that have been dropped by the port’s transmit logic. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 395: Port {0

    CRC LIMIT events. Note: To enable this counter, set the Port {0..17} Operations Register[CNTRS_EN] bit. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 396: Port {0

    Bits Name Description Type Value 0:15 RETRY_LIM Threshold value to trigger congested link partner recovery 0xFFFF 16:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 397: Port {0

    0 = Disable the congestion retry counter 1 = Enable the congestion retry counter RX_FC 0 = Transmitter-controlled flow control 1 = Receiver-controlled flow control CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 398: Broadcast Port Operations Register

    1 = Disable Note: Before changing this field value, see Port Reconfiguration Operations for the correct procedure to follow. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 399 28:30 CRC_RETX_LIMIT 0b000 = No retransmission limit 0b000 0b001–0b111 = The number of retransmissions allowed before packet is dropped. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 400 10. Registers > Port Function Registers (Continued) Reset Bits Name Description Type Value Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 401: Broadcast Port Implementation Specific Error Detect Register

    NACKs at the Part 8 level), and then re-enable the counting of all other NACKs with this bit. UNSOL_LR 1 = Received an unexpected Link-Response CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 402 1 = Received a retry control symbol with a valid ackID RETRY_ACKID 1 = Received a retry control symbol with an unexpected ackID CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 403 REORDER 1 = The port detected that lanes were reordered during port initialization because of information in the IDLE2 sequence CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 404: Broadcast Port Implementation Specific Error Rate Enable Register

    RTE_ISSUE_EN 1 = Enable the capture of the corresponding event in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 405 UNEXP_STOMP_ 1 = Enable the capture of the corresponding event in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 406 REORDER_EN 1 = Enable the capture of the corresponding event in the Port {0..17} Implementation Specific Error Detect Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 407: Implementation Specific Error Logging Registers

    ALL_FLAG_STOP 0 = When all error flags are asserted, do not stop the Error Management block 1 = When all error flags are asserted, stop the error log function and generate a port-write packet CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 408: Error Log Data Register

    Base Address Associated Registers 0xFD0008 LOG_MATCH_0 0xFD000C LOG_MATCH_1 0xFD0010 LOG_MATCH_2 0xFD0014 LOG_MATCH_3 0xFD0018 LOG_MATCH_4 0xFD001C LOG_MATCH_5 0xFD0020 LOG_MATCH_6 0xFD0024 LOG_MATCH_7 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 409: Error Log Match Register {0

    Error Group. Most significant 4 bits of Event Code. 28:31 ERR_NUM Error Number. Least significant 4 bits of Event Code. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 410: Error Log Match Status Register

    Error Log Match Register {0..7}). This field can be reset by FLAG_RESET in the Error Log Control 2 Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 411: Error Log Events Register

    CNT is reset when the Error Manager is reset, or CNT_RESET is set in the Error Log Control 2 Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 412: Error Log Control 2 Register

    0:25 Reserved Reserved STOP_EM 0 = Enable error management 1 = Stop error management. Disable all IDT maintenance packet port-writes, including those resulting from trace matches. Note: When set to 1, it does not affect standard S-RIO port-writes. MAINT_PKT_DIS 0 = Generation of the maintenance packets (for error...

  • Page 413: Pll Registers

    10.19.1 PLL Register Base Addresses PLL Domain Address 0xFF0000 0xFF0010 0xFF0020 0xFF0030 0xFF0040 0xFF0050 0xFF0060 0xFF0070 0xFF0080 0xFF0090 0xFF00A0 0xFF00B0 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 414: Pll {0

    For base address information, see Registers. The broadcast version of this register is Broadcast PLL Control Register. When a port or lane configuration operation occurs, IDT recommends a subsequent port re-initialization or reset (for more information, see Port Reconfiguration Operations).

  • Page 415: Pll {0

    Name Description Type Value 0:29 Reserved Reserved PLL_AUTO_RESE 1 = Pulse occurred on PLL auto reset output Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 416: Broadcast Pll Control Register

    Note: The initial value of this field is determined by the setting of the SPD[2] external pin. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 417: Lane Control Registers

    0xFF8900 0xFF8A00 0xFF8B00 0xFF8C00 0xFF8D00 0xFF8E00 0xFF8F00 0xFF9000 0xFF9100 0xFF9200 0xFF9300 0xFF9400 0xFF9500 0xFF9600 0xFF9700 0xFF9800 0xFF9900 0xFF9A00 0xFF9B00 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 418 0xFF9D00 0xFF9E00 0xFF9F00 0xFFA000 0xFFA100 0xFFA200 0xFFA300 0xFFA400 0xFFA500 0xFFA600 0xFFA700 0xFFA800 0xFFA900 0xFFAA00 0xFFAB00 0xFFAC00 0xFFAD00 0xFFAE00 0xFFAF00 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 419: Lane {0

    0b1001–1111 = Reserved Note: For 8-bit mode, 0b0110, 0b0111, and 0b1000 are supported for PRBS generation only. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 420 Loopback enable at the 8-bit boundary within Lane n 0 = Disable 1 = Enable For more information, see 8-bit Loopback Mode. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 421 SPD[1:0] external pins. Note: Before changing this field value, see Port Reconfiguration Operations for the correct procedure to follow. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 422 Note: Changing the state of the LANE_DIS bit will require a re-initialization or reset. Before changing this field value, see Port Reconfiguration Operations for the correct procedure to follow. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 423: Lane {0

    0 must be set to 1 to guarantee proper pseudo-random generation. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 424: Lane {0

    Value 0:22 Reserved Reserved PRBS_ERR 1 = A PRBS error occurred 24:31 PRBS_ERR_CNT PRBS error counter for this lane. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 425: Lane {0

    LANE_RDY 1 = Lane ready was lost but sync remained high. LANE_SYNC 1 = Lane sync was lost. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 426: Lane {0

    0 = Disable 1 = Enable capturing of loss of receiver descrambler synchronization while receiving scrambled control symbol and packet data. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 427 1 = Enable capturing that Lane sync was lost. a. When a bit in this register is set, it enables Port {0..17} Error Rate CSR.ERR_RATE_CNTR to increment. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 428: Lane {0

    Note: The actual bit numbering of the encoded value is ERR_TYPE. 8:30 Reserved Reserved VALID 1 = Lane capture registers contain valid information. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 429: Lane {0

    16:23 CAPT_DATA 24:31 CAPT_DATA Reset Bits Name Description Type Value 0:31 CAPT_DATA Captured data as defined in Lane Events. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 430: Lane {0

    1 = Enable register adjustment of Tap 3 DFE coefficient Note: It is a programming error if this bit is set to 0 when RX DFE is enabled. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 431 Note: It is a programming error if this bit is set to 0 when RX DFE is enabled. 20:31 Reserved Reserved 0x555 CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 432: Lane {0

    Type Value Reserved Reserved TAP_OFFSET_CF DC differential offset cancellation. IDT recommends that this field 0b100000 not be changed from the reset default value. • Most significant bit is a sign bit, with 1 meaning “positive” and 0 meaning “negative” • Positive values range from 0b100000 (Positive 0) up to 0b111111 (+31) •...
  • Page 433 Lane {0..47} DFE 1 Register. The DFE DACs have no effect on the received signal if RX_DFE_DIS = 1 in the same register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 434: Broadcast Lane Control Register

    0b1001–1111 = Reserved Note: For 8-bit mode, 0b0110, 0b0111, and 0b1000 are supported for PRBS generation only. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 435 Loopback enable at the 8-bit boundary within Lane n 0 = Disable 1 = Enable For more information, see 8-bit Loopback Mode. Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 436 SPD[1:0] external pins. Note: Before changing this field value, see Port Reconfiguration Operations for the correct procedure to follow. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...
  • Page 437 Note: Changing the state of the LANE_DIS bit will require a re-initialization or reset. Before changing this field value, see Port Reconfiguration Operations for the correct procedure to follow. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 438: Broadcast Lane Prbs Generator Seed Register

    0 must be set to 1 to guarantee proper pseudo-random generation. Note: The reset value of this broadcast register is irrelevant to device functionality. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 439: Broadcast Lane Error Detect Register

    (not applicable to the CPS-1848), and/or the connected lane transmitter and the training of the equalization in either the lane receiver or the connected lane transmitter through IDLE2 commands has not been completed.

  • Page 440: Broadcast Lane Error Rate Enable Register

    0 = Disable 1 = Enable capturing of loss of receiver descrambler synchronization while receiving scrambled control symbol and packet data. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 441: Broadcast Lane Attributes Capture Register

    Reset Bits Name Description Type Value 0:30 Reserved Reserved VALID 1 = The Lane capture registers contain valid information. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 442: Broadcast Lane Dfe 1 Register

    1 = Enable register adjustment of Tap 4 DFE coefficient Note: It is a programming error if this bit is set to 0 when RX DFE is enabled. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 443 Note: It is a programming error if this bit is set to 0 when RX DFE is enabled. 20:31 Reserved Reserved CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 444: Broadcast Lane Dfe 2 Register

    {0..47} DFE 2 Register. CFG_EN Load coefficient outputs based on register fields. For more information, see Lane {0..47} DFE 2 Register. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA. Integrated Device Technology...

  • Page 445: Error Management Broadcast Registers

    Bits Name Description Type Value IMP_SPEC_ERR 0 = Did not detect an IDT implementation-specific error 1 = Detected an IDT implementation-specific error Reserved Reserved CS_CRC_ERR 0 = Did not detect a control symbol with a bad CRC 1 = Detected a control symbol with a bad CRC...
  • Page 446 1 = Detected an unsolicited acknowledgement control symbol. LINK_TIMEOUT 0 = Did not detect a link timeout error 1 = Detected a link timeout error CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 447: Broadcast Port Error Rate Enable Register

    Name Description Type Value IMP_SPEC_ERR_ 0 = Disable the capture of IDT implementation-specific errors. 1 = Enable the capture of IDT implementation-specific errors. Reserved Reserved CS_CRC_ERR_EN 0 = Disable the capture of a control symbol with bad CRC. 1 = Enable the capture of a control symbol with bad CRC.
  • Page 448 Note: This does not include packet-not-accept control symbols. LINK_TIMEOUT_E 0 = Disable the capture of link timeout errors. 1 = Enable the capture of link timeout errors. CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.

  • Page 449: References

    • IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks • The I C-Bus Specification (v 2.1), January 2000, Philips CPS-1848 User Manual June 2, 2014 Formal Status This document is confidential and is subject to an NDA.
  • Page 450 The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

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