Switch Fundamental Reset - IDT 89HPES64H16G2 User Manual

IDT Reset and Initialization
Notes
PES64H16G2 User Manual
Signal
P89MERGEN
P1011MERGEN
P1213MERGEN
P1415MERGEN
RSTHALT
SSMBADDR[5,3:1]
SWMODE[3:0]
Table 5.2 Boot Configuration Vector Signals (Part 2 of 2)

Switch Fundamental Reset

A switch fundamental reset may be cold or warm. A cold switch fundamental reset occurs following a
device being powered-on and assertion of the global reset (PERSTN) signal. A warm switch fundamental
reset occurs when a switch fundamental reset is initiated while power remains applied. The PES64H16G2
behaves in the same manner regardless of whether the switch fundamental reset is cold or warm.
A switch fundamental reset may be initiated by any of the following conditions.
– A cold switch fundamental reset initiated by application of power (i.e., a power-on) followed by
assertion of the global reset (PERSTN) signal.
– A warm switch fundamental reset initiated by assertion of PERSTN while power remains applied.
When a switch fundamental reset is initiated, the following sequence is executed.
1. Wait for the switch fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration vector signals shown in Table 5.2.
3. All registers are initialized to their default value.
4. The Register Unlock (REGUNLOCK) bit is set in the Switch Control (SWCTL) register.
5. The on-chip PLL and SerDes are initialized (i.e., PLL lock).
6. The master SMBus operating frequency is determined by examining the MSMBMODE state
sampled in the boot configuration vector. The master SMBus interface is initialized. The master
SMBus address is specified by the MSMBADDR[4:1] bits in the boot configuration vector.
7. The slave SMBus is taken out of reset and initialized. The slave SMBus address is specified by the
SSMBADDR[5,3:1] signals in the boot configuration vector.
8. Within 20 ms after the switch fundamental reset condition clears, the reset signal to the stacks is
negated and link training begins on all ports. While link training takes place, execution of the reset
sequence continues.
May Be
Overridden
N Ports 8 and 9 Merge.
This pin specifies whether ports 8 and 9 are merged.
N Ports 10 and 11 Merge.
This pin specifies whether ports 10 and 11 are merged.
N Ports 12 and 13 Merge.
This pin specifies whether ports 12 and 13 are merged.
N Ports 14 and 15 Merge.
This pin specifies whether ports 14 and 15 are merged.
Y Reset Halt.
When this pin is asserted during a switch fundamental reset
sequence, the PES64H16G2 remains in a reset state with the
Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal
device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the SWCTL register by
an SMBus master.
N Slave SMBus Address.
SMBus address of the switch on the slave SMBus.
N Switch Mode.
These pins specify the switch operating mode.
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Name/Description
April 5, 2013