Reset And Initialization; Introduction; Table 5.1 Pes64H16G2 Reset Precedence - IDT 89HPES64H16G2 User Manual

Notes
PES64H16G2 User Manual
®

Introduction

This chapter describes the PES64H16G2 resets and initialization. There are two classes of
PES64H16G2 resets. The first is a switch fundamental reset which is the reset used to initialize the entire
device. The second class is referred to as partition resets. This class has multiple sub-categories. Partition
resets are associated with a specific PES64H16G2 switch partition and corresponds to those resets defined
in the PCI express base specification. Switch resets are described in section Switch Fundamental Reset on
page 5-3 while partition resets are described in section Partition Resets on page 5-8.
When multiple resets are initiated concurrently, the precedence shown in Table 6.1 is used to determine
which one is acted upon.
– Reset types and causes are described in detail in the following sections.
• A partition reset affects the partition and ports associated with that partition.
• A switch fundamental reset affects the entire device
• A port reset affects only that one port
– When a high priority and low priority reset are initiated concurrently and the condition causing the
high priority reset ends prior to that causing the low priority reset, then the device/partition/port
immediately transitions to the reset associated with low priority reset condition.
• If the high priority and low priority resets share the same reset type, then the device/partition/
port remains in the corresponding reset when the high priority reset condition ends.
• If the high priority and low priority reset have different reset types, then the device/partition/port
transitions to the low priority reset type when the high priority reset condition ends.
Priority
1 Switch fundamental reset
(Highest)
2 Port mode change reset
3 Partition fundamental
reset
4 Partition fundamental
reset
5 Partition hot reset
6 Partition hot reset
7 Partition upstream sec-
ondary bus reset
8 Partition downstream sec-
(Lowest) ondary bus reset
Registers and fields designated as Switch Sticky (SWSticky) take on their initial value as a result of the
following resets. Other resets have no effect on registers and fields with this designation.
– Switch Fundamental Reset

Reset and Initialization

Reset Type
Global reset pin (PERSTN) assertion
Port operating mode change and OMA field set to port
reset in the corresponding SWPORTxCTL register
Assertion of partition fundamental reset pin (PARTxPER-
STN)
Directed by STATE field value in SWPARTxCTL register
Reception of TS1 ordered sets on upstream port indicat-
ing a hot reset
Data link layer of the upstream port transitioning to
DL_Down state
Setting of the SRESET bit in the partition's upstream port
PCI-to-PCI bridge BCTL register
Setting of the SRESET bit in the in the corresponding
port's PCI-to-PCI bridge BCTL register

Table 5.1 PES64H16G2 Reset Precedence

5 - 1
Chapter 5
Reset cause
April 5, 2013