Table 4.1 Initial Port Clocking Mode And Slot Clock Configuration State - IDT 89HPES64H16G2 User Manual

IDT Clocking
Notes
PES64H16G2 User Manual
advertisement of whether or not the port uses the same reference clock source as the link partner. A one in
the SCLK field indicates that the port and its link partner use the same reference clock source. This is
defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field
indicates that the port and its link partner do not use the same reference clock source.
CLKMODE[1:0] Value in
Boot Configuration Vector

Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State

Port 0
SCLK
0 0
1 1
2 0
3 1
4 - 2
SCLK for Ports other
than Port 0
0
0
1
1
April 5, 2013