Table 1.8 System Pins - IDT 89HPES64H16G2 User Manual

IDT PES64H16G2 Device Overview
Notes
PES64H16G2 User Manual
Signal Type
GPIO[29] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: HP2PFN
1st Alternate function pin type: Input
1st Alternate function: Hot Plug Signal Group 2 Power Fault Input.
2nd Alternate function pin name: P4ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 4 Link Active Status Output.
GPIO[30] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: HP2PWRGDN
1st Alternate function pin type: Input
1st Alternate function: Hot Plug Signal Group 2 Power Good Input.
2nd Alternate function pin name: P5LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 5 Link Up Status Output.
GPIO[31] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: HP2MRLN
1st Alternate function pin type: Input
1st Alternate function: Hot Plug Signal Group 2 Manually Operated Reten-
tion Latch Input.
2nd Alternate function pin name: P5ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 5 Link Active Status Output.
Table 1.7 General Purpose I/O Pins (Part 5 of 5)
Signal Type
CLKMODE[1:0] Clock Mode. These signals determine the port clocking mode used by
ports of the device.
GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of
the GCLKP and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. Refer to section Port Merging on page 5-7 for details.
When this pin is high, port 0 and port 1 are not merged, and each operates
as a single x4 port.
P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port
2. Refer to section Port Merging on page 5-7 for details.
When this pin is high, port 2 and port 3 are not merged, and each operates
as a single x4 port.
1 - 13
Name/Description
Name/Description
Table 1.8 System Pins (Part 1 of 3)
April 5, 2013