Logic Diagram - IDT 89HPES64H16G2 User Manual

IDT PES64H16G2 Device Overview

Logic Diagram

Global
Reference Clocks
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 1
PCI Express
Switch
SerDes Input
Port 15
Master
SMBus Interface
Slave
SMBus Interface
System
Pins
PES64H16G2 User Manual
GCLKN[1:0]
GCLKP[1:0]
GCLKFSEL
PE00RP[3:0]
PE00RN[3:0]
PE01RP[3:0]
PE01RN[3:0]
PE15RP[3:0]
PE15RN[3:0]
PES64H16G2
4
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
MSMBSMODE
2
CLKMODE[1:0]
RSTHALT
PERSTN
4
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1011MERGEN
P1213MERGEN
P1415MERGEN
Figure 1.2 PES64H16G2 Logic Diagram
PE00TP[3:0]
PE00TN3:[0]
PE01TP[3:0]
PE01TN[3:0]
PE15TP[3:0]
PE15TN[3:0]
32
GPIO[31:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
REFRES[15:0]
REFRESPLL
V CORE
DD
V I/O
DD
V PEA
DD
V PEHA
DD
V
SS
V PETA
DD
1 - 5
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Output
Port 15
General Purpose
I/O
JTAG Pins
SerDes
Reference
Resistors
Power/Ground
April 5, 2013