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Noise eliminator
INT0/P61
Selector
Φ
Note Even if f
/64 is selected, the HALT mode cannot be released by INT0.
X
<1> Narrow than sampling cycle
(t
)
SMP
Shaped output
<2> 1 to 2 times wider than
sampling cycle
(a)
Shaped output
(b)
Shaped output
<3> More than two times wider
than sampling clock
Shaped output
Remark t
= t
or 64/f
SMP
CY
194
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS
Figure 7-4. Configuration of INT0
f
/64
X
Input buffer
Internal bus
Figure 7-5. I/O Timing of Noise Eliminator
t
SMP
L
INT0
"L"
H
INT0
L
INT0
"L"
H
INT0
X
User's Manual U10676EJ3V0UM
Edge
detector
IM02
IM00, IM01
IM03
Specifies edge to be detected.
IM0
Selects sampling clock.
4
t
t
SMP
SMP
L
Eliminated as noise
H
L
H
L
Eliminated as noise
H
INT0
(IRQ0 set signal)
t
t
SMP
SMP
L
L
L
L
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