8.1 Settings and Operating Statuses of Standby Mode
Instruction to be set
Operating status
Clock generator
Basic interval timer/
watchdog timer
Timer counter
External interrupt
CPU
Release signal
Note Operation is possible only when the noise eliminator is not selected (when IM02 = 1) by bit 2 of the edge
detection mode register (IM0).
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CHAPTER 8 STANDBY FUNCTION
Table 8-1. Operating Statuses in Standby Mode
STOP Mode
STOP instruction
Operation stopped
Operation stopped
Operation stopped
INT0 cannot operate
INT2 can only operate at KRn fall.
Operation stopped
• Reset signal
• Interrupt request signal from hardware
in which interrupt is enabled
• System reset signal (key return reset)
generated by KRn fall when KRREN
pin is 1
User's Manual U10676EJ3V0UM
HALT instruction
Only CPU clock Φ is stopped
(oscillation continues)
Operation possible
BT mode: Sets IRQBT at reference
WT mode: Generates reset signal
Operation possible
Note
• Reset signal
• Interrupt request signal from hardware
in which interrupt is enabled
HALT Mode
time intervals
when BT overflows