Setting Of Timer Counter Output Enable Flag; Setting Of Timer Counter Control Register - NEC PD754144 User Manual

(b) Timer counter control register (TC2)
In the CG mode, set the timer counter output enable flag (TOE1) and TC2 as shown in Figure 6-45 (for
the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register).
TOE1 is manipulated by a bit manipulation instruction. TC2 is manipulated by an 8-, 4-, or bit manipulation
instruction.
TOE1 and TC2 are cleared to 00H when the internal reset signal is asserted.
The flags shown by a solid line in the figure below are used in the CG mode.
Do not use the flags shown by a dotted line in the CG mode (clear these flags to 0).
Figure 6-45. Setting of Timer Counter Output Enable Flag
Address
FAAH TOE1
7 6
0 –
Remote controller output control flag
REMC
0
1
No return zero buffer flag
NRZB
No return zero flag
NRZ
0
1
162
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
Figure 6-46. Setting of Timer Counter Control Register
5 4 3
– – TOE2 REMC
Remote controller output
Outputs carrier pulse to PTO2 pin when NRZ = 1
Outputs high level to PTO2 pin when NRZ = 1
Area to store no return zero data to be output next. Transferred to NRZ
when timer counter (channel 1) interrupt occurs
Outputs low level to PTO2 pin (Carrier clock stopped)
Outputs carrier pulse to PTO2 pin
User's Manual U10676EJ3V0UM
Timer counter output enable flag (W)
0 Disabled
1 Enabled
Symbol
2 1 0
NRZB NRZ TC2
No return zero data