I/O Timing Of Digital I/O Port - NEC PD754144 User Manual

6.1.6 I/O timing of digital I/O port

Figure 6-12 shows the timing at which data is output to the output latch and the timing at which the pin data or
the data of the output latch is loaded to the internal bus.
Figure 6-13 shows the ON timing when an on-chip pull-up resistor connection is specified via software.
Instruction
execution
Input timing
Instruction
execution
Input timing
Instruction
execution
Output latch
(output pin)
Instruction
execution
Output latch
(output pin)
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
Figure 6-12. I/O Timing of Digital I/O Port
(a) When data is loaded by 1-machine-cycle instruction
Φ
0
(b) When data is loaded by 2-machine-cycle instruction
2 machine cycles
Manipulation instruction
(c) When data is latched by 1-machine-cycle instruction
(d) When data is latched by 2-machine-cycle instruction
Manipulation instruction
User's Manual U10676EJ3V0UM
1 machine cycle
Φ Φ Φ
1 2 3
Manipulation
instruction
Φ Φ Φ
0 1 2
Φ Φ
3 0
Manipulation
instruction
Φ
3
Φ
1
Φ Φ
0 1
101