Watchdog Flag (Wdf), Key Return Flag (Krf); Wdf Operation In Generating Each Signal; Wdf And Krf Contents Corresponding To Each Signal - NEC PD754144 User Manual

9.2 Watchdog Flag (WDF), Key Return Flag (KRF)

WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively.
The contents of WDF and KRF are undefined initially, but they are initialized to "0" by external RESET signal
generation.
WDF is cleared by a watchdog timer overflow signal, and KRF is set by a reset signal generated by the KRn
pin. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is
generated.
As WDF and KRF are cleared only by an external signal or instruction execution, once these flags are set, they
are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents
of WDF and KRF after the reset start operation by executing the SKTCLR instruction, etc.
Table 9-2 lists the contents of WDF and KRF corresponding to each signal. Figure 9-3 shows the WDF operation
in generating each signal, and Figure 9-4 shows the KRF operation in generating each signal.
Table 9-2. WDF and KRF Contents Corresponding to Each Signal
Hardware
Watchdog flag (WDF)
Key return flag (KRF)
Reset signal generation by
watchdog timer overflow
WDF
External RESET
Operation mode
Operation mode
CHAPTER 9 RESET FUNCTION
External RESET Reset Signal
Signal Generation Generation by Watch-
dog Timer Overflow
0 1
0 Hold
Figure 9-3. WDF Operation in Generating Each Signal
External RESET
signal generation
HALT Operation
mode mode
Internal reset operation
User's Manual U10676EJ3V0UM
Reset Signal WDF Clear
Generation by Instruction
KRn Input Execution
Hold 0
1 Hold
Reset signal generation by
watchdog timer overflow
HALT Operation
mode mode
Internal reset operation Internal reset operation
KRF Clear
Instruction
Execution
Hold
0
WDF clear
instruction
execution
HALT
mode
Operation mode
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