NEC PD754144 User Manual page 156

(3) Timer counter operation (at 16-bit)
The timer counter operates as follows.
Figure 6-42 shows the configuration when the timer counter operates.
<1> The count pulse (CP) is selected by timer counter mode registers TM1 and TM2 and is input to timer
counter count register T2. The overflow of T2 is input to count register T1.
<2> The contents of T1 are compared with those of timer counter modulo register TMOD1. When the contents
of these registers match, a match signal is generated.
<3> The contents of T2 are compared with those of timer counter modulo register TMOD2. When the contents
of these registers match, a match signal is generated.
<4> If the match signals in <2> and <3> overlap, interrupt request flag IRQT2 is set. At the same time, timer
out flip-flop TOUT F/F is inverted.
Figure 6-43 shows the operation timing of the timer counter operation.
The timer counter operation is usually started by the following procedure.
<1> Set the higher 8 bits of the number of counts indicated as 16 bits wide to TMOD1.
<2> Set the lower 8 bits of the number of counts indicated as 16 bits wide to TMOD2.
<3> Set the count pulse to TM1.
<4> Set the operation mode, count pulse, and start command to TM2.
Caution Be sure to set a value other than 00H to timer counter modulo register TMOD2.
Also, set "0" to IET1.
To use timer counter output pin PTO2, set the P32 pin as follows:
<1> Clear the output latch of P32.
<2> Set port 3 in the output mode.
<3> Disconnect the internal pull-up resistor from port 3.
<4> Set timer counter output enable flag TOE2 to 1.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
User's Manual U10676EJ3V0UM