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Figure No.
3-1
Selecting MBE = 0 Mode and MBE = 1 Mode ..................................................................................
3-2
Data Memory Configuration and Addressing Range for Each Addressing Mode ............................
3-3
Updating Address of Static RAM .......................................................................................................
3-4
Example of Using Register Banks .....................................................................................................
3-5
Configuration of General-Purpose Registers (4-Bit Processing) ......................................................
3-6
Configuration of General-Purpose Registers (8-Bit Processing) ......................................................
µ PD754244 I/O Map ...........................................................................................................................
3-7
4-1
Format of Stack Bank Select Register ...............................................................................................
4-2
Configuration of Program Counter .....................................................................................................
4-3
Program Memory Map ........................................................................................................................
4-4
Data Memory Map ..............................................................................................................................
4-5
Configuration of General-Purpose Register Area .............................................................................
4-6
Configuration of Register Pair ............................................................................................................
4-7
Accumulator ........................................................................................................................................
4-8
Stack Pointer and Stack Bank Selection Register Configuration .....................................................
4-9
Data Saved to Stack Memory (MkI Mode) .........................................................................................
4-10
Data Restored from Stack Memory (MkI Mode) ................................................................................
4-11
Data Saved to Stack Memory (MkII Mode) ........................................................................................
4-12
Data Restored from Stack Memory (MkII Mode) ...............................................................................
4-13
Configuration of Program Status Word ..............................................................................................
4-14
Configuration of Bank Select Register ...............................................................................................
5-1
Format of EEPROM Write Control Register ......................................................................................
5-2
EEPROM Write Control Register in EEPROM Read Manipulation ..................................................
5-3
EEPROM Write Control Register in EEPROM Write Manipulation ...................................................
6-1
Data Memory Address of Digital Ports ..............................................................................................
6-2
P3n Configuration (n = 0 to 2) ............................................................................................................
6-3
P33 Configuration ...............................................................................................................................
6-4
P60 Configuration ...............................................................................................................................
6-5
P61 Configuration ...............................................................................................................................
6-6
P62 Configuration ...............................................................................................................................
6-7
P63 Configuration ...............................................................................................................................
6-8
P7n Configuration (n = 0 to 3) ............................................................................................................
6-9
P80 Configuration ...............................................................................................................................
6-10
Format of Each Port Mode Register ..................................................................................................
6-11
Format of Pull-up Resistor Specification Register ............................................................................
6-12
I/O Timing of Digital I/O Port ..............................................................................................................
6-13
ON Timing of Internal Pull-up Resistor Connected via Software .....................................................
6-14
Block Diagram of Clock Generator .....................................................................................................
6-15
Format of Processor Clock Control Register .....................................................................................
6-16
RC Oscillation External Circuit ...........................................................................................................
6-17
Crystal/Ceramic Oscillation External Circuit ......................................................................................
LIST OF FIGURES (1/3)
Title
User's Manual U10676EJ3V0UM
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