Table Of Contents - NEC PD754144 User Manual

CHAPTER 1 GENERAL .....................................................................................................................
1.1 Functional Outline .............................................................................................................
1.2 Ordering Information .........................................................................................................
1.3 Differences Between Series Products ............................................................................
1.4 Block Diagram ....................................................................................................................
1.5 Pin Configuration (Top View) ............................................................................................
CHAPTER 2 PIN FUNCTIONS ..........................................................................................................
Pin Functions of µ PD754244 ............................................................................................
2.1
2.2 Description of Pin Functions ...........................................................................................
2.2.1 P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8) .......................................................
2.2.2 P70 to P73 (Port 7) ................................................................................................................
2.2.3 PTO0 to PTO2 .......................................................................................................................
2.2.4 INT0 ........................................................................................................................................
2.2.5 KR4 to KR7 ............................................................................................................................
2.2.6 KRREN ...................................................................................................................................
2.2.7 TH00 and TH01 .....................................................................................................................
2.2.8 AV
REF
CL1 and CL2 ( µ PD754144 only) ...........................................................................................
2.2.9
X1 and X2 ( µ PD754244 only) ...............................................................................................
2.2.10
2.2.11 RESET ....................................................................................................................................
2.2.12 IC ............................................................................................................................................
2.2.13 V ..........................................................................................................................................
DD
2.2.14 V ..........................................................................................................................................
SS
2.3 Pin I/O Circuits ...................................................................................................................
2.4 Processing of Unused Pins ..............................................................................................
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP ...........................................
3.1 Bank Configuration of Data Memory and Addressing Modes .....................................
3.1.1 Bank configuration of data memory ......................................................................................
3.1.2 Addressing mode of data memory ........................................................................................
3.2 Bank Configuration of General-Purpose Registers ......................................................
3.3 Memory-Mapped I/O ...........................................................................................................
CHAPTER 4 INTERNAL CPU FUNCTION .......................................................................................
4.1 Function to Select MkI and MkII Modes ..........................................................................
4.1.1 Difference between MkI and MkII modes .............................................................................
4.1.2 Setting stack bank select register (SBS) ..............................................................................
4.2 Program Counter (PC) .......................................................................................................
4.3 Program Memory (ROM) ....................................................................................................
4.4 Data Memory (RAM) ...........................................................................................................
4.4.1 Configuration of data memory ...............................................................................................
4.4.2 Specifying bank of data memory ..........................................................................................
4.5 General-Purpose Registers ..............................................................................................

TABLE OF CONTENTS

......................................................................................................................................
User's Manual U10676EJ3V0UM
17
18
19
19
20
21
24
24
26
26
26
26
27
27
27
27
28
28
28
28
29
29
29
30
31
32
32
32
34
45
50
60
60
60
61
62
63
65
65
66
69
9