Table 18. Pci Interrupt Routing/Sharing - Intel SE7520AF2 Technical Product Specification

Functional Architecture
3.4.2.1 Legacy Interrupt Routing
For PC-compatible mode, the ICH5-R provides two 82C59-compatible interrupt controllers. The
two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary
interrupt controller (standard PC configuration). A single interrupt signal is presented to the
processors, to which only one processor will respond for servicing. The ICH5-R contains
configuration registers that define which interrupt source logically maps to I/O APIC INTx pins.
Interrupts, both PCI and IRQ types, are handled by the ICH5-R. The ICH5-R then translates
these to the APIC bus. The numbers in the table below indicate the ICH5-R PCI interrupt input
pin to which the associated device interrupt (INTA, INTB, INTC, and INTD) is connected. The
ICH5-R' I/O APIC exists on the I/O APIC bus with the processors.
Interrupt
USB Controller 1 and 4
USB Controller 1
USB Controller 2
USB Controller 3, IDE, SATA
Video
SIO
Legacy IDE
82546GB 1
82546GB 2
SCSI Controller 1
SCSI Controller 2
Slot 1 (PCI-X 64/133)
Slot 3 (PCI EXP x4)
Slot 4 (PCI EXP x8)
Slot 5 (PCI-X 64/133)
Slot 6 (PCI-X 64/100)
Slot 6 (Upper slot of optional 2-
slot riser)
Slot 7 (Lower slot of optional 2-
slot riser)
3.4.2.2 APIC Interrupt Routing
For APIC mode, the Intel® Server Board SE7520AF2 interrupt architecture incorporates three
Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor.
The Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to
the ISA compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding
to the interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus
minimizes interrupt latency time for compatibility interrupt sources. The I/O APICs can also
supply greater than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC
clock and two bidirectional data lines.
56

Table 18. PCI Interrupt Routing/Sharing

INT A
ICH5R_PIRQA
ICH5R_PIRQH
ICH5R_PIRQD
ICH5R_PIRQC
ICH5R_PIRQB
ICH5R_SERIRQ
ICH5R_IRQ14
PXH_PBIRQ4
PXH_PBIRQ5
IOP_XINT0
IOP_XINT1
IOP_XINT4 IOP_XINT5
NA NA
NA NA
PXH_PAIRQ0 PXH_PAIRQ1
PXH_PBIRQ0 PXH_PBIRQ1
PXH_PBIRQ0 PXH_PBIRQ1
PXH_PBIRQ0 PXH_PBIRQ1
Intel order number C77866-003
Intel® Server Board SE7520AF2 TPS
INT B INT C
IOP_XINT6
NA
NA
PXH_PAIRQ2
PXH_PBIRQ2
PXH_PBIRQ2
PXH_PBIRQ2
INT D
IOP_XINT7
NA
NA
PXH_PAIRQ3
PXH_PBIRQ3
PXH_PBIRQ3
PXH_PBIRQ3
Revision 1.2